[llvm] Revert "[CodeGen] Use RegisterClassInfo for remaining allocation-order users" (PR #221749)

[Michael Halkenhäuser via llvm-commits]

mhalk wrote:

> I'd guess this is an incidental code change (or is WWM reservation related)

@arsenm Yes. AFAICT it's the latter, in the case I am looking at:
`AMDGPUReserveWWMRegs` reserves a VGPR and clears the per-lane VGPR mask, but commits neither to `MachineRegisterInfo` nor to the shared `RegisterClassInfo`.

So `AMDGPURewriteAGPRCopyMFMA` is handed a stale allocation order that still contains the reserved register and eventually assigns it.
That is tripping the assertion we see in our CI:
`Assertion '!getRegInfo().isReserved(physReg) && "Attempt to map virtReg to a reserved physReg"' failed.`
Note that the assertion is the only thing catching this: without assertions the register really is handed out, and the SGPRs spilled to it get clobbered.

Hence, my current approach fixes the issue related to [this TODO](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp#L69-L70): by adopting and maintaining the shared RCI analysis in the pass rather than abandoning it.

> @ronlieb lmk if I can help debug the failures or make PR changes again once its fixed

Thanks for the offer, I'll let you know if I need further support on this.
I should have a fix with lit test at hand shortly -- which in turn should allow a re-land of your contribution.

https://github.com/llvm/llvm-project/pull/221749