[llvm] [AMDGPU] Fix GlobalISel VGPR-to-VCC lowering types (PR #220987)
Keshav Vinayak Jha via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 7 06:19:36 PDT 2026
https://github.com/keshavvinayak01 updated https://github.com/llvm/llvm-project/pull/220987
>From 6132ca761b9c5417676497124536d0b7d9089e42 Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Thu, 3 Sep 2026 22:01:04 +0530
Subject: [PATCH 1/4] [AMDGPU] Use integer LLTs for VGPR to VCC lowering
Convert untyped scalar VGPR sources to a same-width integer LLT before building the generic mask and compare operations. This lets the generated instruction selector match the helper-created operations.
Add register-bank coverage for i16, i32, and i64 along with an end-to-end regression for the reported GlobalISel failure.
Co-authored-by: GPT-5 Codex <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 4 +++
.../CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll | 26 +++++++++++++++++
.../AMDGPU/GlobalISel/regbankselect-trunc.mir | 29 +++++++++++--------
3 files changed, 47 insertions(+), 12 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 5e65097cc6a7d..5988bd594141a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1483,6 +1483,10 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
case VgprToVccCopy: {
Register Src = MI.getOperand(1).getReg();
LLT Ty = MRI.getType(Src);
+ if (Ty.isAnyScalar()) {
+ Ty = LLT::integer(Ty.getSizeInBits());
+ Src = B.buildCopy({VgprRB, Ty}, Src).getReg(0);
+ }
// Take lowest bit from each lane and put it in lane mask.
// Lowering via compare, but we need to clean high bits first as compare
// compares all bits in register.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll
new file mode 100644
index 0000000000000..0fa27039a060d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll
@@ -0,0 +1,26 @@
+; RUN: llc -O0 -global-isel -mtriple=amdgpu9.50-amd-amdhsa -verify-machineinstrs -filetype=null %s
+; RUN: llc -O2 -global-isel -mtriple=amdgpu9.50-amd-amdhsa -verify-machineinstrs -filetype=null %s
+; RUN: llc -O2 -global-isel -mtriple=amdgpu9.0a-amd-amdhsa -verify-machineinstrs -filetype=null %s
+
+; Make sure lowering the divergent low-bit test does not leave an untyped
+; VGPR G_AND for instruction selection.
+
+define amdgpu_kernel void @and_vgpr_s32(i32 %lane.bit) {
+entry:
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %lane.bit1 = and i32 %tid, 1
+ %cond = icmp eq i32 %lane.bit1, 0
+ br i1 %cond, label %common.ret, label %else
+
+common.ret:
+ ret void
+
+else:
+ %ins = insertelement <4 x i32> zeroinitializer, i32 %lane.bit, i32 0
+ %ins1 = insertelement <4 x i32> %ins, i32 0, i32 0
+ %ins2 = insertelement <4 x i32> %ins1, i32 0, i32 0
+ %ins3 = insertelement <4 x i32> %ins2, i32 0, i32 0
+ br label %common.ret
+}
+
+declare noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
index d9748f938e9a1..512c4ebe941c2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX6 %s
# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX8 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize,instruction-select" \
+# RUN: -global-isel-abort=1 -verify-machineinstrs -o /dev/null %s
---
name: trunc_i64_to_i32_s
@@ -62,14 +64,15 @@ body: |
; GFX: liveins: $vgpr0_vgpr1
; GFX-NEXT: {{ $}}
; GFX-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; GFX-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; GFX-NEXT: [[COPY1:%[0-9]+]]:vgpr(i64) = COPY [[COPY]](s64)
+ ; GFX-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[COPY1]](i64)
; GFX-NEXT: [[C:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 1
; GFX-NEXT: [[AND:%[0-9]+]]:vgpr(i32) = G_AND [[UV]], [[C]]
; GFX-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
; GFX-NEXT: [[AND1:%[0-9]+]]:vgpr(i32) = G_AND [[UV1]], [[C1]]
- ; GFX-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[AND]](i32), [[AND1]](i32)
- ; GFX-NEXT: [[C2:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 0
- ; GFX-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[MV]](s64), [[C2]]
+ ; GFX-NEXT: [[MV:%[0-9]+]]:vgpr(i64) = G_MERGE_VALUES [[AND]](i32), [[AND1]](i32)
+ ; GFX-NEXT: [[C2:%[0-9]+]]:vgpr(i64) = G_CONSTANT i64 0
+ ; GFX-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[MV]](i64), [[C2]]
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s1) = G_TRUNC %0
...
@@ -103,10 +106,11 @@ body: |
; GFX: liveins: $vgpr0
; GFX-NEXT: {{ $}}
; GFX-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
- ; GFX-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
- ; GFX-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
- ; GFX-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
+ ; GFX-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY [[COPY]](s32)
+ ; GFX-NEXT: [[C:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 1
+ ; GFX-NEXT: [[AND:%[0-9]+]]:vgpr(i32) = G_AND [[COPY1]], [[C]]
+ ; GFX-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
+ ; GFX-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](i32), [[C1]]
%0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0
...
@@ -134,10 +138,11 @@ body: |
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[C:%[0-9]+]]:vgpr(s16) = G_CONSTANT i16 1
- ; GFX8-NEXT: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[TRUNC]], [[C]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:vgpr(s16) = G_CONSTANT i16 0
- ; GFX8-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s16), [[C1]]
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr(i16) = COPY [[TRUNC]](s16)
+ ; GFX8-NEXT: [[C:%[0-9]+]]:vgpr(i16) = G_CONSTANT i16 1
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:vgpr(i16) = G_AND [[COPY1]], [[C]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:vgpr(i16) = G_CONSTANT i16 0
+ ; GFX8-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](i16), [[C1]]
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s1) = G_TRUNC %1
>From f7cea3f6863a1f2e4eef50671f4811fa08b62c03 Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Thu, 3 Sep 2026 22:11:40 +0530
Subject: [PATCH 2/4] [AMDGPU] Remove redundant test comment
Co-authored-by: GPT-5 Codex <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll | 3 ---
1 file changed, 3 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll
index 0fa27039a060d..c08e1975cabc0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll
@@ -2,9 +2,6 @@
; RUN: llc -O2 -global-isel -mtriple=amdgpu9.50-amd-amdhsa -verify-machineinstrs -filetype=null %s
; RUN: llc -O2 -global-isel -mtriple=amdgpu9.0a-amd-amdhsa -verify-machineinstrs -filetype=null %s
-; Make sure lowering the divergent low-bit test does not leave an untyped
-; VGPR G_AND for instruction selection.
-
define amdgpu_kernel void @and_vgpr_s32(i32 %lane.bit) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
>From e75262f8a892a8c281e0067db241bddf36af6168 Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Mon, 7 Sep 2026 18:39:15 +0530
Subject: [PATCH 3/4] [AMDGPU] Avoid typed copies in VGPR to VCC lowering
Construct integer-typed temporary operations directly without inserting a copy. Consolidate the regression into the existing divergent control-flow test and check the generated assembly.
Co-authored-by: GPT-5 Codex <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 6 +----
.../CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll | 23 ----------------
.../GlobalISel/divergent-control-flow.ll | 26 +++++++++++++++++++
.../AMDGPU/GlobalISel/regbankselect-trunc.mir | 11 +++-----
4 files changed, 30 insertions(+), 36 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 5988bd594141a..1f89b3c22f722 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1482,11 +1482,7 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
}
case VgprToVccCopy: {
Register Src = MI.getOperand(1).getReg();
- LLT Ty = MRI.getType(Src);
- if (Ty.isAnyScalar()) {
- Ty = LLT::integer(Ty.getSizeInBits());
- Src = B.buildCopy({VgprRB, Ty}, Src).getReg(0);
- }
+ LLT Ty = LLT::integer(MRI.getType(Src).getSizeInBits());
// Take lowest bit from each lane and put it in lane mask.
// Lowering via compare, but we need to clean high bits first as compare
// compares all bits in register.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll
deleted file mode 100644
index c08e1975cabc0..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/and-vgpr-s32.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llc -O0 -global-isel -mtriple=amdgpu9.50-amd-amdhsa -verify-machineinstrs -filetype=null %s
-; RUN: llc -O2 -global-isel -mtriple=amdgpu9.50-amd-amdhsa -verify-machineinstrs -filetype=null %s
-; RUN: llc -O2 -global-isel -mtriple=amdgpu9.0a-amd-amdhsa -verify-machineinstrs -filetype=null %s
-
-define amdgpu_kernel void @and_vgpr_s32(i32 %lane.bit) {
-entry:
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %lane.bit1 = and i32 %tid, 1
- %cond = icmp eq i32 %lane.bit1, 0
- br i1 %cond, label %common.ret, label %else
-
-common.ret:
- ret void
-
-else:
- %ins = insertelement <4 x i32> zeroinitializer, i32 %lane.bit, i32 0
- %ins1 = insertelement <4 x i32> %ins, i32 0, i32 0
- %ins2 = insertelement <4 x i32> %ins1, i32 0, i32 0
- %ins3 = insertelement <4 x i32> %ins2, i32 0, i32 0
- br label %common.ret
-}
-
-declare noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
index e32f09a38c83b..04388838c8212 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
@@ -1,5 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s
+; RUN: llc -O0 -global-isel -mtriple=amdgpu9.50-amd-amdhsa < %s | FileCheck --check-prefix=GFX9-AND %s
+; RUN: llc -global-isel -mtriple=amdgpu9.50-amd-amdhsa < %s | FileCheck --check-prefix=GFX9-AND %s
+; RUN: llc -global-isel -mtriple=amdgpu9.0a-amd-amdhsa < %s | FileCheck --check-prefix=GFX9-AND %s
; Make sure the branch targets are correct after lowering llvm.amdgcn.if
@@ -262,4 +265,27 @@ bb9:
ret void
}
+define amdgpu_kernel void @and_vgpr_s32(i32 %lane.bit) {
+; GFX9-AND-LABEL: and_vgpr_s32:
+; GFX9-AND: ; %bb.0: ; %entry
+; GFX9-AND: v_and_b32_{{e32|e64}}
+; GFX9-AND: v_cmp_ne_u32_{{e32|e64}}
+; GFX9-AND: s_endpgm
+entry:
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %lane.bit1 = and i32 %tid, 1
+ %cond = icmp eq i32 %lane.bit1, 0
+ br i1 %cond, label %common.ret, label %else
+
+common.ret:
+ ret void
+
+else:
+ %ins = insertelement <4 x i32> zeroinitializer, i32 %lane.bit, i32 0
+ %ins1 = insertelement <4 x i32> %ins, i32 0, i32 0
+ %ins2 = insertelement <4 x i32> %ins1, i32 0, i32 0
+ %ins3 = insertelement <4 x i32> %ins2, i32 0, i32 0
+ br label %common.ret
+}
+
declare i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
index 512c4ebe941c2..59201971db9b9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
@@ -1,8 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX6 %s
# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX,GFX8 %s
-# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-reg-bank-select,amdgpu-reg-bank-legalize,instruction-select" \
-# RUN: -global-isel-abort=1 -verify-machineinstrs -o /dev/null %s
---
name: trunc_i64_to_i32_s
@@ -64,8 +62,7 @@ body: |
; GFX: liveins: $vgpr0_vgpr1
; GFX-NEXT: {{ $}}
; GFX-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; GFX-NEXT: [[COPY1:%[0-9]+]]:vgpr(i64) = COPY [[COPY]](s64)
- ; GFX-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[COPY1]](i64)
+ ; GFX-NEXT: [[UV:%[0-9]+]]:vgpr(i32), [[UV1:%[0-9]+]]:vgpr(i32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX-NEXT: [[C:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 1
; GFX-NEXT: [[AND:%[0-9]+]]:vgpr(i32) = G_AND [[UV]], [[C]]
; GFX-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
@@ -106,9 +103,8 @@ body: |
; GFX: liveins: $vgpr0
; GFX-NEXT: {{ $}}
; GFX-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY [[COPY]](s32)
; GFX-NEXT: [[C:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 1
- ; GFX-NEXT: [[AND:%[0-9]+]]:vgpr(i32) = G_AND [[COPY1]], [[C]]
+ ; GFX-NEXT: [[AND:%[0-9]+]]:vgpr(i32) = G_AND [[COPY]], [[C]]
; GFX-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0
; GFX-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](i32), [[C1]]
%0:_(s32) = COPY $vgpr0
@@ -138,9 +134,8 @@ body: |
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr(i16) = COPY [[TRUNC]](s16)
; GFX8-NEXT: [[C:%[0-9]+]]:vgpr(i16) = G_CONSTANT i16 1
- ; GFX8-NEXT: [[AND:%[0-9]+]]:vgpr(i16) = G_AND [[COPY1]], [[C]]
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:vgpr(i16) = G_AND [[TRUNC]], [[C]]
; GFX8-NEXT: [[C1:%[0-9]+]]:vgpr(i16) = G_CONSTANT i16 0
; GFX8-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](i16), [[C1]]
%0:_(s32) = COPY $vgpr0
>From dfaef5b85087dfd0fe157c0ca8b88be4418c9b25 Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Mon, 7 Sep 2026 18:48:57 +0530
Subject: [PATCH 4/4] [AMDGPU] Remove redundant GlobalISel test runs
Keep one affected gfx950 configuration that exercises the selector regression.
Co-authored-by: GPT-5 Codex <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
index 04388838c8212..3182057fc47bd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s
-; RUN: llc -O0 -global-isel -mtriple=amdgpu9.50-amd-amdhsa < %s | FileCheck --check-prefix=GFX9-AND %s
; RUN: llc -global-isel -mtriple=amdgpu9.50-amd-amdhsa < %s | FileCheck --check-prefix=GFX9-AND %s
-; RUN: llc -global-isel -mtriple=amdgpu9.0a-amd-amdhsa < %s | FileCheck --check-prefix=GFX9-AND %s
; Make sure the branch targets are correct after lowering llvm.amdgcn.if
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