[llvm] [AArch64][NEON] Fold insert(zero, extract(X, 0), 0) -> X when X is known to zero lanes 1-N (PR #213940)

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CarolineConcatto wrote:

Hello @paulwalker-arm,
I've updated the commit message:

> Limit this change to matching input and result vector types. Mixed vector
> sizes and scalar conversions are not part of this PR.
The main reason was that a code similar to the one bellow in C did not  have  optimal codegen:
```
float64x2_t minIntoVec64(const float64x2_t v) {
    const float64x2_t res = {vmaxvq_f64(v), 0};
    return res;
}
```
In the examples the conversion is to the same size.

https://github.com/llvm/llvm-project/pull/213940