[llvm] [CodeGen] Expand unsupported interleave to shuffles (PR #210494)
Kamlesh Kumar via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 7 05:20:26 PDT 2026
https://github.com/kamleshbhalui updated https://github.com/llvm/llvm-project/pull/210494
>From e71f2c0170833c7a4b3db31e9cd0c4d76e88f614 Mon Sep 17 00:00:00 2001
From: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: Fri, 4 Sep 2026 11:58:46 +0000
Subject: [PATCH 1/2] [CodeGen] Add generic expand for interleave ops
Added generic expand for unsupported vector_(de)interleave
operation to prevent crashes.
Also unify the expand fragmented at multiple places to vector legalize.
---
llvm/include/llvm/CodeGen/TargetLowering.h | 8 +
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 53 +-
.../SelectionDAG/LegalizeVectorOps.cpp | 13 +
.../SelectionDAG/SelectionDAGBuilder.cpp | 22 -
.../CodeGen/SelectionDAG/TargetLowering.cpp | 122 +
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +-
.../aarch64-interleaved-access-w-undef.ll | 103 +-
.../AArch64/aarch64-interleaved-ld-combine.ll | 71 +-
llvm/test/CodeGen/AArch64/binopshuffles.ll | 73 +-
.../complex-deinterleaving-multiuses.ll | 288 +-
.../complex-deinterleaving-reductions.ll | 16 +-
.../AArch64/fixed-deinterleave-intrinsics.ll | 866 +-
.../AArch64/fixed-length-sve-interleave.ll | 19 +-
.../AArch64/fixed-vector-deinterleave.ll | 131 +-
.../fixed-vector-interleave-odd-factor.ll | 132 +
.../AArch64/fixed-vector-interleave.ll | 100 +-
.../fixed_masked_deinterleaved_loads.ll | 14 +-
.../fixed_masked_interleaved_stores.ll | 10 +-
.../CodeGen/AArch64/interleaved-accesses.ll | 89 +-
.../AArch64/nontemporal-load-interleaved.ll | 522 +-
.../nontemporal-store-interleaved-optsize.ll | 183 +-
.../AArch64/nontemporal-store-interleaved.ll | 644 +-
.../AArch64/sve-fixed-length-shuffles.ll | 26 +-
.../AArch64/sve-interleaved-accesses.ll | 136 +-
...-streaming-mode-fixed-length-interleave.ll | 128 +-
...-streaming-mode-fixed-length-ld2-alloca.ll | 8 +-
...sve-streaming-mode-fixed-length-shuffle.ll | 15 +-
.../AArch64/sve-vector-deinterleave.ll | 32 +-
.../AArch64/sve-vector-interleave-widen.ll | 16 +-
.../CodeGen/AArch64/sve-vector-interleave.ll | 32 +-
llvm/test/CodeGen/AArch64/tbl-loops.ll | 231 +-
.../AArch64/vector-deinterleave-load.ll | 39 +-
.../AArch64/vector-interleave-store.ll | 90 +-
llvm/test/CodeGen/AArch64/vldn_shuffle.ll | 243 +-
.../rvv/fixed-vectors-interleave-store.ll | 59 +-
.../RISCV/rvv/vector-deinterleave-fixed.ll | 554 +-
.../RISCV/rvv/vector-deinterleave-load.ll | 29 +-
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 548 +-
.../RISCV/rvv/vector-interleave-fixed.ll | 1025 +-
.../CodeGen/RISCV/rvv/vector-interleave.ll | 11581 +++++++++-------
.../RISCV/rvv/vp-vector-interleaved-access.ll | 28 +-
.../X86/vector-deinterleave-intrinsics.ll | 386 +
.../X86/vector-interleave-intrinsics.ll | 274 +
43 files changed, 9628 insertions(+), 9335 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll
create mode 100644 llvm/test/CodeGen/X86/vector-deinterleave-intrinsics.ll
create mode 100644 llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 69f5e0e4e3011..55c51722ee7ab 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -6027,6 +6027,14 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
/// method accepts vectors as its arguments.
SDValue expandVectorSplice(SDNode *Node, SelectionDAG &DAG) const;
+ /// Expand a VECTOR_INTERLEAVE without introducing wider vector types.
+ void expandVectorInterleave(SDNode *Node, SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const;
+
+ /// Expand a VECTOR_DEINTERLEAVE without introducing wider vector types.
+ void expandVectorDeinterleave(SDNode *Node, SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const;
+
/// Expand a vector VECTOR_COMPRESS into a sequence of extract element, store
/// temporarily, advance store position, before re-loading the final vector.
SDValue expandVECTOR_COMPRESS(SDNode *Node, SelectionDAG &DAG) const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index eadc09a459e25..3c256d7c21d5e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3790,57 +3790,12 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Results.push_back(TLI.expandVectorSplice(Node, DAG));
break;
}
- case ISD::VECTOR_DEINTERLEAVE: {
- unsigned Factor = Node->getNumOperands();
- if (Factor <= 2 || Factor % 2 != 0)
- break;
- SmallVector<SDValue, 8> Ops(Node->ops());
- EVT VecVT = Node->getValueType(0);
- SmallVector<EVT> HalfVTs(Factor / 2, VecVT);
- // Deinterleave at Factor/2 so each result contains two factors interleaved:
- // a0b0 c0d0 a1b1 c1d1 -> [a0c0 b0d0] [a1c1 b1d1]
- SDValue L = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, dl, HalfVTs,
- ArrayRef(Ops).take_front(Factor / 2));
- SDValue R = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, dl, HalfVTs,
- ArrayRef(Ops).take_back(Factor / 2));
- Results.resize(Factor);
- // Deinterleave the 2 factors out:
- // [a0c0 a1c1] [b0d0 b1d1] -> a0a1 b0b1 c0c1 d0d1
- for (unsigned I = 0; I < Factor / 2; I++) {
- SDValue Deinterleave =
- DAG.getNode(ISD::VECTOR_DEINTERLEAVE, dl, {VecVT, VecVT},
- {L.getValue(I), R.getValue(I)});
- Results[I] = Deinterleave.getValue(0);
- Results[I + Factor / 2] = Deinterleave.getValue(1);
- }
+ case ISD::VECTOR_INTERLEAVE:
+ TLI.expandVectorInterleave(Node, Results, DAG);
break;
- }
- case ISD::VECTOR_INTERLEAVE: {
- unsigned Factor = Node->getNumOperands();
- if (Factor <= 2 || Factor % 2 != 0)
- break;
- EVT VecVT = Node->getValueType(0);
- SmallVector<EVT> HalfVTs(Factor / 2, VecVT);
- SmallVector<SDValue, 8> LOps, ROps;
- // Interleave so we have 2 factors per result:
- // a0a1 b0b1 c0c1 d0d1 -> [a0c0 b0d0] [a1c1 b1d1]
- for (unsigned I = 0; I < Factor / 2; I++) {
- SDValue Interleave =
- DAG.getNode(ISD::VECTOR_INTERLEAVE, dl, {VecVT, VecVT},
- {Node->getOperand(I), Node->getOperand(I + Factor / 2)});
- LOps.push_back(Interleave.getValue(0));
- ROps.push_back(Interleave.getValue(1));
- }
- // Interleave at Factor/2:
- // [a0c0 b0d0] [a1c1 b1d1] -> a0b0 c0d0 a1b1 c1d1
- SDValue L = DAG.getNode(ISD::VECTOR_INTERLEAVE, dl, HalfVTs, LOps);
- SDValue R = DAG.getNode(ISD::VECTOR_INTERLEAVE, dl, HalfVTs, ROps);
- for (unsigned I = 0; I < Factor / 2; I++)
- Results.push_back(L.getValue(I));
- for (unsigned I = 0; I < Factor / 2; I++)
- Results.push_back(R.getValue(I));
+ case ISD::VECTOR_DEINTERLEAVE:
+ TLI.expandVectorDeinterleave(Node, Results, DAG);
break;
- }
case ISD::EXTRACT_ELEMENT: {
EVT OpTy = Node->getOperand(0).getValueType();
if (Node->getConstantOperandVal(1)) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 03fae7d7af4be..6044972f37729 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -488,6 +488,13 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::VECTOR_MATCH:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
break;
+ case ISD::VECTOR_INTERLEAVE:
+ case ISD::VECTOR_DEINTERLEAVE: {
+ EVT VT = Node->getValueType(0);
+ unsigned Factor = Node->getNumOperands();
+ Action = TLI.getVectorInterleaveAction(Node->getOpcode(), Factor, VT);
+ break;
+ }
case ISD::SMULFIX:
case ISD::SMULFIXSAT:
case ISD::UMULFIX:
@@ -949,6 +956,12 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
Results.push_back(Node->getOperand(i));
return;
+ case ISD::VECTOR_INTERLEAVE:
+ TLI.expandVectorInterleave(Node, Results, DAG);
+ return;
+ case ISD::VECTOR_DEINTERLEAVE:
+ TLI.expandVectorDeinterleave(Node, Results, DAG);
+ return;
case ISD::SIGN_EXTEND_INREG:
if (SDValue Expanded = ExpandSEXTINREG(Node)) {
Results.push_back(Expanded);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 710a1eda00cc1..287cebdc68fe4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -12958,18 +12958,6 @@ void SelectionDAGBuilder::visitVectorDeinterleave(const CallInst &I,
DAG.getVectorIdxConstant(OutNumElts * i, DL));
}
- // Use VECTOR_SHUFFLE for fixed-length vectors with factor of 2 to benefit
- // from existing legalisation and combines.
- if (OutVT.isFixedLengthVector() && Factor == 2) {
- SDValue Even = DAG.getVectorShuffle(OutVT, DL, SubVecs[0], SubVecs[1],
- createStrideMask(0, 2, OutNumElts));
- SDValue Odd = DAG.getVectorShuffle(OutVT, DL, SubVecs[0], SubVecs[1],
- createStrideMask(1, 2, OutNumElts));
- SDValue Res = DAG.getMergeValues({Even, Odd}, getCurSDLoc());
- setValue(&I, Res);
- return;
- }
-
SDValue Res = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL,
DAG.getVTList(ValueVTs), SubVecs);
setValue(&I, Res);
@@ -12989,16 +12977,6 @@ void SelectionDAGBuilder::visitVectorInterleave(const CallInst &I,
"Expected VTs to be the same");
}
- // Use VECTOR_SHUFFLE for fixed-length vectors with factor of 2 to benefit
- // from existing legalisation and combines.
- if (OutVT.isFixedLengthVector() && Factor == 2) {
- unsigned NumElts = InVT.getVectorMinNumElements();
- SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, InVecs);
- setValue(&I, DAG.getVectorShuffle(OutVT, DL, V, DAG.getUNDEF(OutVT),
- createInterleaveMask(NumElts, 2)));
- return;
- }
-
SmallVector<EVT, 8> ValueVTs(Factor, InVT);
SDValue Res =
DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, DAG.getVTList(ValueVTs), InVecs);
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 16f91bb50e717..c0398bee9ac07 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -13425,6 +13425,128 @@ SDValue TargetLowering::expandFP_ROUND(SDNode *Node, SelectionDAG &DAG) const {
return SDValue();
}
+void TargetLowering::expandVectorInterleave(SDNode *Node,
+ SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const {
+ assert(Node->getOpcode() == ISD::VECTOR_INTERLEAVE && "Unexpected opcode");
+ EVT VT = Node->getValueType(0);
+ unsigned Factor = Node->getNumOperands();
+ SDLoc DL(Node);
+
+ if (Factor > 2 && Factor % 2 == 0) {
+ SmallVector<EVT> HalfVTs(Factor / 2, VT);
+ SmallVector<SDValue, 8> LOps, ROps;
+ // Interleave so we have 2 factors per result:
+ // a0a1 b0b1 c0c1 d0d1 -> [a0c0 b0d0] [a1c1 b1d1]
+ for (unsigned I = 0; I < Factor / 2; I++) {
+ SDValue Interleave =
+ DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, {VT, VT},
+ {Node->getOperand(I), Node->getOperand(I + Factor / 2)});
+ LOps.push_back(Interleave.getValue(0));
+ ROps.push_back(Interleave.getValue(1));
+ }
+ // Interleave at Factor/2:
+ // [a0c0 b0d0] [a1c1 b1d1] -> a0b0 c0d0 a1b1 c1d1
+ SDValue L = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, HalfVTs, LOps);
+ SDValue R = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, HalfVTs, ROps);
+ for (unsigned I = 0; I < Factor / 2; I++)
+ Results.push_back(L.getValue(I));
+ for (unsigned I = 0; I < Factor / 2; I++)
+ Results.push_back(R.getValue(I));
+ return;
+ }
+
+ if (!VT.isFixedLengthVector())
+ return;
+
+ unsigned NumElts = VT.getVectorNumElements();
+ EVT EltVT = VT.getVectorElementType();
+
+ // A factor of two needs only same-width, two-input shuffles.
+ if (Factor == 2) {
+ SmallVector<int, 8> Mask = createInterleaveMask(NumElts, Factor);
+ for (unsigned I = 0; I != Factor; ++I)
+ Results.push_back(DAG.getVectorShuffle(
+ VT, DL, Node->getOperand(0), Node->getOperand(1),
+ ArrayRef<int>(Mask).slice(I * NumElts, NumElts)));
+ return;
+ }
+
+ SmallVector<SDValue> InterleavedElts;
+ InterleavedElts.reserve(Factor * NumElts);
+ for (unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx)
+ for (unsigned OperandIdx = 0; OperandIdx != Factor; ++OperandIdx)
+ InterleavedElts.push_back(DAG.getExtractVectorElt(
+ DL, EltVT, Node->getOperand(OperandIdx), EltIdx));
+
+ for (unsigned ResultIdx = 0; ResultIdx != Factor; ++ResultIdx)
+ Results.push_back(DAG.getBuildVector(
+ VT, DL, ArrayRef(InterleavedElts).slice(ResultIdx * NumElts, NumElts)));
+}
+
+void TargetLowering::expandVectorDeinterleave(SDNode *Node,
+ SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const {
+ assert(Node->getOpcode() == ISD::VECTOR_DEINTERLEAVE && "Unexpected opcode");
+ EVT VT = Node->getValueType(0);
+ unsigned Factor = Node->getNumOperands();
+ SDLoc DL(Node);
+
+ if (Factor > 2 && Factor % 2 == 0) {
+ SmallVector<SDValue, 8> Ops(Node->ops());
+ SmallVector<EVT> HalfVTs(Factor / 2, VT);
+ // Deinterleave at Factor/2 so each result contains two factors interleaved:
+ // a0b0 c0d0 a1b1 c1d1 -> [a0c0 b0d0] [a1c1 b1d1]
+ SDValue L = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, HalfVTs,
+ ArrayRef(Ops).take_front(Factor / 2));
+ SDValue R = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, HalfVTs,
+ ArrayRef(Ops).take_back(Factor / 2));
+ Results.resize(Factor);
+ // Deinterleave the 2 factors out:
+ // [a0c0 a1c1] [b0d0 b1d1] -> a0a1 b0b1 c0c1 d0d1
+ for (unsigned I = 0; I < Factor / 2; I++) {
+ SDValue Deinterleave = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, {VT, VT},
+ {L.getValue(I), R.getValue(I)});
+ Results[I] = Deinterleave.getValue(0);
+ Results[I + Factor / 2] = Deinterleave.getValue(1);
+ }
+ return;
+ }
+
+ if (!VT.isFixedLengthVector())
+ return;
+
+ unsigned NumElts = VT.getVectorNumElements();
+ EVT EltVT = VT.getVectorElementType();
+
+ // A factor of two needs only same-width, two-input shuffles.
+ if (Factor == 2) {
+ for (unsigned I = 0; I != Factor; ++I)
+ Results.push_back(
+ DAG.getVectorShuffle(VT, DL, Node->getOperand(0), Node->getOperand(1),
+ createStrideMask(I, Factor, NumElts)));
+ return;
+ }
+
+ SmallVector<SDValue> ConcatElts;
+ ConcatElts.reserve(Factor * NumElts);
+ for (unsigned OperandIdx = 0; OperandIdx != Factor; ++OperandIdx)
+ for (unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx)
+ ConcatElts.push_back(DAG.getExtractVectorElt(
+ DL, EltVT, Node->getOperand(OperandIdx), EltIdx));
+
+ SmallVector<SDValue> DeinterleavedElts;
+ DeinterleavedElts.reserve(Factor * NumElts);
+ for (unsigned ResultIdx = 0; ResultIdx != Factor; ++ResultIdx)
+ for (unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx)
+ DeinterleavedElts.push_back(ConcatElts[ResultIdx + EltIdx * Factor]);
+
+ for (unsigned ResultIdx = 0; ResultIdx != Factor; ++ResultIdx)
+ Results.push_back(DAG.getBuildVector(
+ VT, DL,
+ ArrayRef(DeinterleavedElts).slice(ResultIdx * NumElts, NumElts)));
+}
+
SDValue TargetLowering::expandVectorSplice(SDNode *Node,
SelectionDAG &DAG) const {
assert((Node->getOpcode() == ISD::VECTOR_SPLICE_LEFT ||
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b2f684952dd90..d49991e65b162 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1616,7 +1616,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setVectorInterleaveAction(
{ISD::VECTOR_INTERLEAVE, ISD::VECTOR_DEINTERLEAVE},
- {2, 3, 4, 5, 6, 7, 8}, VT, Custom);
+ {3, 4, 5, 6, 7, 8}, VT, Custom);
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT},
VT, Custom);
@@ -1796,7 +1796,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setVectorInterleaveAction(
{ISD::VECTOR_INTERLEAVE, ISD::VECTOR_DEINTERLEAVE},
- {2, 3, 4, 5, 6, 7, 8}, VT, Custom);
+ {3, 4, 5, 6, 7, 8}, VT, Custom);
setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE,
ISD::MGATHER, ISD::MSCATTER},
diff --git a/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll b/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
index 6b49ba0a65340..3f5fe57106310 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
@@ -157,6 +157,12 @@ define void @f_undef_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_undef_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
+; CHECK-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: zip1 v1.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #32]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #64]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #96]
; CHECK-IADISABLED-NEXT: ret
BB:
%S = call <16 x i64> @llvm.vector.interleave2.v16i64(<8 x i64> poison, <8 x i64> poison)
@@ -179,6 +185,12 @@ define void @f_poison_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_poison_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
+; CHECK-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: zip1 v1.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #32]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #64]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #96]
; CHECK-IADISABLED-NEXT: ret
BB:
%S = call <16 x i64> @llvm.vector.interleave2.v16i64(<8 x i64> poison, <8 x i64> poison)
@@ -202,8 +214,14 @@ define void @f_undef_15_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_undef_15_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
-; CHECK-IADISABLED-NEXT: dup v1.2d, v0.d[1]
-; CHECK-IADISABLED-NEXT: stp q0, q1, [x0]
+; CHECK-IADISABLED-NEXT: // kill: def $q0 killed $q0 def $q0_q1
+; CHECK-IADISABLED-NEXT: mov x8, x0
+; CHECK-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: st2 { v0.2d, v1.2d }, [x8], #32
+; CHECK-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: stp q0, q2, [x0, #64]
+; CHECK-IADISABLED-NEXT: stp q0, q2, [x0, #96]
+; CHECK-IADISABLED-NEXT: st2 { v0.2d, v1.2d }, [x8]
; CHECK-IADISABLED-NEXT: ret
BB:
%a.0 = extractelement <8 x i64> %a, i64 0
@@ -236,18 +254,19 @@ define void @f_undef_1_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_undef_1_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
-; CHECK-IADISABLED-NEXT: dup v4.2d, v3.d[1]
-; CHECK-IADISABLED-NEXT: dup v3.2d, v3.d[0]
-; CHECK-IADISABLED-NEXT: dup v5.2d, v2.d[1]
-; CHECK-IADISABLED-NEXT: dup v2.2d, v2.d[0]
-; CHECK-IADISABLED-NEXT: stp q3, q4, [x0, #96]
-; CHECK-IADISABLED-NEXT: dup v4.2d, v1.d[1]
-; CHECK-IADISABLED-NEXT: dup v1.2d, v1.d[0]
-; CHECK-IADISABLED-NEXT: dup v3.2d, v0.d[1]
-; CHECK-IADISABLED-NEXT: dup v0.2d, v0.d[0]
-; CHECK-IADISABLED-NEXT: stp q2, q5, [x0, #64]
-; CHECK-IADISABLED-NEXT: stp q1, q4, [x0, #32]
-; CHECK-IADISABLED-NEXT: stp q0, q3, [x0]
+; CHECK-IADISABLED-NEXT: mov v5.16b, v2.16b
+; CHECK-IADISABLED-NEXT: mov v16.16b, v0.16b
+; CHECK-IADISABLED-NEXT: // kill: def $q3 killed $q3 def $q3_q4
+; CHECK-IADISABLED-NEXT: // kill: def $q1 killed $q1 def $q1_q2
+; CHECK-IADISABLED-NEXT: add x8, x0, #64
+; CHECK-IADISABLED-NEXT: mov v4.16b, v3.16b
+; CHECK-IADISABLED-NEXT: mov v2.16b, v1.16b
+; CHECK-IADISABLED-NEXT: mov v6.16b, v5.16b
+; CHECK-IADISABLED-NEXT: mov v17.16b, v16.16b
+; CHECK-IADISABLED-NEXT: st2 { v5.2d, v6.2d }, [x8], #32
+; CHECK-IADISABLED-NEXT: st2 { v3.2d, v4.2d }, [x8]
+; CHECK-IADISABLED-NEXT: st2 { v16.2d, v17.2d }, [x0], #32
+; CHECK-IADISABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
; CHECK-IADISABLED-NEXT: ret
BB:
%even = insertelement <8 x i64> %a, i64 poison, i64 6
@@ -258,25 +277,15 @@ BB:
define void @noundefs_intrinsic(<8 x i32> %a, <8 x i32> %b, ptr %dst) {
-; CHECK-IAENABLED-LABEL: noundefs_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %BB
-; CHECK-IAENABLED-NEXT: mov v5.16b, v2.16b
-; CHECK-IAENABLED-NEXT: // kill: def $q3 killed $q3 def $q2_q3
-; CHECK-IAENABLED-NEXT: mov v4.16b, v0.16b
-; CHECK-IAENABLED-NEXT: mov v2.16b, v1.16b
-; CHECK-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
-; CHECK-IAENABLED-NEXT: st2 { v2.4s, v3.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: noundefs_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %BB
-; CHECK-IADISABLED-NEXT: zip2 v4.4s, v1.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v1.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v3.4s, v0.4s, v2.4s
-; CHECK-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v2.4s
-; CHECK-IADISABLED-NEXT: stp q1, q4, [x0, #32]
-; CHECK-IADISABLED-NEXT: stp q0, q3, [x0]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: noundefs_intrinsic:
+; CHECK: // %bb.0: // %BB
+; CHECK-NEXT: mov v5.16b, v2.16b
+; CHECK-NEXT: // kill: def $q3 killed $q3 def $q2_q3
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: mov v2.16b, v1.16b
+; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
+; CHECK-NEXT: st2 { v2.4s, v3.4s }, [x0]
+; CHECK-NEXT: ret
BB:
%even = insertelement <8 x i32> %a, i32 poison, i64 6
%S = call <16 x i32> @llvm.vector.interleave2.v16i32(<8 x i32> %even, <8 x i32> %b)
@@ -286,25 +295,15 @@ BB:
define void @undefs_intrinsic(<8 x i32> %a, <8 x i32> %b, ptr %dst) {
-; CHECK-IAENABLED-LABEL: undefs_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %BB
-; CHECK-IAENABLED-NEXT: mov v5.16b, v2.16b
-; CHECK-IAENABLED-NEXT: // kill: def $q3 killed $q3 def $q2_q3
-; CHECK-IAENABLED-NEXT: mov v4.16b, v0.16b
-; CHECK-IAENABLED-NEXT: mov v2.16b, v1.16b
-; CHECK-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
-; CHECK-IAENABLED-NEXT: st2 { v2.4s, v3.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: undefs_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %BB
-; CHECK-IADISABLED-NEXT: zip2 v4.4s, v1.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v1.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v3.4s, v0.4s, v2.4s
-; CHECK-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v2.4s
-; CHECK-IADISABLED-NEXT: stp q1, q4, [x0, #32]
-; CHECK-IADISABLED-NEXT: stp q0, q3, [x0]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: undefs_intrinsic:
+; CHECK: // %bb.0: // %BB
+; CHECK-NEXT: mov v5.16b, v2.16b
+; CHECK-NEXT: // kill: def $q3 killed $q3 def $q2_q3
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: mov v2.16b, v1.16b
+; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
+; CHECK-NEXT: st2 { v2.4s, v3.4s }, [x0]
+; CHECK-NEXT: ret
BB:
%a.3 = extractelement <8 x i32> %a, i64 3
%a.7 = extractelement <8 x i32> %a, i64 7
diff --git a/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll b/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll
index f83739ef6f44f..c56b492bb33cd 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll
@@ -896,31 +896,17 @@ define void @aarch64_ilc_idx_ld2_intrinsic(ptr %ptr, i64 %idx) {
; CHECK-NEXT: store <4 x float> [[M4_7]], ptr [[GEP2]], align 16
; CHECK-NEXT: ret void
;
-; AS-IAENABLED-LABEL: aarch64_ilc_idx_ld2_intrinsic:
-; AS-IAENABLED: // %bb.0: // %entry
-; AS-IAENABLED-NEXT: lsl x8, x1, #2
-; AS-IAENABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; AS-IAENABLED-NEXT: add x8, x8, #16
-; AS-IAENABLED-NEXT: add x10, x0, x9
-; AS-IAENABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; AS-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x10]
-; AS-IAENABLED-NEXT: str q0, [x0, x9]
-; AS-IAENABLED-NEXT: str q1, [x0, x8]
-; AS-IAENABLED-NEXT: ret
-;
-; AS-IADISABLED-LABEL: aarch64_ilc_idx_ld2_intrinsic:
-; AS-IADISABLED: // %bb.0: // %entry
-; AS-IADISABLED-NEXT: lsl x8, x1, #2
-; AS-IADISABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; AS-IADISABLED-NEXT: add x8, x8, #16
-; AS-IADISABLED-NEXT: add x9, x0, x9
-; AS-IADISABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; AS-IADISABLED-NEXT: ldp q1, q0, [x9]
-; AS-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: str q2, [x9]
-; AS-IADISABLED-NEXT: str q0, [x0, x8]
-; AS-IADISABLED-NEXT: ret
+; AS-LABEL: aarch64_ilc_idx_ld2_intrinsic:
+; AS: // %bb.0: // %entry
+; AS-NEXT: lsl x8, x1, #2
+; AS-NEXT: and x9, x8, #0xfffffffffffffff0
+; AS-NEXT: add x8, x8, #16
+; AS-NEXT: add x10, x0, x9
+; AS-NEXT: and x8, x8, #0xfffffffffffffff0
+; AS-NEXT: ld2 { v0.4s, v1.4s }, [x10]
+; AS-NEXT: str q0, [x0, x9]
+; AS-NEXT: str q1, [x0, x8]
+; AS-NEXT: ret
entry:
%idx1 = lshr i64 %idx, 2
%a1 = add i64 %idx, 4
@@ -1009,30 +995,17 @@ define void @aarch64_ilc_i32_idx_intrinsic(ptr %ptr, i32 %idx) {
; CHECK-NEXT: store <4 x float> [[M4_7]], ptr [[GEP2]], align 16
; CHECK-NEXT: ret void
;
-; AS-IAENABLED-LABEL: aarch64_ilc_i32_idx_intrinsic:
-; AS-IAENABLED: // %bb.0: // %entry
-; AS-IAENABLED-NEXT: lsr w8, w1, #2
-; AS-IAENABLED-NEXT: ubfiz x8, x8, #4, #32
-; AS-IAENABLED-NEXT: add x9, x0, x8
-; AS-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x9]
-; AS-IAENABLED-NEXT: add w9, w1, #4
-; AS-IAENABLED-NEXT: lsr w9, w9, #2
-; AS-IAENABLED-NEXT: str q0, [x0, x8]
-; AS-IAENABLED-NEXT: str q1, [x0, w9, uxtw #4]
-; AS-IAENABLED-NEXT: ret
-;
-; AS-IADISABLED-LABEL: aarch64_ilc_i32_idx_intrinsic:
-; AS-IADISABLED: // %bb.0: // %entry
-; AS-IADISABLED-NEXT: lsr w8, w1, #2
-; AS-IADISABLED-NEXT: add w9, w1, #4
-; AS-IADISABLED-NEXT: lsr w9, w9, #2
-; AS-IADISABLED-NEXT: add x8, x0, w8, uxtw #4
-; AS-IADISABLED-NEXT: ldp q1, q0, [x8]
-; AS-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: str q2, [x8]
-; AS-IADISABLED-NEXT: str q0, [x0, w9, uxtw #4]
-; AS-IADISABLED-NEXT: ret
+; AS-LABEL: aarch64_ilc_i32_idx_intrinsic:
+; AS: // %bb.0: // %entry
+; AS-NEXT: lsr w8, w1, #2
+; AS-NEXT: ubfiz x8, x8, #4, #32
+; AS-NEXT: add x9, x0, x8
+; AS-NEXT: ld2 { v0.4s, v1.4s }, [x9]
+; AS-NEXT: add w9, w1, #4
+; AS-NEXT: lsr w9, w9, #2
+; AS-NEXT: str q0, [x0, x8]
+; AS-NEXT: str q1, [x0, w9, uxtw #4]
+; AS-NEXT: ret
entry:
%idx1 = lshr i32 %idx, 2
%a1 = add i32 %idx, 4
diff --git a/llvm/test/CodeGen/AArch64/binopshuffles.ll b/llvm/test/CodeGen/AArch64/binopshuffles.ll
index 3ee9df3165c98..ab4e106c6362e 100644
--- a/llvm/test/CodeGen/AArch64/binopshuffles.ll
+++ b/llvm/test/CodeGen/AArch64/binopshuffles.ll
@@ -251,25 +251,13 @@ entry:
}
define <4 x float> @twosrc_intrinsic(ptr %pSrc1, ptr %pSrc2) {
-; CHECK-IAENABLED-LABEL: twosrc_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ld2 { v3.4s, v4.4s }, [x1]
-; CHECK-IAENABLED-NEXT: fmul v0.4s, v3.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmla v0.4s, v2.4s, v4.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: twosrc_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0]
-; CHECK-IADISABLED-NEXT: ldp q3, q2, [x1]
-; CHECK-IADISABLED-NEXT: uzp1 v4.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp1 v5.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: uzp2 v2.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v5.4s, v4.4s
-; CHECK-IADISABLED-NEXT: fmla v0.4s, v1.4s, v2.4s
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: twosrc_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x0]
+; CHECK-NEXT: ld2 { v3.4s, v4.4s }, [x1]
+; CHECK-NEXT: fmul v0.4s, v3.4s, v1.4s
+; CHECK-NEXT: fmla v0.4s, v2.4s, v4.4s
+; CHECK-NEXT: ret
entry:
%intrinsic.load.0 = load <8 x float>, ptr %pSrc1, align 4
%ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
@@ -286,25 +274,13 @@ entry:
}
define <4 x float> @twosrc2_intrinsic(ptr %pSrc1, ptr %pSrc2) {
-; CHECK-IAENABLED-LABEL: twosrc2_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ld2 { v3.4s, v4.4s }, [x1]
-; CHECK-IAENABLED-NEXT: fmul v0.4s, v3.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmla v0.4s, v2.4s, v4.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: twosrc2_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0]
-; CHECK-IADISABLED-NEXT: ldp q3, q2, [x1]
-; CHECK-IADISABLED-NEXT: uzp1 v4.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp1 v5.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: uzp2 v2.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v5.4s, v4.4s
-; CHECK-IADISABLED-NEXT: fmla v0.4s, v1.4s, v2.4s
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: twosrc2_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x0]
+; CHECK-NEXT: ld2 { v3.4s, v4.4s }, [x1]
+; CHECK-NEXT: fmul v0.4s, v3.4s, v1.4s
+; CHECK-NEXT: fmla v0.4s, v2.4s, v4.4s
+; CHECK-NEXT: ret
entry:
%intrinsic.load.0 = load <8 x float>, ptr %pSrc1, align 4
%ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
@@ -321,21 +297,12 @@ entry:
}
define <4 x float> @vld2_intrinsic(ptr %pSrc) {
-; CHECK-IAENABLED-LABEL: vld2_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x0]
-; CHECK-IAENABLED-NEXT: fmul v0.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmla v0.4s, v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld2_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0]
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v0.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld2_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x0]
+; CHECK-NEXT: fmul v0.4s, v1.4s, v1.4s
+; CHECK-NEXT: fmla v0.4s, v2.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%intrinsic.load.0 = load <8 x float>, ptr %pSrc, align 4
%ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
index 0e4b3eee1f991..8df834af2e2df 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
@@ -525,10 +525,10 @@ define <4 x float> @mul_triangle_external_use_intrinsic(<4 x float> %a, <4 x flo
; CHECK-NEXT: mov d3, v0.d[1]
; CHECK-NEXT: mov d4, v1.d[1]
; CHECK-NEXT: movi v2.2s, #128, lsl #24
-; CHECK-NEXT: zip2 v5.2s, v0.2s, v3.2s
-; CHECK-NEXT: zip1 v6.2s, v1.2s, v4.2s
-; CHECK-NEXT: zip1 v0.2s, v0.2s, v3.2s
-; CHECK-NEXT: zip2 v1.2s, v1.2s, v4.2s
+; CHECK-NEXT: uzp2 v5.2s, v0.2s, v3.2s
+; CHECK-NEXT: uzp1 v6.2s, v1.2s, v4.2s
+; CHECK-NEXT: uzp1 v0.2s, v0.2s, v3.2s
+; CHECK-NEXT: uzp2 v1.2s, v1.2s, v4.2s
; CHECK-NEXT: fmul v3.2s, v5.2s, v6.2s
; CHECK-NEXT: fmls v2.2s, v1.2s, v5.2s
; CHECK-NEXT: fmla v3.2s, v0.2s, v1.2s
@@ -539,9 +539,7 @@ define <4 x float> @mul_triangle_external_use_intrinsic(<4 x float> %a, <4 x flo
; CHECK-NEXT: str d3, [x0]
; CHECK-NEXT: fmla v4.2s, v5.2s, v2.2s
; CHECK-NEXT: fmla v1.2s, v0.2s, v2.2s
-; CHECK-NEXT: mov v1.d[1], v4.d[0]
-; CHECK-NEXT: rev64 v0.4s, v1.4s
-; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: zip1 v0.4s, v1.4s, v4.4s
; CHECK-NEXT: ret
entry:
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
@@ -569,64 +567,33 @@ entry:
define <4 x float> @multiple_muls_shuffle_external_intrinsic(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, ptr %p1, ptr %p2) {
-; CHECK-IAENABLED-LABEL: multiple_muls_shuffle_external_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov d4, v1.d[1]
-; CHECK-IAENABLED-NEXT: mov d5, v0.d[1]
-; CHECK-IAENABLED-NEXT: mov d16, v2.d[1]
-; CHECK-IAENABLED-NEXT: movi v17.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: zip1 v6.2s, v1.2s, v4.2s
-; CHECK-IAENABLED-NEXT: zip2 v7.2s, v0.2s, v5.2s
-; CHECK-IAENABLED-NEXT: zip1 v0.2s, v0.2s, v5.2s
-; CHECK-IAENABLED-NEXT: zip2 v1.2s, v1.2s, v4.2s
-; CHECK-IAENABLED-NEXT: movi v5.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: fmul v4.2s, v6.2s, v7.2s
-; CHECK-IAENABLED-NEXT: fmls v5.2s, v1.2s, v7.2s
-; CHECK-IAENABLED-NEXT: fmla v4.2s, v0.2s, v1.2s
-; CHECK-IAENABLED-NEXT: zip1 v1.2s, v2.2s, v16.2s
-; CHECK-IAENABLED-NEXT: fmla v5.2s, v0.2s, v6.2s
-; CHECK-IAENABLED-NEXT: zip2 v6.2s, v2.2s, v16.2s
-; CHECK-IAENABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IAENABLED-NEXT: fmul v18.2s, v1.2s, v4.2s
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #0
-; CHECK-IAENABLED-NEXT: str d5, [x0]
-; CHECK-IAENABLED-NEXT: fmla v18.2s, v5.2s, v6.2s
-; CHECK-IAENABLED-NEXT: fmls v17.2s, v6.2s, v4.2s
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #90
-; CHECK-IAENABLED-NEXT: fmla v17.2s, v5.2s, v1.2s
-; CHECK-IAENABLED-NEXT: st2 { v17.2s, v18.2s }, [x1]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: multiple_muls_shuffle_external_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov d4, v1.d[1]
-; CHECK-IADISABLED-NEXT: mov d5, v0.d[1]
-; CHECK-IADISABLED-NEXT: movi v16.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: zip1 v6.2s, v1.2s, v4.2s
-; CHECK-IADISABLED-NEXT: zip2 v7.2s, v0.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip1 v0.2s, v0.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip2 v1.2s, v1.2s, v4.2s
-; CHECK-IADISABLED-NEXT: mov d5, v2.d[1]
-; CHECK-IADISABLED-NEXT: fmul v4.2s, v6.2s, v7.2s
-; CHECK-IADISABLED-NEXT: fmls v16.2s, v1.2s, v7.2s
-; CHECK-IADISABLED-NEXT: zip2 v7.2s, v2.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip1 v5.2s, v2.2s, v5.2s
-; CHECK-IADISABLED-NEXT: fmla v4.2s, v0.2s, v1.2s
-; CHECK-IADISABLED-NEXT: movi v1.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: fmla v16.2s, v0.2s, v6.2s
-; CHECK-IADISABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IADISABLED-NEXT: fmul v6.2s, v5.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmls v1.2s, v7.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #0
-; CHECK-IADISABLED-NEXT: str d16, [x0]
-; CHECK-IADISABLED-NEXT: fmla v6.2s, v16.2s, v7.2s
-; CHECK-IADISABLED-NEXT: fmla v1.2s, v16.2s, v5.2s
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #90
-; CHECK-IADISABLED-NEXT: mov v1.d[1], v6.d[0]
-; CHECK-IADISABLED-NEXT: rev64 v4.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp1 v1.4s, v1.4s, v4.4s
-; CHECK-IADISABLED-NEXT: str q1, [x1]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: multiple_muls_shuffle_external_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d4, v1.d[1]
+; CHECK-NEXT: mov d5, v0.d[1]
+; CHECK-NEXT: mov d16, v2.d[1]
+; CHECK-NEXT: movi v17.2s, #128, lsl #24
+; CHECK-NEXT: uzp1 v6.2s, v1.2s, v4.2s
+; CHECK-NEXT: uzp2 v7.2s, v0.2s, v5.2s
+; CHECK-NEXT: uzp1 v0.2s, v0.2s, v5.2s
+; CHECK-NEXT: uzp2 v1.2s, v1.2s, v4.2s
+; CHECK-NEXT: movi v5.2s, #128, lsl #24
+; CHECK-NEXT: fmul v4.2s, v6.2s, v7.2s
+; CHECK-NEXT: fmls v5.2s, v1.2s, v7.2s
+; CHECK-NEXT: fmla v4.2s, v0.2s, v1.2s
+; CHECK-NEXT: uzp1 v1.2s, v2.2s, v16.2s
+; CHECK-NEXT: fmla v5.2s, v0.2s, v6.2s
+; CHECK-NEXT: uzp2 v6.2s, v2.2s, v16.2s
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: fmul v18.2s, v1.2s, v4.2s
+; CHECK-NEXT: fcmla v0.4s, v2.4s, v3.4s, #0
+; CHECK-NEXT: str d5, [x0]
+; CHECK-NEXT: fmla v18.2s, v5.2s, v6.2s
+; CHECK-NEXT: fmls v17.2s, v6.2s, v4.2s
+; CHECK-NEXT: fcmla v0.4s, v2.4s, v3.4s, #90
+; CHECK-NEXT: fmla v17.2s, v5.2s, v1.2s
+; CHECK-NEXT: st2 { v17.2s, v18.2s }, [x1]
+; CHECK-NEXT: ret
entry:
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
%strided.vec = extractvalue { <2 x float>, <2 x float> } %a.deinterleaved, 0
@@ -667,66 +634,30 @@ entry:
define <4 x float> @multiple_muls_shuffle_external_with_loads_intrinsic(ptr %ptr_a, ptr %ptr_b, ptr %ptr_c, ptr %ptr_d, ptr %p1, ptr %p2) {
-; CHECK-IAENABLED-LABEL: multiple_muls_shuffle_external_with_loads_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-IAENABLED-NEXT: movi v4.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: ld2 { v2.2s, v3.2s }, [x1]
-; CHECK-IAENABLED-NEXT: fmls v4.2s, v3.2s, v1.2s
-; CHECK-IAENABLED-NEXT: fmul v6.2s, v2.2s, v1.2s
-; CHECK-IAENABLED-NEXT: fmla v4.2s, v0.2s, v2.2s
-; CHECK-IAENABLED-NEXT: fmla v6.2s, v0.2s, v3.2s
-; CHECK-IAENABLED-NEXT: movi v1.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: str d4, [x4]
-; CHECK-IAENABLED-NEXT: ldr q5, [x2]
-; CHECK-IAENABLED-NEXT: mov d7, v5.d[1]
-; CHECK-IAENABLED-NEXT: zip1 v0.2s, v5.2s, v7.2s
-; CHECK-IAENABLED-NEXT: zip2 v3.2s, v5.2s, v7.2s
-; CHECK-IAENABLED-NEXT: fmul v2.2s, v0.2s, v6.2s
-; CHECK-IAENABLED-NEXT: fmla v2.2s, v4.2s, v3.2s
-; CHECK-IAENABLED-NEXT: fmls v1.2s, v3.2s, v6.2s
-; CHECK-IAENABLED-NEXT: fmla v1.2s, v4.2s, v0.2s
-; CHECK-IAENABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x5]
-; CHECK-IAENABLED-NEXT: ldr q1, [x3]
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v5.4s, v1.4s, #0
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v5.4s, v1.4s, #90
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: multiple_muls_shuffle_external_with_loads_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-IADISABLED-NEXT: ldr q1, [x1]
-; CHECK-IADISABLED-NEXT: movi v6.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: mov d2, v0.d[1]
-; CHECK-IADISABLED-NEXT: mov d3, v1.d[1]
-; CHECK-IADISABLED-NEXT: zip2 v4.2s, v0.2s, v2.2s
-; CHECK-IADISABLED-NEXT: zip2 v5.2s, v1.2s, v3.2s
-; CHECK-IADISABLED-NEXT: zip1 v0.2s, v0.2s, v2.2s
-; CHECK-IADISABLED-NEXT: zip1 v1.2s, v1.2s, v3.2s
-; CHECK-IADISABLED-NEXT: fmls v6.2s, v5.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmla v6.2s, v0.2s, v1.2s
-; CHECK-IADISABLED-NEXT: fmul v1.2s, v1.2s, v4.2s
-; CHECK-IADISABLED-NEXT: str d6, [x4]
-; CHECK-IADISABLED-NEXT: fmla v1.2s, v0.2s, v5.2s
-; CHECK-IADISABLED-NEXT: movi v0.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: ldr q2, [x2]
-; CHECK-IADISABLED-NEXT: mov d3, v2.d[1]
-; CHECK-IADISABLED-NEXT: zip2 v4.2s, v2.2s, v3.2s
-; CHECK-IADISABLED-NEXT: zip1 v3.2s, v2.2s, v3.2s
-; CHECK-IADISABLED-NEXT: fmul v5.2s, v3.2s, v1.2s
-; CHECK-IADISABLED-NEXT: fmls v0.2s, v4.2s, v1.2s
-; CHECK-IADISABLED-NEXT: fmla v5.2s, v6.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmla v0.2s, v6.2s, v3.2s
-; CHECK-IADISABLED-NEXT: mov v0.d[1], v5.d[0]
-; CHECK-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp1 v1.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IADISABLED-NEXT: str q1, [x5]
-; CHECK-IADISABLED-NEXT: ldr q1, [x3]
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v2.4s, v1.4s, #0
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v2.4s, v1.4s, #90
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: multiple_muls_shuffle_external_with_loads_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-NEXT: movi v4.2s, #128, lsl #24
+; CHECK-NEXT: ld2 { v2.2s, v3.2s }, [x1]
+; CHECK-NEXT: fmls v4.2s, v3.2s, v1.2s
+; CHECK-NEXT: fmul v5.2s, v2.2s, v1.2s
+; CHECK-NEXT: fmla v4.2s, v0.2s, v2.2s
+; CHECK-NEXT: fmla v5.2s, v0.2s, v3.2s
+; CHECK-NEXT: movi v1.2s, #128, lsl #24
+; CHECK-NEXT: str d4, [x4]
+; CHECK-NEXT: ldr q6, [x2]
+; CHECK-NEXT: uzp1 v0.4s, v6.4s, v0.4s
+; CHECK-NEXT: uzp2 v3.4s, v6.4s, v0.4s
+; CHECK-NEXT: fmul v2.2s, v0.2s, v5.2s
+; CHECK-NEXT: fmla v2.2s, v4.2s, v3.2s
+; CHECK-NEXT: fmls v1.2s, v3.2s, v5.2s
+; CHECK-NEXT: fmla v1.2s, v4.2s, v0.2s
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: st2 { v1.2s, v2.2s }, [x5]
+; CHECK-NEXT: ldr q1, [x3]
+; CHECK-NEXT: fcmla v0.4s, v6.4s, v1.4s, #0
+; CHECK-NEXT: fcmla v0.4s, v6.4s, v1.4s, #90
+; CHECK-NEXT: ret
entry:
%a = load <4 x float>, ptr %ptr_a
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
@@ -771,80 +702,39 @@ entry:
define <4 x float> @multiple_muls_mul_external_intrinsic(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, ptr %p1, ptr %p2) {
-; CHECK-IAENABLED-LABEL: multiple_muls_mul_external_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov d4, v0.d[1]
-; CHECK-IAENABLED-NEXT: mov d5, v1.d[1]
-; CHECK-IAENABLED-NEXT: mov d6, v2.d[1]
-; CHECK-IAENABLED-NEXT: mov d7, v3.d[1]
-; CHECK-IAENABLED-NEXT: movi v16.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: zip2 v17.2s, v0.2s, v4.2s
-; CHECK-IAENABLED-NEXT: zip2 v18.2s, v1.2s, v5.2s
-; CHECK-IAENABLED-NEXT: zip1 v19.2s, v2.2s, v6.2s
-; CHECK-IAENABLED-NEXT: zip2 v20.2s, v3.2s, v7.2s
-; CHECK-IAENABLED-NEXT: zip1 v0.2s, v0.2s, v4.2s
-; CHECK-IAENABLED-NEXT: zip1 v1.2s, v1.2s, v5.2s
-; CHECK-IAENABLED-NEXT: zip2 v2.2s, v2.2s, v6.2s
-; CHECK-IAENABLED-NEXT: movi v4.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: zip1 v3.2s, v3.2s, v7.2s
-; CHECK-IAENABLED-NEXT: movi v6.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: fmls v16.2s, v17.2s, v18.2s
-; CHECK-IAENABLED-NEXT: fmul v5.2s, v19.2s, v20.2s
-; CHECK-IAENABLED-NEXT: fmls v4.2s, v2.2s, v20.2s
-; CHECK-IAENABLED-NEXT: fmla v16.2s, v1.2s, v0.2s
-; CHECK-IAENABLED-NEXT: fmul v0.2s, v0.2s, v18.2s
-; CHECK-IAENABLED-NEXT: fmla v5.2s, v3.2s, v2.2s
-; CHECK-IAENABLED-NEXT: fmla v4.2s, v3.2s, v19.2s
-; CHECK-IAENABLED-NEXT: fmla v0.2s, v1.2s, v17.2s
-; CHECK-IAENABLED-NEXT: str d16, [x0]
-; CHECK-IAENABLED-NEXT: fmul v7.2s, v16.2s, v5.2s
-; CHECK-IAENABLED-NEXT: fmla v7.2s, v4.2s, v0.2s
-; CHECK-IAENABLED-NEXT: fmls v6.2s, v0.2s, v5.2s
-; CHECK-IAENABLED-NEXT: fmla v6.2s, v4.2s, v16.2s
-; CHECK-IAENABLED-NEXT: mov v4.d[1], v5.d[0]
-; CHECK-IAENABLED-NEXT: rev64 v0.4s, v4.4s
-; CHECK-IAENABLED-NEXT: st2 { v6.2s, v7.2s }, [x1]
-; CHECK-IAENABLED-NEXT: uzp1 v0.4s, v4.4s, v0.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: multiple_muls_mul_external_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov d4, v0.d[1]
-; CHECK-IADISABLED-NEXT: mov d5, v1.d[1]
-; CHECK-IADISABLED-NEXT: mov d6, v2.d[1]
-; CHECK-IADISABLED-NEXT: mov d7, v3.d[1]
-; CHECK-IADISABLED-NEXT: movi v16.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: zip2 v17.2s, v0.2s, v4.2s
-; CHECK-IADISABLED-NEXT: zip1 v0.2s, v0.2s, v4.2s
-; CHECK-IADISABLED-NEXT: zip2 v4.2s, v1.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip1 v18.2s, v2.2s, v6.2s
-; CHECK-IADISABLED-NEXT: zip2 v19.2s, v3.2s, v7.2s
-; CHECK-IADISABLED-NEXT: zip1 v1.2s, v1.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip2 v2.2s, v2.2s, v6.2s
-; CHECK-IADISABLED-NEXT: zip1 v3.2s, v3.2s, v7.2s
-; CHECK-IADISABLED-NEXT: fmul v5.2s, v0.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmls v16.2s, v17.2s, v4.2s
-; CHECK-IADISABLED-NEXT: movi v4.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: fmul v6.2s, v18.2s, v19.2s
-; CHECK-IADISABLED-NEXT: fmla v5.2s, v1.2s, v17.2s
-; CHECK-IADISABLED-NEXT: fmla v16.2s, v1.2s, v0.2s
-; CHECK-IADISABLED-NEXT: movi v1.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: fmla v6.2s, v3.2s, v2.2s
-; CHECK-IADISABLED-NEXT: fmls v4.2s, v2.2s, v19.2s
-; CHECK-IADISABLED-NEXT: str d16, [x0]
-; CHECK-IADISABLED-NEXT: fmla v4.2s, v3.2s, v18.2s
-; CHECK-IADISABLED-NEXT: fmul v0.2s, v16.2s, v6.2s
-; CHECK-IADISABLED-NEXT: fmls v1.2s, v5.2s, v6.2s
-; CHECK-IADISABLED-NEXT: fmla v0.2s, v4.2s, v5.2s
-; CHECK-IADISABLED-NEXT: fmla v1.2s, v4.2s, v16.2s
-; CHECK-IADISABLED-NEXT: mov v4.d[1], v6.d[0]
-; CHECK-IADISABLED-NEXT: mov v1.d[1], v0.d[0]
-; CHECK-IADISABLED-NEXT: rev64 v0.4s, v4.4s
-; CHECK-IADISABLED-NEXT: rev64 v2.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp1 v0.4s, v4.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp1 v1.4s, v1.4s, v2.4s
-; CHECK-IADISABLED-NEXT: str q1, [x1]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: multiple_muls_mul_external_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d4, v0.d[1]
+; CHECK-NEXT: mov d5, v1.d[1]
+; CHECK-NEXT: mov d6, v2.d[1]
+; CHECK-NEXT: mov d7, v3.d[1]
+; CHECK-NEXT: movi v16.2s, #128, lsl #24
+; CHECK-NEXT: uzp2 v17.2s, v0.2s, v4.2s
+; CHECK-NEXT: uzp2 v18.2s, v1.2s, v5.2s
+; CHECK-NEXT: uzp1 v19.2s, v2.2s, v6.2s
+; CHECK-NEXT: uzp2 v20.2s, v3.2s, v7.2s
+; CHECK-NEXT: uzp1 v0.2s, v0.2s, v4.2s
+; CHECK-NEXT: uzp1 v1.2s, v1.2s, v5.2s
+; CHECK-NEXT: uzp2 v2.2s, v2.2s, v6.2s
+; CHECK-NEXT: movi v4.2s, #128, lsl #24
+; CHECK-NEXT: uzp1 v3.2s, v3.2s, v7.2s
+; CHECK-NEXT: movi v6.2s, #128, lsl #24
+; CHECK-NEXT: fmls v16.2s, v17.2s, v18.2s
+; CHECK-NEXT: fmul v5.2s, v19.2s, v20.2s
+; CHECK-NEXT: fmls v4.2s, v2.2s, v20.2s
+; CHECK-NEXT: fmla v16.2s, v1.2s, v0.2s
+; CHECK-NEXT: fmul v0.2s, v0.2s, v18.2s
+; CHECK-NEXT: fmla v5.2s, v3.2s, v2.2s
+; CHECK-NEXT: fmla v4.2s, v3.2s, v19.2s
+; CHECK-NEXT: fmla v0.2s, v1.2s, v17.2s
+; CHECK-NEXT: str d16, [x0]
+; CHECK-NEXT: fmul v7.2s, v16.2s, v5.2s
+; CHECK-NEXT: fmla v7.2s, v4.2s, v0.2s
+; CHECK-NEXT: fmls v6.2s, v0.2s, v5.2s
+; CHECK-NEXT: zip1 v0.4s, v4.4s, v5.4s
+; CHECK-NEXT: fmla v6.2s, v4.2s, v16.2s
+; CHECK-NEXT: st2 { v6.2s, v7.2s }, [x1]
+; CHECK-NEXT: ret
entry:
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
%strided.vec = extractvalue { <2 x float>, <2 x float> } %a.deinterleaved, 0
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
index 355adec955e4b..ad6f77773d9fc 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
@@ -31,8 +31,8 @@ define dso_local %"struct.std::complex" @complex_mul_v2f64(ptr %a, ptr %b) {
; CHECK-NEXT: fcmla v0.2d, v4.2d, v2.2d, #90
; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %middle.block
-; CHECK-NEXT: zip2 v2.2d, v1.2d, v0.2d
-; CHECK-NEXT: zip1 v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp2 v2.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp1 v0.2d, v1.2d, v0.2d
; CHECK-NEXT: faddp d0, v0.2d
; CHECK-NEXT: faddp d1, v2.2d
; CHECK-NEXT: ret
@@ -98,8 +98,8 @@ define %"struct.std::complex" @complex_mul_nonzero_init_v2f64(ptr %a, ptr %b) {
; CHECK-NEXT: fcmla v0.2d, v4.2d, v2.2d, #90
; CHECK-NEXT: b.ne .LBB1_1
; CHECK-NEXT: // %bb.2: // %middle.block
-; CHECK-NEXT: zip2 v2.2d, v1.2d, v0.2d
-; CHECK-NEXT: zip1 v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp2 v2.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp1 v0.2d, v1.2d, v0.2d
; CHECK-NEXT: faddp d0, v0.2d
; CHECK-NEXT: faddp d1, v2.2d
; CHECK-NEXT: ret
@@ -168,10 +168,10 @@ define %"struct.std::complex" @complex_mul_v2f64_unrolled(ptr %a, ptr %b) {
; CHECK-NEXT: fcmla v3.2d, v18.2d, v16.2d, #90
; CHECK-NEXT: b.ne .LBB2_1
; CHECK-NEXT: // %bb.2: // %middle.block
-; CHECK-NEXT: zip2 v4.2d, v0.2d, v3.2d
-; CHECK-NEXT: zip1 v0.2d, v0.2d, v3.2d
-; CHECK-NEXT: zip2 v3.2d, v2.2d, v1.2d
-; CHECK-NEXT: zip1 v1.2d, v2.2d, v1.2d
+; CHECK-NEXT: uzp2 v4.2d, v0.2d, v3.2d
+; CHECK-NEXT: uzp1 v0.2d, v0.2d, v3.2d
+; CHECK-NEXT: uzp2 v3.2d, v2.2d, v1.2d
+; CHECK-NEXT: uzp1 v1.2d, v2.2d, v1.2d
; CHECK-NEXT: fadd v0.2d, v0.2d, v1.2d
; CHECK-NEXT: fadd v1.2d, v4.2d, v3.2d
; CHECK-NEXT: faddp d0, v0.2d
diff --git a/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll b/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll
index 09b6072e8aee2..1a746a6ded1e6 100644
--- a/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll
@@ -5,91 +5,18 @@
; RUN: llc -mtriple=aarch64-linux-gnu --lower-interleaved-accesses=false < %s -mattr=+sve -force-streaming-compatible | FileCheck %s --check-prefixes=SVE-FIXED,SVE-FIXED-IADISABLED
define void @deinterleave_i8_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_i8_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_i8_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.16b, v1.16b, v0.16b
-; NEON-IADISABLED-NEXT: uzp2 v0.16b, v1.16b, v0.16b
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_i8_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_i8_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
-; SVE-FIXED-NEXT: .cfi_def_cfa_offset 16
-; SVE-FIXED-NEXT: .cfi_offset b8, -16
-; SVE-FIXED-NEXT: ldp q0, q1, [x0]
-; SVE-FIXED-NEXT: mov z2.b, z1.b[15]
-; SVE-FIXED-NEXT: mov z3.b, z1.b[13]
-; SVE-FIXED-NEXT: mov z4.b, z1.b[11]
-; SVE-FIXED-NEXT: mov z5.b, z1.b[9]
-; SVE-FIXED-NEXT: mov z6.b, z1.b[7]
-; SVE-FIXED-NEXT: mov z7.b, z1.b[5]
-; SVE-FIXED-NEXT: mov z18.b, z0.b[15]
-; SVE-FIXED-NEXT: mov z19.b, z0.b[13]
-; SVE-FIXED-NEXT: mov z20.b, z1.b[14]
-; SVE-FIXED-NEXT: mov z21.b, z1.b[12]
-; SVE-FIXED-NEXT: mov z16.b, z1.b[3]
-; SVE-FIXED-NEXT: mov z17.b, z1.b[1]
-; SVE-FIXED-NEXT: zip1 z2.b, z3.b, z2.b
-; SVE-FIXED-NEXT: zip1 z3.b, z5.b, z4.b
-; SVE-FIXED-NEXT: zip1 z4.b, z7.b, z6.b
-; SVE-FIXED-NEXT: zip1 z6.b, z19.b, z18.b
-; SVE-FIXED-NEXT: mov z22.b, z1.b[6]
-; SVE-FIXED-NEXT: mov z23.b, z1.b[4]
-; SVE-FIXED-NEXT: zip1 z19.b, z21.b, z20.b
-; SVE-FIXED-NEXT: mov z20.b, z1.b[10]
-; SVE-FIXED-NEXT: mov z21.b, z1.b[8]
-; SVE-FIXED-NEXT: mov z24.b, z1.b[2]
-; SVE-FIXED-NEXT: mov z25.b, z0.b[14]
-; SVE-FIXED-NEXT: mov z26.b, z0.b[12]
-; SVE-FIXED-NEXT: mov z27.b, z0.b[10]
-; SVE-FIXED-NEXT: mov z28.b, z0.b[8]
-; SVE-FIXED-NEXT: mov z29.b, z0.b[6]
-; SVE-FIXED-NEXT: mov z30.b, z0.b[4]
-; SVE-FIXED-NEXT: mov z31.b, z0.b[2]
-; SVE-FIXED-NEXT: zip1 z5.b, z17.b, z16.b
-; SVE-FIXED-NEXT: mov z7.b, z0.b[11]
-; SVE-FIXED-NEXT: mov z16.b, z0.b[9]
-; SVE-FIXED-NEXT: mov z17.b, z0.b[7]
-; SVE-FIXED-NEXT: mov z18.b, z0.b[5]
-; SVE-FIXED-NEXT: mov z8.b, z0.b[3]
-; SVE-FIXED-NEXT: zip1 z20.b, z21.b, z20.b
-; SVE-FIXED-NEXT: mov z21.b, z0.b[1]
-; SVE-FIXED-NEXT: zip1 z22.b, z23.b, z22.b
-; SVE-FIXED-NEXT: zip1 z1.b, z1.b, z24.b
-; SVE-FIXED-NEXT: zip1 z23.b, z26.b, z25.b
-; SVE-FIXED-NEXT: zip1 z24.b, z28.b, z27.b
-; SVE-FIXED-NEXT: zip1 z25.b, z30.b, z29.b
-; SVE-FIXED-NEXT: zip1 z0.b, z0.b, z31.b
-; SVE-FIXED-NEXT: zip1 z7.b, z16.b, z7.b
-; SVE-FIXED-NEXT: zip1 z16.b, z18.b, z17.b
-; SVE-FIXED-NEXT: zip1 z17.b, z21.b, z8.b
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z20.h, z19.h
-; SVE-FIXED-NEXT: zip1 z1.h, z1.h, z22.h
-; SVE-FIXED-NEXT: zip1 z18.h, z24.h, z23.h
-; SVE-FIXED-NEXT: zip1 z4.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z25.h
-; SVE-FIXED-NEXT: zip1 z5.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z6.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z3.s
-; SVE-FIXED-NEXT: zip1 z2.s, z4.s, z2.s
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z18.s
-; SVE-FIXED-NEXT: zip1 z3.s, z6.s, z5.s
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
-; SVE-FIXED-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
+; SVE-FIXED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <32 x i8>, ptr %ptr, align 1
%deinterleave = tail call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> %load)
@@ -101,55 +28,18 @@ define void @deinterleave_i8_factor2(ptr %ptr) {
}
define void @deinterleave_i16_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_i16_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_i16_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.8h, v1.8h, v0.8h
-; NEON-IADISABLED-NEXT: uzp2 v0.8h, v1.8h, v0.8h
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_i16_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_i16_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: mov z2.h, z0.h[7]
-; SVE-FIXED-NEXT: mov z3.h, z0.h[5]
-; SVE-FIXED-NEXT: mov z7.h, z0.h[6]
-; SVE-FIXED-NEXT: mov z16.h, z0.h[4]
-; SVE-FIXED-NEXT: mov z17.h, z0.h[2]
-; SVE-FIXED-NEXT: mov z18.h, z1.h[6]
-; SVE-FIXED-NEXT: mov z19.h, z1.h[4]
-; SVE-FIXED-NEXT: mov z20.h, z1.h[2]
-; SVE-FIXED-NEXT: mov z4.h, z0.h[3]
-; SVE-FIXED-NEXT: mov z5.h, z0.h[1]
-; SVE-FIXED-NEXT: mov z6.h, z1.h[7]
-; SVE-FIXED-NEXT: mov z21.h, z1.h[5]
-; SVE-FIXED-NEXT: mov z22.h, z1.h[3]
-; SVE-FIXED-NEXT: mov z23.h, z1.h[1]
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z16.h, z7.h
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z17.h
-; SVE-FIXED-NEXT: zip1 z7.h, z19.h, z18.h
-; SVE-FIXED-NEXT: zip1 z1.h, z1.h, z20.h
-; SVE-FIXED-NEXT: zip1 z4.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z5.h, z21.h, z6.h
-; SVE-FIXED-NEXT: zip1 z6.h, z23.h, z22.h
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z3.s
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z7.s
-; SVE-FIXED-NEXT: zip1 z2.s, z4.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z6.s, z5.s
-; SVE-FIXED-NEXT: zip1 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
+; SVE-FIXED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <16 x i16>, ptr %ptr, align 2
%deinterleave = tail call { <8 x i16>, <8 x i16> } @llvm.vector.deinterleave2.v16i16(<16 x i16> %load)
@@ -161,39 +51,18 @@ define void @deinterleave_i16_factor2(ptr %ptr) {
}
define void @deinterleave_8xi32_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_8xi32_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_8xi32_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_8xi32_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_8xi32_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q0, q1, [x0]
-; SVE-FIXED-NEXT: mov z3.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z4.s, z0.s[2]
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z5.s, z1.s[1]
-; SVE-FIXED-NEXT: mov z6.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z7.s, z0.s[1]
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z3.s
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z4.s
-; SVE-FIXED-NEXT: zip1 z2.s, z5.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z7.s, z6.s
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
+; SVE-FIXED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <8 x i32>, ptr %ptr, align 4
%deinterleave = tail call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %load)
@@ -205,29 +74,18 @@ define void @deinterleave_8xi32_factor2(ptr %ptr) {
}
define void @deinterleave_i64_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_i64_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_i64_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: zip2 v0.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_i64_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_i64_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: zip1 z2.d, z1.d, z0.d
-; SVE-FIXED-NEXT: trn2 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: // fake_use: $q2 $z2
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
+; SVE-FIXED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <4 x i64>, ptr %ptr, align 8
%deinterleave = tail call { <2 x i64>, <2 x i64> } @llvm.vector.deinterleave2.v4i64(<4 x i64> %load)
@@ -239,39 +97,18 @@ define void @deinterleave_i64_factor2(ptr %ptr) {
}
define void @deinterleave_float_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_float_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_float_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_float_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_float_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q0, q1, [x0]
-; SVE-FIXED-NEXT: mov z3.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z4.s, z0.s[2]
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z5.s, z1.s[1]
-; SVE-FIXED-NEXT: mov z6.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z7.s, z0.s[1]
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z3.s
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z4.s
-; SVE-FIXED-NEXT: zip1 z2.s, z5.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z7.s, z6.s
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
+; SVE-FIXED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <8 x float>, ptr %ptr, align 4
%deinterleave = tail call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %load)
@@ -283,29 +120,18 @@ define void @deinterleave_float_factor2(ptr %ptr) {
}
define void @deinterleave_double_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_double_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_double_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: zip2 v0.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_double_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_double_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: zip1 z2.d, z1.d, z0.d
-; SVE-FIXED-NEXT: trn2 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: // fake_use: $q2 $z2
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
+; SVE-FIXED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <4 x double>, ptr %ptr, align 8
%deinterleave = tail call { <2 x double>, <2 x double> } @llvm.vector.deinterleave2.v4f64(<4 x double> %load)
@@ -317,29 +143,18 @@ define void @deinterleave_double_factor2(ptr %ptr) {
}
define void @deinterleave_ptr_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_ptr_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_ptr_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: zip2 v0.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_ptr_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_ptr_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: zip1 z2.d, z1.d, z0.d
-; SVE-FIXED-NEXT: trn2 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: // fake_use: $q2 $z2
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
+; SVE-FIXED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <4 x ptr>, ptr %ptr, align 8
%deinterleave = tail call { <2 x ptr>, <2 x ptr> } @llvm.vector.deinterleave2.v4p0(<4 x ptr> %load)
@@ -351,57 +166,19 @@ define void @deinterleave_ptr_factor2(ptr %ptr) {
}
define void @interleave_i8_factor2(ptr %ptr, <16 x i8> %l, <16 x i8> %r) {
-; NEON-IAENABLED-LABEL: interleave_i8_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.16b, v1.16b }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i8_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i8_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.16b, v1.16b }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i8_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.b, z1.b[15]
-; SVE-FIXED-NEXT: mov z3.b, z0.b[15]
-; SVE-FIXED-NEXT: mov z4.b, z1.b[14]
-; SVE-FIXED-NEXT: mov z5.b, z0.b[14]
-; SVE-FIXED-NEXT: mov z6.b, z1.b[13]
-; SVE-FIXED-NEXT: mov z7.b, z0.b[13]
-; SVE-FIXED-NEXT: mov z16.b, z1.b[12]
-; SVE-FIXED-NEXT: mov z17.b, z0.b[12]
-; SVE-FIXED-NEXT: mov z18.b, z1.b[11]
-; SVE-FIXED-NEXT: mov z19.b, z0.b[11]
-; SVE-FIXED-NEXT: mov z20.b, z1.b[10]
-; SVE-FIXED-NEXT: mov z21.b, z0.b[10]
-; SVE-FIXED-NEXT: mov z22.b, z1.b[9]
-; SVE-FIXED-NEXT: mov z23.b, z0.b[9]
-; SVE-FIXED-NEXT: mov z24.b, z1.b[8]
-; SVE-FIXED-NEXT: mov z25.b, z0.b[8]
-; SVE-FIXED-NEXT: zip1 z2.b, z3.b, z2.b
-; SVE-FIXED-NEXT: zip1 z3.b, z5.b, z4.b
-; SVE-FIXED-NEXT: zip1 z4.b, z7.b, z6.b
-; SVE-FIXED-NEXT: zip1 z5.b, z17.b, z16.b
-; SVE-FIXED-NEXT: zip1 z6.b, z19.b, z18.b
-; SVE-FIXED-NEXT: zip1 z7.b, z21.b, z20.b
-; SVE-FIXED-NEXT: zip1 z16.b, z23.b, z22.b
-; SVE-FIXED-NEXT: zip1 z0.b, z0.b, z1.b
-; SVE-FIXED-NEXT: zip1 z17.b, z25.b, z24.b
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.b, vl16
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2b { z0.b, z1.b }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %l, <16 x i8> %r)
store <32 x i8> %interleave, ptr %ptr, align 1
@@ -409,41 +186,19 @@ define void @interleave_i8_factor2(ptr %ptr, <16 x i8> %l, <16 x i8> %r) {
}
define void @interleave_i16_factor2(ptr %ptr, <8 x i16> %l, <8 x i16> %r) {
-; NEON-IAENABLED-LABEL: interleave_i16_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i16_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i16_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i16_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.h, z1.h[7]
-; SVE-FIXED-NEXT: mov z3.h, z0.h[7]
-; SVE-FIXED-NEXT: mov z4.h, z1.h[6]
-; SVE-FIXED-NEXT: mov z5.h, z0.h[6]
-; SVE-FIXED-NEXT: mov z6.h, z1.h[5]
-; SVE-FIXED-NEXT: mov z7.h, z0.h[5]
-; SVE-FIXED-NEXT: mov z16.h, z1.h[4]
-; SVE-FIXED-NEXT: mov z17.h, z0.h[4]
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z1.h
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.h, vl8
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2h { z0.h, z1.h }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %l, <8 x i16> %r)
store <16 x i16> %interleave, ptr %ptr, align 2
@@ -451,33 +206,19 @@ define void @interleave_i16_factor2(ptr %ptr, <8 x i16> %l, <8 x i16> %r) {
}
define void @interleave_i32_factor2(ptr %ptr, <4 x i32> %l, <4 x i32> %r) {
-; NEON-IAENABLED-LABEL: interleave_i32_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i32_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i32_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i32_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %l, <4 x i32> %r)
store <8 x i32> %interleave, ptr %ptr, align 4
@@ -485,27 +226,19 @@ define void @interleave_i32_factor2(ptr %ptr, <4 x i32> %l, <4 x i32> %r) {
}
define void @interleave_i64_factor2(ptr %ptr, <2 x i64> %l, <2 x i64> %r) {
-; NEON-IAENABLED-LABEL: interleave_i64_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i64_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i64_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i64_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %l, <2 x i64> %r)
store <4 x i64> %interleave, ptr %ptr, align 8
@@ -513,33 +246,19 @@ define void @interleave_i64_factor2(ptr %ptr, <2 x i64> %l, <2 x i64> %r) {
}
define void @interleave_float_factor2(ptr %ptr, <4 x float> %l, <4 x float> %r) {
-; NEON-IAENABLED-LABEL: interleave_float_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_float_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_float_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_float_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %l, <4 x float> %r)
store <8 x float> %interleave, ptr %ptr, align 4
@@ -547,27 +266,19 @@ define void @interleave_float_factor2(ptr %ptr, <4 x float> %l, <4 x float> %r)
}
define void @interleave_double_factor2(ptr %ptr, <2 x double> %l, <2 x double> %r) {
-; NEON-IAENABLED-LABEL: interleave_double_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_double_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_double_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_double_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %l, <2 x double> %r)
store <4 x double> %interleave, ptr %ptr, align 4
@@ -575,27 +286,19 @@ define void @interleave_double_factor2(ptr %ptr, <2 x double> %l, <2 x double> %
}
define void @interleave_ptr_factor2(ptr %ptr, <2 x ptr> %l, <2 x ptr> %r) {
-; NEON-IAENABLED-LABEL: interleave_ptr_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_ptr_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_ptr_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_ptr_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x ptr> @llvm.vector.interleave2.v4p0(<2 x ptr> %l, <2 x ptr> %r)
store <4 x ptr> %interleave, ptr %ptr, align 4
@@ -727,18 +430,19 @@ define void @interleave_wide_ptr_factor2(ptr %ptr, <8 x ptr> %l, <8 x ptr> %r) {
;
; NEON-IADISABLED-LABEL: interleave_wide_ptr_factor2:
; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v16.2d, v3.2d, v7.2d
-; NEON-IADISABLED-NEXT: zip1 v3.2d, v3.2d, v7.2d
-; NEON-IADISABLED-NEXT: zip2 v7.2d, v2.2d, v6.2d
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v2.2d, v6.2d
-; NEON-IADISABLED-NEXT: zip2 v6.2d, v1.2d, v5.2d
-; NEON-IADISABLED-NEXT: zip1 v1.2d, v1.2d, v5.2d
-; NEON-IADISABLED-NEXT: stp q3, q16, [x0, #96]
-; NEON-IADISABLED-NEXT: zip2 v3.2d, v0.2d, v4.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v4.2d
-; NEON-IADISABLED-NEXT: stp q1, q6, [x0, #32]
-; NEON-IADISABLED-NEXT: stp q2, q7, [x0, #64]
-; NEON-IADISABLED-NEXT: stp q0, q3, [x0]
+; NEON-IADISABLED-NEXT: // kill: def $q7 killed $q7 killed $q6_q7 def $q6_q7
+; NEON-IADISABLED-NEXT: mov v17.16b, v6.16b
+; NEON-IADISABLED-NEXT: // kill: def $q5 killed $q5 killed $q4_q5 def $q4_q5
+; NEON-IADISABLED-NEXT: mov v19.16b, v4.16b
+; NEON-IADISABLED-NEXT: add x8, x0, #64
+; NEON-IADISABLED-NEXT: mov v6.16b, v3.16b
+; NEON-IADISABLED-NEXT: mov v16.16b, v2.16b
+; NEON-IADISABLED-NEXT: mov v4.16b, v1.16b
+; NEON-IADISABLED-NEXT: mov v18.16b, v0.16b
+; NEON-IADISABLED-NEXT: st2 { v16.2d, v17.2d }, [x8], #32
+; NEON-IADISABLED-NEXT: st2 { v18.2d, v19.2d }, [x0], #32
+; NEON-IADISABLED-NEXT: st2 { v6.2d, v7.2d }, [x8]
+; NEON-IADISABLED-NEXT: st2 { v4.2d, v5.2d }, [x0]
; NEON-IADISABLED-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_wide_ptr_factor2:
@@ -770,27 +474,19 @@ define void @interleave_wide_ptr_factor2(ptr %ptr, <8 x ptr> %l, <8 x ptr> %r) {
}
define void @interleave_double_factor2_intrinsic(ptr %ptr, <2 x double> %l, <2 x double> %r) {
-; NEON-IAENABLED-LABEL: interleave_double_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_double_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_double_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_double_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %l, <2 x double> %r)
store <4 x double> %interleave, ptr %ptr, align 4
@@ -798,33 +494,19 @@ define void @interleave_double_factor2_intrinsic(ptr %ptr, <2 x double> %l, <2 x
}
define void @interleave_float_factor2_intrinsic(ptr %ptr, <4 x float> %l, <4 x float> %r) {
-; NEON-IAENABLED-LABEL: interleave_float_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_float_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_float_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_float_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %l, <4 x float> %r)
store <8 x float> %interleave, ptr %ptr, align 4
@@ -832,41 +514,19 @@ define void @interleave_float_factor2_intrinsic(ptr %ptr, <4 x float> %l, <4 x f
}
define void @interleave_i16_factor2_intrinsic(ptr %ptr, <8 x i16> %l, <8 x i16> %r) {
-; NEON-IAENABLED-LABEL: interleave_i16_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i16_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i16_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i16_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.h, z1.h[7]
-; SVE-FIXED-NEXT: mov z3.h, z0.h[7]
-; SVE-FIXED-NEXT: mov z4.h, z1.h[6]
-; SVE-FIXED-NEXT: mov z5.h, z0.h[6]
-; SVE-FIXED-NEXT: mov z6.h, z1.h[5]
-; SVE-FIXED-NEXT: mov z7.h, z0.h[5]
-; SVE-FIXED-NEXT: mov z16.h, z1.h[4]
-; SVE-FIXED-NEXT: mov z17.h, z0.h[4]
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z1.h
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.h, vl8
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2h { z0.h, z1.h }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %l, <8 x i16> %r)
store <16 x i16> %interleave, ptr %ptr, align 2
@@ -874,33 +534,19 @@ define void @interleave_i16_factor2_intrinsic(ptr %ptr, <8 x i16> %l, <8 x i16>
}
define void @interleave_i32_factor2_intrinsic(ptr %ptr, <4 x i32> %l, <4 x i32> %r) {
-; NEON-IAENABLED-LABEL: interleave_i32_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i32_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i32_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i32_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %l, <4 x i32> %r)
store <8 x i32> %interleave, ptr %ptr, align 4
@@ -908,27 +554,19 @@ define void @interleave_i32_factor2_intrinsic(ptr %ptr, <4 x i32> %l, <4 x i32>
}
define void @interleave_i64_factor2_intrinsic(ptr %ptr, <2 x i64> %l, <2 x i64> %r) {
-; NEON-IAENABLED-LABEL: interleave_i64_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i64_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i64_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i64_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %l, <2 x i64> %r)
store <4 x i64> %interleave, ptr %ptr, align 8
@@ -936,57 +574,19 @@ define void @interleave_i64_factor2_intrinsic(ptr %ptr, <2 x i64> %l, <2 x i64>
}
define void @interleave_i8_factor2_intrinsic(ptr %ptr, <16 x i8> %l, <16 x i8> %r) {
-; NEON-IAENABLED-LABEL: interleave_i8_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.16b, v1.16b }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i8_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i8_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.16b, v1.16b }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i8_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.b, z1.b[15]
-; SVE-FIXED-NEXT: mov z3.b, z0.b[15]
-; SVE-FIXED-NEXT: mov z4.b, z1.b[14]
-; SVE-FIXED-NEXT: mov z5.b, z0.b[14]
-; SVE-FIXED-NEXT: mov z6.b, z1.b[13]
-; SVE-FIXED-NEXT: mov z7.b, z0.b[13]
-; SVE-FIXED-NEXT: mov z16.b, z1.b[12]
-; SVE-FIXED-NEXT: mov z17.b, z0.b[12]
-; SVE-FIXED-NEXT: mov z18.b, z1.b[11]
-; SVE-FIXED-NEXT: mov z19.b, z0.b[11]
-; SVE-FIXED-NEXT: mov z20.b, z1.b[10]
-; SVE-FIXED-NEXT: mov z21.b, z0.b[10]
-; SVE-FIXED-NEXT: mov z22.b, z1.b[9]
-; SVE-FIXED-NEXT: mov z23.b, z0.b[9]
-; SVE-FIXED-NEXT: mov z24.b, z1.b[8]
-; SVE-FIXED-NEXT: mov z25.b, z0.b[8]
-; SVE-FIXED-NEXT: zip1 z2.b, z3.b, z2.b
-; SVE-FIXED-NEXT: zip1 z3.b, z5.b, z4.b
-; SVE-FIXED-NEXT: zip1 z4.b, z7.b, z6.b
-; SVE-FIXED-NEXT: zip1 z5.b, z17.b, z16.b
-; SVE-FIXED-NEXT: zip1 z6.b, z19.b, z18.b
-; SVE-FIXED-NEXT: zip1 z7.b, z21.b, z20.b
-; SVE-FIXED-NEXT: zip1 z16.b, z23.b, z22.b
-; SVE-FIXED-NEXT: zip1 z0.b, z0.b, z1.b
-; SVE-FIXED-NEXT: zip1 z17.b, z25.b, z24.b
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.b, vl16
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2b { z0.b, z1.b }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %l, <16 x i8> %r)
store <32 x i8> %interleave, ptr %ptr, align 1
@@ -994,27 +594,19 @@ define void @interleave_i8_factor2_intrinsic(ptr %ptr, <16 x i8> %l, <16 x i8> %
}
define void @interleave_ptr_factor2_intrinsic(ptr %ptr, <2 x ptr> %l, <2 x ptr> %r) {
-; NEON-IAENABLED-LABEL: interleave_ptr_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_ptr_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_ptr_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_ptr_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x ptr> @llvm.vector.interleave2.v4p0(<2 x ptr> %l, <2 x ptr> %r)
store <4 x ptr> %interleave, ptr %ptr, align 4
@@ -1043,18 +635,19 @@ define void @interleave_wide_ptr_factor2_intrinsic(ptr %ptr, <8 x ptr> %l, <8 x
;
; NEON-IADISABLED-LABEL: interleave_wide_ptr_factor2_intrinsic:
; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v16.2d, v3.2d, v7.2d
-; NEON-IADISABLED-NEXT: zip1 v3.2d, v3.2d, v7.2d
-; NEON-IADISABLED-NEXT: zip2 v7.2d, v2.2d, v6.2d
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v2.2d, v6.2d
-; NEON-IADISABLED-NEXT: zip2 v6.2d, v1.2d, v5.2d
-; NEON-IADISABLED-NEXT: zip1 v1.2d, v1.2d, v5.2d
-; NEON-IADISABLED-NEXT: stp q3, q16, [x0, #96]
-; NEON-IADISABLED-NEXT: zip2 v3.2d, v0.2d, v4.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v4.2d
-; NEON-IADISABLED-NEXT: stp q1, q6, [x0, #32]
-; NEON-IADISABLED-NEXT: stp q2, q7, [x0, #64]
-; NEON-IADISABLED-NEXT: stp q0, q3, [x0]
+; NEON-IADISABLED-NEXT: // kill: def $q7 killed $q7 killed $q6_q7 def $q6_q7
+; NEON-IADISABLED-NEXT: mov v17.16b, v6.16b
+; NEON-IADISABLED-NEXT: // kill: def $q5 killed $q5 killed $q4_q5 def $q4_q5
+; NEON-IADISABLED-NEXT: mov v19.16b, v4.16b
+; NEON-IADISABLED-NEXT: add x8, x0, #64
+; NEON-IADISABLED-NEXT: mov v6.16b, v3.16b
+; NEON-IADISABLED-NEXT: mov v16.16b, v2.16b
+; NEON-IADISABLED-NEXT: mov v4.16b, v1.16b
+; NEON-IADISABLED-NEXT: mov v18.16b, v0.16b
+; NEON-IADISABLED-NEXT: st2 { v16.2d, v17.2d }, [x8], #32
+; NEON-IADISABLED-NEXT: st2 { v18.2d, v19.2d }, [x0], #32
+; NEON-IADISABLED-NEXT: st2 { v6.2d, v7.2d }, [x8]
+; NEON-IADISABLED-NEXT: st2 { v4.2d, v5.2d }, [x0]
; NEON-IADISABLED-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_wide_ptr_factor2_intrinsic:
@@ -1086,6 +679,5 @@ define void @interleave_wide_ptr_factor2_intrinsic(ptr %ptr, <8 x ptr> %l, <8 x
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; NEON: {{.*}}
; SVE-FIXED-IADISABLED: {{.*}}
; SVE-FIXED-IAENABLED: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll b/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll
index 1278606f5b63f..3c0dc8d99dc76 100644
--- a/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll
@@ -5,20 +5,15 @@
define void @store_factor2_intrinsic(ptr %ptr, <16 x i16> %v0, <16 x i16> %v1) vscale_range(2,2) {
; CHECK-LABEL: store_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.h, vl8
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI0_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI0_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h
-; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
-; CHECK-NEXT: tbl z1.h, { z1.h }, z4.h
-; CHECK-NEXT: tbl z0.h, { z0.h }, z4.h
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h
+; CHECK-NEXT: splice z4.h, p0, z4.h, z1.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: st2h { z4.h, z5.h }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <32 x i16> @llvm.vector.interleave2.v32i16(<16 x i16> %v0, <16 x i16> %v1)
store <32 x i16> %interleaved.vec, ptr %ptr, align 4
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
index 426fb4b472cbe..625de777a9583 100644
--- a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
@@ -1,25 +1,16 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64-none-linux-gnu -lower-interleaved-accesses=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-linux-gnu -lower-interleaved-accesses=false -global-isel -global-isel-abort=0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {
-; CHECK-SD-LABEL: vector_deinterleave_v2f16_v4f16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: dup v1.2s, v0.s[1]
-; CHECK-SD-NEXT: zip1 v2.4h, v0.4h, v1.4h
-; CHECK-SD-NEXT: trn2 v1.4h, v0.4h, v1.4h
-; CHECK-SD-NEXT: fmov d0, d2
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vector_deinterleave_v2f16_v4f16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: uzp1 v2.4h, v0.4h, v0.4h
-; CHECK-GI-NEXT: uzp2 v1.4h, v0.4h, v0.4h
-; CHECK-GI-NEXT: fmov d0, d2
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vector_deinterleave_v2f16_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: uzp1 v2.4h, v0.4h, v0.4h
+; CHECK-NEXT: uzp2 v1.4h, v0.4h, v0.4h
+; CHECK-NEXT: fmov d0, d2
+; CHECK-NEXT: ret
%retval = call {<2 x half>, <2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half> %vec)
ret {<2 x half>, <2 x half>} %retval
}
@@ -51,8 +42,8 @@ define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %
; CHECK-SD-LABEL: vector_deinterleave_v2f32_v4f32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov d1, v0.d[1]
-; CHECK-SD-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT: zip2 v1.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: uzp1 v2.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: uzp2 v1.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmov d0, d2
; CHECK-SD-NEXT: ret
;
@@ -79,12 +70,19 @@ ret {<4 x float>, <4 x float>} %retval
}
define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
-; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
-; CHECK-NEXT: mov v0.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vector_deinterleave_v2f64_v4f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uzp1 v2.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: uzp2 v1.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: mov v0.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vector_deinterleave_v2f64_v4f64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: zip1 v2.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: zip2 v1.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%retval = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec)
ret {<2 x double>, <2 x double>} %retval
}
@@ -125,12 +123,19 @@ define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_v8i32(<8 x i32> %vec) {
}
define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
-; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
-; CHECK-NEXT: mov v0.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vector_deinterleave_v2i64_v4i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uzp1 v2.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: uzp2 v1.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: mov v0.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vector_deinterleave_v2i64_v4i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: zip1 v2.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: zip2 v1.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%retval = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec)
ret {<2 x i64>, <2 x i64>} %retval
}
@@ -505,11 +510,12 @@ define {<2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: .cfi_def_cfa_offset 96
-; CHECK-NEXT: stp q0, q1, [sp]
-; CHECK-NEXT: add x8, sp, #48
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp q2, q3, [sp, #32]
-; CHECK-NEXT: stp q4, q5, [sp, #64]
+; CHECK-NEXT: stp q4, q5, [sp, #16]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: str q3, [sp]
+; CHECK-NEXT: stp q1, q2, [sp, #64]
+; CHECK-NEXT: str q0, [sp, #48]
; CHECK-NEXT: ld3 { v5.2d, v6.2d, v7.2d }, [x8]
; CHECK-NEXT: ld3 { v16.2d, v17.2d, v18.2d }, [x9]
; CHECK-NEXT: uzp1 v0.2d, v16.2d, v5.2d
@@ -535,11 +541,12 @@ define {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} @deint
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: .cfi_def_cfa_offset 96
-; CHECK-NEXT: stp q0, q1, [sp]
-; CHECK-NEXT: add x8, sp, #48
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp q2, q3, [sp, #32]
-; CHECK-NEXT: stp q4, q5, [sp, #64]
+; CHECK-NEXT: stp q4, q5, [sp, #16]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: str q3, [sp]
+; CHECK-NEXT: stp q1, q2, [sp, #64]
+; CHECK-NEXT: str q0, [sp, #48]
; CHECK-NEXT: ld3 { v5.4s, v6.4s, v7.4s }, [x8]
; CHECK-NEXT: ld3 { v16.4s, v17.4s, v18.4s }, [x9]
; CHECK-NEXT: uzp1 v0.4s, v16.4s, v5.4s
@@ -565,11 +572,12 @@ define {<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>} @deint
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: stp d4, d5, [sp, #32]
-; CHECK-NEXT: add x8, sp, #24
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp d2, d3, [sp, #16]
-; CHECK-NEXT: stp d0, d1, [sp]
+; CHECK-NEXT: stp d4, d5, [sp, #8]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #24
+; CHECK-NEXT: str d3, [sp]
+; CHECK-NEXT: stp d1, d2, [sp, #32]
+; CHECK-NEXT: str d0, [sp, #24]
; CHECK-NEXT: ld3 { v5.2s, v6.2s, v7.2s }, [x8]
; CHECK-NEXT: ld3 { v16.2s, v17.2s, v18.2s }, [x9]
; CHECK-NEXT: uzp1 v0.2s, v16.2s, v5.2s
@@ -595,11 +603,12 @@ define {<8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: .cfi_def_cfa_offset 96
-; CHECK-NEXT: stp q0, q1, [sp]
-; CHECK-NEXT: add x8, sp, #48
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp q2, q3, [sp, #32]
-; CHECK-NEXT: stp q4, q5, [sp, #64]
+; CHECK-NEXT: stp q4, q5, [sp, #16]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: str q3, [sp]
+; CHECK-NEXT: stp q1, q2, [sp, #64]
+; CHECK-NEXT: str q0, [sp, #48]
; CHECK-NEXT: ld3 { v5.8h, v6.8h, v7.8h }, [x8]
; CHECK-NEXT: ld3 { v16.8h, v17.8h, v18.8h }, [x9]
; CHECK-NEXT: uzp1 v0.8h, v16.8h, v5.8h
@@ -625,11 +634,12 @@ define {<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>} @deint
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: stp d4, d5, [sp, #32]
-; CHECK-NEXT: add x8, sp, #24
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp d2, d3, [sp, #16]
-; CHECK-NEXT: stp d0, d1, [sp]
+; CHECK-NEXT: stp d4, d5, [sp, #8]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #24
+; CHECK-NEXT: str d3, [sp]
+; CHECK-NEXT: stp d1, d2, [sp, #32]
+; CHECK-NEXT: str d0, [sp, #24]
; CHECK-NEXT: ld3 { v5.4h, v6.4h, v7.4h }, [x8]
; CHECK-NEXT: ld3 { v16.4h, v17.4h, v18.4h }, [x9]
; CHECK-NEXT: uzp1 v0.4h, v16.4h, v5.4h
@@ -655,11 +665,12 @@ define {<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>} @deint
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: .cfi_def_cfa_offset 96
-; CHECK-NEXT: stp q0, q1, [sp]
-; CHECK-NEXT: add x8, sp, #48
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp q2, q3, [sp, #32]
-; CHECK-NEXT: stp q4, q5, [sp, #64]
+; CHECK-NEXT: stp q4, q5, [sp, #16]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: str q3, [sp]
+; CHECK-NEXT: stp q1, q2, [sp, #64]
+; CHECK-NEXT: str q0, [sp, #48]
; CHECK-NEXT: ld3 { v5.16b, v6.16b, v7.16b }, [x8]
; CHECK-NEXT: ld3 { v16.16b, v17.16b, v18.16b }, [x9]
; CHECK-NEXT: uzp1 v0.16b, v16.16b, v5.16b
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll b/llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll
new file mode 100644
index 0000000000000..5dd9b3a4d8080
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll
@@ -0,0 +1,132 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s
+
+define { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @deinterleave5_v10i16(<10 x i16> %vec) {
+; CHECK-LABEL: deinterleave5_v10i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s1, w1
+; CHECK-NEXT: fmov s4, w4
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: fmov s3, w3
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: add x9, sp, #8
+; CHECK-NEXT: fmov s2, w2
+; CHECK-NEXT: mov v1.s[1], w6
+; CHECK-NEXT: ld1 { v4.h }[2], [x9]
+; CHECK-NEXT: mov v0.s[1], w5
+; CHECK-NEXT: ld1 { v3.h }[2], [x8]
+; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-NEXT: // kill: def $d4 killed $d4 killed $q4
+; CHECK-NEXT: mov v2.s[1], w7
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: // kill: def $d3 killed $d3 killed $q3
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: ret
+ %result = call { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @llvm.vector.deinterleave5.v10i16(<10 x i16> %vec)
+ ret { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } %result
+}
+
+define <10 x i16> @interleave5_v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e) {
+; CHECK-LABEL: interleave5_v10i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v5.16b, v0.16b
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3
+; CHECK-NEXT: // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT: mov w9, v0.s[1]
+; CHECK-NEXT: mov w10, v3.s[1]
+; CHECK-NEXT: mov w11, v4.s[1]
+; CHECK-NEXT: mov v5.h[1], v1.h[0]
+; CHECK-NEXT: fmov s0, w10
+; CHECK-NEXT: mov v5.h[2], v2.h[0]
+; CHECK-NEXT: mov v0.h[1], w11
+; CHECK-NEXT: mov v5.h[3], v3.h[0]
+; CHECK-NEXT: str s0, [x8, #16]
+; CHECK-NEXT: mov v5.h[4], v4.h[0]
+; CHECK-NEXT: mov v5.h[5], w9
+; CHECK-NEXT: mov w9, v1.s[1]
+; CHECK-NEXT: mov v5.h[6], w9
+; CHECK-NEXT: mov w9, v2.s[1]
+; CHECK-NEXT: mov v5.h[7], w9
+; CHECK-NEXT: str q5, [x8]
+; CHECK-NEXT: ret
+ %result = call <10 x i16> @llvm.vector.interleave5.v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e)
+ ret <10 x i16> %result
+}
+
+define { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @deinterleave7_v14i16(<14 x i16> %vec) {
+; CHECK-LABEL: deinterleave7_v14i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s3, w3
+; CHECK-NEXT: fmov s2, w2
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: fmov s1, w1
+; CHECK-NEXT: fmov s6, w6
+; CHECK-NEXT: add x9, sp, #8
+; CHECK-NEXT: fmov s5, w5
+; CHECK-NEXT: fmov s4, w4
+; CHECK-NEXT: add x10, sp, #16
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: ld1 { v2.h }[2], [x9]
+; CHECK-NEXT: ld1 { v3.h }[2], [x10]
+; CHECK-NEXT: ld1 { v1.h }[2], [x8]
+; CHECK-NEXT: add x8, sp, #24
+; CHECK-NEXT: add x9, sp, #32
+; CHECK-NEXT: add x10, sp, #40
+; CHECK-NEXT: ld1 { v4.h }[2], [x8]
+; CHECK-NEXT: ld1 { v5.h }[2], [x9]
+; CHECK-NEXT: mov v0.s[1], w7
+; CHECK-NEXT: ld1 { v6.h }[2], [x10]
+; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: // kill: def $d3 killed $d3 killed $q3
+; CHECK-NEXT: // kill: def $d4 killed $d4 killed $q4
+; CHECK-NEXT: // kill: def $d5 killed $d5 killed $q5
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: // kill: def $d6 killed $d6 killed $q6
+; CHECK-NEXT: ret
+ %result = call { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @llvm.vector.deinterleave7.v14i16(<14 x i16> %vec)
+ ret { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } %result
+}
+
+define <14 x i16> @interleave7_v14i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f, <2 x i16> %g) {
+; CHECK-LABEL: interleave7_v14i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v7.16b, v0.16b
+; CHECK-NEXT: mov w9, v1.s[1]
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3
+; CHECK-NEXT: // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT: // kill: def $d5 killed $d5 def $q5
+; CHECK-NEXT: // kill: def $d6 killed $d6 def $q6
+; CHECK-NEXT: mov w10, v2.s[1]
+; CHECK-NEXT: mov v7.h[1], v1.h[0]
+; CHECK-NEXT: fmov s16, w9
+; CHECK-NEXT: mov w9, v3.s[1]
+; CHECK-NEXT: mov v7.h[2], v2.h[0]
+; CHECK-NEXT: mov v16.h[1], w10
+; CHECK-NEXT: mov w10, v4.s[1]
+; CHECK-NEXT: mov v7.h[3], v3.h[0]
+; CHECK-NEXT: mov v16.h[2], w9
+; CHECK-NEXT: mov w9, v5.s[1]
+; CHECK-NEXT: mov v7.h[4], v4.h[0]
+; CHECK-NEXT: mov v16.h[3], w10
+; CHECK-NEXT: mov w10, v6.s[1]
+; CHECK-NEXT: mov v7.h[5], v5.h[0]
+; CHECK-NEXT: mov v16.h[4], w9
+; CHECK-NEXT: mov w9, v0.s[1]
+; CHECK-NEXT: mov v7.h[6], v6.h[0]
+; CHECK-NEXT: mov v16.h[5], w10
+; CHECK-NEXT: mov v7.h[7], w9
+; CHECK-NEXT: mov s0, v16.s[2]
+; CHECK-NEXT: str d16, [x8, #16]
+; CHECK-NEXT: str q7, [x8]
+; CHECK-NEXT: str s0, [x8, #24]
+; CHECK-NEXT: ret
+ %result = call <14 x i16> @llvm.vector.interleave7.v14i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f, <2 x i16> %g)
+ ret <14 x i16> %result
+}
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
index ab06111fb52ff..44a63298d18b8 100644
--- a/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=0 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64-none-linux-gnu -lower-interleaved-accesses=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
@@ -14,22 +14,12 @@ define <4 x half> @interleave2_v4f16(<2 x half> %vec0, <2 x half> %vec1) {
}
define <8 x half> @interleave2_v8f16(<4 x half> %vec0, <4 x half> %vec1) {
-; CHECK-SD-LABEL: interleave2_v8f16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-SD-NEXT: adrp x8, .LCPI1_0
-; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
-; CHECK-SD-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: interleave2_v8f16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-GI-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: interleave2_v8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: zip1 v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
%retval = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %vec0, <4 x half> %vec1)
ret <8 x half> %retval
}
@@ -46,21 +36,12 @@ define <16 x half> @interleave2_v16f16(<8 x half> %vec0, <8 x half> %vec1) {
}
define <4 x float> @interleave2_v4f32(<2 x float> %vec0, <2 x float> %vec1) {
-; CHECK-SD-LABEL: interleave2_v4f32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-SD-NEXT: rev64 v1.4s, v0.4s
-; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: interleave2_v4f32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-GI-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: interleave2_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: zip1 v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
%retval = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %vec0, <2 x float> %vec1)
ret <4 x float> %retval
}
@@ -187,11 +168,10 @@ define <4 x i16> @interleave2_diff_nonconst_splat_v4i16(i16 %a, i16 %b) {
; CHECK-SD-LABEL: interleave2_diff_nonconst_splat_v4i16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmov s0, w0
-; CHECK-SD-NEXT: mov v0.h[1], w0
-; CHECK-SD-NEXT: mov v0.h[2], w1
+; CHECK-SD-NEXT: mov v0.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w0
; CHECK-SD-NEXT: mov v0.h[3], w1
-; CHECK-SD-NEXT: rev32 v1.4h, v0.4h
-; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: interleave2_diff_nonconst_splat_v4i16:
@@ -565,20 +545,21 @@ define <12 x double> @interleave6_v12f64(<2 x double> %vec0, <2 x double> %vec1,
; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: zip1 v18.2d, v2.2d, v5.2d
; CHECK-NEXT: zip2 v7.2d, v2.2d, v5.2d
-; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: add x9, sp, #48
; CHECK-NEXT: zip1 v17.2d, v1.2d, v4.2d
; CHECK-NEXT: zip2 v6.2d, v1.2d, v4.2d
; CHECK-NEXT: zip1 v16.2d, v0.2d, v3.2d
; CHECK-NEXT: zip2 v5.2d, v0.2d, v3.2d
; CHECK-NEXT: st3 { v16.2d, v17.2d, v18.2d }, [x9]
-; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st3 { v5.2d, v6.2d, v7.2d }, [x9]
-; CHECK-NEXT: ldp q2, q0, [sp, #64]
-; CHECK-NEXT: ldp q5, q1, [sp, #32]
-; CHECK-NEXT: ldp q3, q4, [sp]
-; CHECK-NEXT: stp q2, q0, [x8, #64]
+; CHECK-NEXT: ldp q2, q0, [sp, #16]
+; CHECK-NEXT: ldr q1, [sp]
+; CHECK-NEXT: ldp q3, q4, [sp, #48]
+; CHECK-NEXT: ldr q5, [sp, #80]
; CHECK-NEXT: stp q5, q1, [x8, #32]
; CHECK-NEXT: stp q3, q4, [x8]
+; CHECK-NEXT: stp q2, q0, [x8, #64]
; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret
%retval = call <12 x double> @llvm.vector.interleave6.v12f64(<2 x double> %vec0, <2 x double> %vec1, <2 x double> %vec2, <2 x double> %vec3, <2 x double> %vec4, <2 x double> %vec5)
@@ -592,20 +573,21 @@ define <24 x i32> @interleave6_v24i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32
; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: zip1 v18.4s, v2.4s, v5.4s
; CHECK-NEXT: zip2 v7.4s, v2.4s, v5.4s
-; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: add x9, sp, #48
; CHECK-NEXT: zip1 v17.4s, v1.4s, v4.4s
; CHECK-NEXT: zip2 v6.4s, v1.4s, v4.4s
; CHECK-NEXT: zip1 v16.4s, v0.4s, v3.4s
; CHECK-NEXT: zip2 v5.4s, v0.4s, v3.4s
; CHECK-NEXT: st3 { v16.4s, v17.4s, v18.4s }, [x9]
-; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st3 { v5.4s, v6.4s, v7.4s }, [x9]
-; CHECK-NEXT: ldp q2, q0, [sp, #64]
-; CHECK-NEXT: ldp q5, q1, [sp, #32]
-; CHECK-NEXT: ldp q3, q4, [sp]
-; CHECK-NEXT: stp q2, q0, [x8, #64]
+; CHECK-NEXT: ldp q2, q0, [sp, #16]
+; CHECK-NEXT: ldr q1, [sp]
+; CHECK-NEXT: ldp q3, q4, [sp, #48]
+; CHECK-NEXT: ldr q5, [sp, #80]
; CHECK-NEXT: stp q5, q1, [x8, #32]
; CHECK-NEXT: stp q3, q4, [x8]
+; CHECK-NEXT: stp q2, q0, [x8, #64]
; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret
%retval = call <24 x i32> @llvm.vector.interleave6.v24i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5)
@@ -619,17 +601,18 @@ define <12 x i32> @interleave6_v12i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: zip1 v18.2s, v2.2s, v5.2s
; CHECK-NEXT: zip2 v7.2s, v2.2s, v5.2s
-; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: add x9, sp, #24
; CHECK-NEXT: zip1 v17.2s, v1.2s, v4.2s
; CHECK-NEXT: zip2 v6.2s, v1.2s, v4.2s
; CHECK-NEXT: zip1 v16.2s, v0.2s, v3.2s
; CHECK-NEXT: zip2 v5.2s, v0.2s, v3.2s
; CHECK-NEXT: st3 { v16.2s, v17.2s, v18.2s }, [x9]
-; CHECK-NEXT: add x9, sp, #24
+; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st3 { v5.2s, v6.2s, v7.2s }, [x9]
-; CHECK-NEXT: ldp d1, d0, [sp, #32]
-; CHECK-NEXT: ldp d3, d2, [sp, #16]
-; CHECK-NEXT: ldp d5, d4, [sp]
+; CHECK-NEXT: ldp d1, d0, [sp, #8]
+; CHECK-NEXT: ldr d2, [sp]
+; CHECK-NEXT: ldp d4, d3, [sp, #32]
+; CHECK-NEXT: ldr d5, [sp, #24]
; CHECK-NEXT: mov v1.d[1], v0.d[0]
; CHECK-NEXT: mov v3.d[1], v2.d[0]
; CHECK-NEXT: mov v5.d[1], v4.d[0]
@@ -648,17 +631,18 @@ define <24 x i16> @interleave6_v24i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: zip1 v18.4h, v2.4h, v5.4h
; CHECK-NEXT: zip2 v7.4h, v2.4h, v5.4h
-; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: add x9, sp, #24
; CHECK-NEXT: zip1 v17.4h, v1.4h, v4.4h
; CHECK-NEXT: zip2 v6.4h, v1.4h, v4.4h
; CHECK-NEXT: zip1 v16.4h, v0.4h, v3.4h
; CHECK-NEXT: zip2 v5.4h, v0.4h, v3.4h
; CHECK-NEXT: st3 { v16.4h, v17.4h, v18.4h }, [x9]
-; CHECK-NEXT: add x9, sp, #24
+; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st3 { v5.4h, v6.4h, v7.4h }, [x9]
-; CHECK-NEXT: ldp d1, d0, [sp, #32]
-; CHECK-NEXT: ldp d3, d2, [sp, #16]
-; CHECK-NEXT: ldp d5, d4, [sp]
+; CHECK-NEXT: ldp d1, d0, [sp, #8]
+; CHECK-NEXT: ldr d2, [sp]
+; CHECK-NEXT: ldp d4, d3, [sp, #32]
+; CHECK-NEXT: ldr d5, [sp, #24]
; CHECK-NEXT: mov v1.d[1], v0.d[0]
; CHECK-NEXT: mov v3.d[1], v2.d[0]
; CHECK-NEXT: mov v5.d[1], v4.d[0]
diff --git a/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll b/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
index da917119c6b25..0732c30c05992 100644
--- a/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
+++ b/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
@@ -349,10 +349,11 @@ define { <8 x i16>, <8 x i16> } @foo_ld2_v8i16(<8 x i1> %mask, ptr %p) {
define { <4 x float>, <4 x float> } @foo_ld2_v4f32(<4 x i1> %mask, ptr %p) {
; CHECK-LABEL: foo_ld2_v4f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI2_0
+; CHECK-NEXT: zip1 v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: shl v0.8b, v0.8b, #7
; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
@@ -419,10 +420,11 @@ define { <4 x float>, <4 x float> } @foo_ld2_v4f32(<4 x i1> %mask, ptr %p) {
define { <2 x double>, <2 x double> } @foo_ld2_v2f64(<2 x i1> %mask, ptr %p) {
; CHECK-LABEL: foo_ld2_v2f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI3_0
+; CHECK-NEXT: zip1 v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT: zip1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
@@ -453,8 +455,8 @@ define { <2 x double>, <2 x double> } @foo_ld2_v2f64(<2 x i1> %mask, ptr %p) {
; CHECK-NEXT: add x8, x0, #24
; CHECK-NEXT: ld1 { v2.d }[1], [x8]
; CHECK-NEXT: .LBB3_8: // %else8
-; CHECK-NEXT: zip1 v0.2d, v1.2d, v2.2d
-; CHECK-NEXT: zip2 v1.2d, v1.2d, v2.2d
+; CHECK-NEXT: uzp1 v0.2d, v1.2d, v2.2d
+; CHECK-NEXT: uzp2 v1.2d, v1.2d, v2.2d
; CHECK-NEXT: ret
%interleaved.mask = call <4 x i1> @llvm.vector.interleave2.v4i1(<2 x i1> %mask, <2 x i1> %mask)
%wide.masked.vec = call <4 x double> @llvm.masked.load.v4f64.p0(ptr %p, i32 8, <4 x i1> %interleaved.mask, <4 x double> poison)
diff --git a/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll b/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll
index 972be0fca2089..4d8a0e9e59b9a 100644
--- a/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll
+++ b/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll
@@ -345,10 +345,11 @@ define void @foo_st2_v8i16(<8 x i1> %mask, <8 x i16> %val1, <8 x i16> %val2, ptr
define void @foo_st2_v4i32(<4 x i1> %mask, <4 x i32> %val1, <4 x i32> %val2, ptr %p) {
; CHECK-LABEL: foo_st2_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI2_0
+; CHECK-NEXT: zip1 v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: shl v0.8b, v0.8b, #7
; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
; CHECK-NEXT: and v0.8b, v0.8b, v3.8b
@@ -413,10 +414,11 @@ define void @foo_st2_v4i32(<4 x i1> %mask, <4 x i32> %val1, <4 x i32> %val2, ptr
define void @foo_st2_v2i64(<2 x i1> %mask, <2 x i64> %val1, <2 x i64> %val2, ptr %p) {
; CHECK-LABEL: foo_st2_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI3_0
+; CHECK-NEXT: zip1 v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT: zip1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
; CHECK-NEXT: and v0.8b, v0.8b, v3.8b
diff --git a/llvm/test/CodeGen/AArch64/interleaved-accesses.ll b/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
index 2e52b3b373484..bfa6d5da749b0 100644
--- a/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
+++ b/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
@@ -2195,23 +2195,12 @@ define <4 x i1> @load_large_vector_intrinsic(ptr %p) {
}
define void @store_factor2_intrinsic(ptr %ptr, <8 x i8> %v0, <8 x i8> %v1) {
-; NEON-IAENABLED-LABEL: store_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; NEON-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; NEON-IAENABLED-NEXT: st2 { v0.8b, v1.8b }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: store_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; NEON-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; NEON-IADISABLED-NEXT: adrp x8, .LCPI41_0
-; NEON-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; NEON-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI41_0]
-; NEON-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; NEON-IADISABLED-NEXT: str q0, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: store_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; NEON-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; NEON-NEXT: st2 { v0.8b, v1.8b }, [x0]
+; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_factor2_intrinsic:
; NO_NEON: // %bb.0:
@@ -2247,25 +2236,15 @@ define void @store_factor2_intrinsic(ptr %ptr, <8 x i8> %v0, <8 x i8> %v1) {
}
define void @store_factor2_wide_intrinsic(ptr %ptr, <8 x i32> %v0, <8 x i32> %v1) {
-; NEON-IAENABLED-LABEL: store_factor2_wide_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: mov v5.16b, v2.16b
-; NEON-IAENABLED-NEXT: // kill: def $q3 killed $q3 def $q2_q3
-; NEON-IAENABLED-NEXT: mov v4.16b, v0.16b
-; NEON-IAENABLED-NEXT: mov v2.16b, v1.16b
-; NEON-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
-; NEON-IAENABLED-NEXT: st2 { v2.4s, v3.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: store_factor2_wide_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v4.4s, v1.4s, v3.4s
-; NEON-IADISABLED-NEXT: zip1 v1.4s, v1.4s, v3.4s
-; NEON-IADISABLED-NEXT: zip2 v3.4s, v0.4s, v2.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v2.4s
-; NEON-IADISABLED-NEXT: stp q1, q4, [x0, #32]
-; NEON-IADISABLED-NEXT: stp q0, q3, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: store_factor2_wide_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: mov v5.16b, v2.16b
+; NEON-NEXT: // kill: def $q3 killed $q3 def $q2_q3
+; NEON-NEXT: mov v4.16b, v0.16b
+; NEON-NEXT: mov v2.16b, v1.16b
+; NEON-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
+; NEON-NEXT: st2 { v2.4s, v3.4s }, [x0]
+; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_factor2_wide_intrinsic:
; NO_NEON: // %bb.0:
@@ -2826,19 +2805,12 @@ define void @store_general_mask_factor4_undefmulti_intrinsic(ptr %ptr, <32 x i32
}
define void @store_ptrvec_factor2_intrinsic(ptr %ptr, <2 x ptr> %v0, <2 x ptr> %v1) {
-; NEON-IAENABLED-LABEL: store_ptrvec_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: store_ptrvec_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: store_ptrvec_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_ptrvec_factor2_intrinsic:
; NO_NEON: // %bb.0:
@@ -2895,19 +2867,12 @@ define void @store_ptrvec_factor4_intrinsic(ptr %ptr, <2 x ptr> %v0, <2 x ptr> %
}
define void @store_undef_mask_factor2_intrinsic(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1) {
-; NEON-IAENABLED-LABEL: store_undef_mask_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: store_undef_mask_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: store_undef_mask_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_undef_mask_factor2_intrinsic:
; NO_NEON: // %bb.0:
diff --git a/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll b/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll
index 951f356ee1da5..32f43f03b2b16 100644
--- a/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll
+++ b/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll
@@ -2425,39 +2425,19 @@ entry:
}
define void @test_ldnp_interleaved_load2_v2i32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: str d2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x i32>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %loaded)
@@ -2470,37 +2450,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4i16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: xtn v1.4h, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-LE-IADISABLED-NEXT: str d1, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v1.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v1.4h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x i16>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <4 x i16>, <4 x i16> } @llvm.vector.deinterleave2.v8i16(<8 x i16> %loaded)
@@ -2513,37 +2475,19 @@ entry:
define void @test_ldnp_interleaved_load2_v8i8_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.8b, v1.8b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: xtn v1.8b, v0.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v0.16b
-; CHECK-LE-IADISABLED-NEXT: str d1, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.8b, v1.8b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.8b }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.8b }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.8b, v1.8b }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v1.16b, v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v1.8b }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8b }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.8b, v1.8b }, [x0]
+; CHECK-BE-NEXT: st1 { v0.8b }, [x1]
+; CHECK-BE-NEXT: st1 { v1.8b }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <16 x i8>, ptr %ptr, align 1, !nontemporal !0
%deinterleaved = call { <8 x i8>, <8 x i8> } @llvm.vector.deinterleave2.v16i8(<16 x i8> %loaded)
@@ -2556,39 +2500,19 @@ entry:
define void @test_ldnp_interleaved_load2_v2f32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: str d2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x float>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %loaded)
@@ -2601,37 +2525,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4f16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v1.8h, v0.8h, v0.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-LE-IADISABLED-NEXT: str d1, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v1.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v1.4h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x half>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <4 x half>, <4 x half> } @llvm.vector.deinterleave2.v8f16(<8 x half> %loaded)
@@ -2644,39 +2550,19 @@ entry:
define void @test_ldnp_interleaved_load2_v2i64_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2d }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2d }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2d }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2d }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x i64>, ptr %ptr, align 8, !nontemporal !0
%deinterleaved = call { <2 x i64>, <2 x i64> } @llvm.vector.deinterleave2.v4i64(<4 x i64> %loaded)
@@ -2689,39 +2575,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4i32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x i32>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %loaded)
@@ -2734,39 +2600,19 @@ entry:
define void @test_ldnp_interleaved_load2_v8i16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.8h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.8h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.8h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.8h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <16 x i16>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <8 x i16>, <8 x i16> } @llvm.vector.deinterleave2.v16i16(<16 x i16> %loaded)
@@ -2779,39 +2625,19 @@ entry:
define void @test_ldnp_interleaved_load2_v16i8_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.16b }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.16b }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.16b }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; CHECK-BE-NEXT: st1 { v0.16b }, [x1]
+; CHECK-BE-NEXT: st1 { v1.16b }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <32 x i8>, ptr %ptr, align 1, !nontemporal !0
%deinterleaved = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> %loaded)
@@ -2824,39 +2650,19 @@ entry:
define void @test_ldnp_interleaved_load2_v2f64_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2d }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2d }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2d }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2d }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x double>, ptr %ptr, align 8, !nontemporal !0
%deinterleaved = call { <2 x double>, <2 x double> } @llvm.vector.deinterleave2.v4f64(<4 x double> %loaded)
@@ -2869,39 +2675,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4f32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x float>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %loaded)
@@ -2914,39 +2700,19 @@ entry:
define void @test_ldnp_interleaved_load2_v8f16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.8h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.8h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.8h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.8h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <16 x half>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <8 x half>, <8 x half> } @llvm.vector.deinterleave2.v16f16(<16 x half> %loaded)
diff --git a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll
index ca1f86d83710c..452e2e56c8625 100644
--- a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll
+++ b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll
@@ -166,39 +166,19 @@ entry:
}
define void @test_stnp_interleaved_store2_v2i32_Os_intrinsic(<2 x i32> %v0, <2 x i32> %v1, ptr %ptr) #0 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %v0, <2 x i32> %v1)
store <4 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -207,39 +187,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i32_Oz_intrinsic(<2 x i32> %v0, <2 x i32> %v1, ptr %ptr) #1 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %v0, <2 x i32> %v1)
store <4 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -248,37 +208,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i64_Os_intrinsic(<2 x i64> %v0, <2 x i64> %v1, ptr %ptr) #0 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %v0, <2 x i64> %v1)
store <4 x i64> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -287,37 +229,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i64_Oz_intrinsic(<2 x i64> %v0, <2 x i64> %v1, ptr %ptr) #1 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %v0, <2 x i64> %v1)
store <4 x i64> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -328,6 +252,3 @@ entry:
attributes #0 = { optsize }
attributes #1 = { minsize optsize }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-BE: {{.*}}
-; CHECK-LE: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll
index 76b77530f2d16..9cbc98fc96814 100644
--- a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll
+++ b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll
@@ -2376,40 +2376,19 @@ entry:
}
define void @test_stnp_interleaved_store2_v2i32_intrinsic(<2 x i32> %v0, <2 x i32> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %v0, <2 x i32> %v1)
store <4 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2418,44 +2397,19 @@ entry:
define void @test_stnp_interleaved_store2_v4i16_intrinsic(<4 x i16> %v0, <4 x i16> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: adrp x8, .LCPI39_0
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI39_0]
-; CHECK-LE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.4h, v1.4h
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4h, v0.4h
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4h, v2.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4h, v0.4h
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4h, v1.4h
-; CHECK-BE-IADISABLED-NEXT: adrp x8, .LCPI39_0
-; CHECK-BE-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI39_0
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: rev16 v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.4h, v1.4h
+; CHECK-BE-NEXT: rev64 v1.4h, v0.4h
+; CHECK-BE-NEXT: st2 { v1.4h, v2.4h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x i16> @llvm.vector.interleave2.v8i16(<4 x i16> %v0, <4 x i16> %v1)
store <8 x i16> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -2464,43 +2418,19 @@ entry:
define void @test_stnp_interleaved_store2_v8i8_intrinsic(<8 x i8> %v0, <8 x i8> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.8b, v1.8b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: adrp x8, .LCPI40_0
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI40_0]
-; CHECK-LE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.8b, v1.8b
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.8b, v0.8b
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.8b, v2.8b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.8b, v1.8b }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.8b, v0.8b
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.8b, v1.8b
-; CHECK-BE-IADISABLED-NEXT: adrp x8, .LCPI40_0
-; CHECK-BE-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI40_0
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.8b, v1.8b
+; CHECK-BE-NEXT: rev64 v1.8b, v0.8b
+; CHECK-BE-NEXT: st2 { v1.8b, v2.8b }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <16 x i8> @llvm.vector.interleave2.v16i8(<8 x i8> %v0, <8 x i8> %v1)
store <16 x i8> %interleave, ptr %ptr, align 1, !nontemporal !0
@@ -2509,40 +2439,19 @@ entry:
define void @test_stnp_interleaved_store2_v2f32_intrinsic(<2 x float> %v0, <2 x float> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %v0, <2 x float> %v1)
store <4 x float> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2551,44 +2460,19 @@ entry:
define void @test_stnp_interleaved_store2_v4f16_intrinsic(<4 x half> %v0, <4 x half> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: adrp x8, .LCPI42_0
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI42_0]
-; CHECK-LE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.4h, v1.4h
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4h, v0.4h
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4h, v2.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4h, v0.4h
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4h, v1.4h
-; CHECK-BE-IADISABLED-NEXT: adrp x8, .LCPI42_0
-; CHECK-BE-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI42_0
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: rev16 v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.4h, v1.4h
+; CHECK-BE-NEXT: rev64 v1.4h, v0.4h
+; CHECK-BE-NEXT: st2 { v1.4h, v2.4h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %v0, <4 x half> %v1)
store <8 x half> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -2597,37 +2481,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i64_intrinsic(<2 x i64> %v0, <2 x i64> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %v0, <2 x i64> %v1)
store <4 x i64> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -2636,41 +2502,21 @@ entry:
define void @test_stnp_interleaved_store2_v4i32_intrinsic(<4 x i32> %v0, <4 x i32> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4s, v2.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.4s, v1.4s
+; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.4s, v2.4s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %v0, <4 x i32> %v1)
store <8 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2679,41 +2525,21 @@ entry:
define void @test_stnp_interleaved_store2_v8i16_intrinsic(<8 x i16> %v0, <8 x i16> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.8h, v2.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.8h, v1.8h
+; CHECK-BE-NEXT: rev64 v0.8h, v0.8h
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.8h, v2.8h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %v0, <8 x i16> %v1)
store <16 x i16> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -2722,41 +2548,21 @@ entry:
define void @test_stnp_interleaved_store2_v16i8_intrinsic(<16 x i8> %v0, <16 x i8> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.16b, v1.16b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.16b, v1.16b
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.16b, v0.16b
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.16b, v2.16b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.16b, v1.16b }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
+; CHECK-BE-NEXT: rev64 v0.16b, v0.16b
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.16b, v2.16b }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %v0, <16 x i8> %v1)
store <32 x i8> %interleave, ptr %ptr, align 1, !nontemporal !0
@@ -2765,37 +2571,19 @@ entry:
define void @test_stnp_interleaved_store2_v2f64_intrinsic(<2 x double> %v0, <2 x double> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %v0, <2 x double> %v1)
store <4 x double> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -2804,41 +2592,21 @@ entry:
define void @test_stnp_interleaved_store2_v4f32_intrinsic(<4 x float> %v0, <4 x float> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4s, v2.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.4s, v1.4s
+; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.4s, v2.4s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %v0, <4 x float> %v1)
store <8 x float> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2847,41 +2615,21 @@ entry:
define void @test_stnp_interleaved_store2_v8f16_intrinsic(<8 x half> %v0, <8 x half> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.8h, v2.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.8h, v1.8h
+; CHECK-BE-NEXT: rev64 v0.8h, v0.8h
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.8h, v2.8h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %v0, <8 x half> %v1)
store <16 x half> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -3503,11 +3251,14 @@ entry:
define void @test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic(<3 x i32> %v0, <3 x i32> %v1, ptr %ptr) {
; CHECK-LE-LABEL: test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic:
; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: zip1 v2.4s, v0.4s, v1.4s
-; CHECK-LE-NEXT: zip2 v0.4s, v0.4s, v1.4s
-; CHECK-LE-NEXT: mov d3, v2.d[1]
-; CHECK-LE-NEXT: str d0, [x0, #16]
-; CHECK-LE-NEXT: stnp d2, d3, [x0]
+; CHECK-LE-NEXT: zip2 v2.4s, v0.4s, v1.4s
+; CHECK-LE-NEXT: zip1 v0.4s, v0.4s, v1.4s
+; CHECK-LE-NEXT: ext v1.16b, v0.16b, v2.16b, #12
+; CHECK-LE-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-LE-NEXT: mov d2, v0.d[1]
+; CHECK-LE-NEXT: ext v1.16b, v1.16b, v0.16b, #4
+; CHECK-LE-NEXT: stnp d0, d2, [x0]
+; CHECK-LE-NEXT: str d1, [x0, #16]
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic:
@@ -3518,6 +3269,9 @@ define void @test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic(<3
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: zip2 v2.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: zip1 v0.4s, v0.4s, v1.4s
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v2.16b, #12
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v0.16b, #4
+; CHECK-BE-NEXT: mov v0.s[3], v1.s[0]
; CHECK-BE-NEXT: rev64 v1.4s, v2.4s
; CHECK-BE-NEXT: st1 { v0.4s }, [x0]
; CHECK-BE-NEXT: str d1, [x0, #16]
@@ -3532,54 +3286,48 @@ entry:
define void @test_stnp_interleaved_store2_v2i24_non_pow2_elt_size_intrinsic(<2 x i24> %v0, <2 x i24> %v1, ptr %ptr) {
; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i24_non_pow2_elt_size_intrinsic:
; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-NEXT: mov v2.16b, v0.16b
-; CHECK-LE-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-NEXT: fmov w9, s0
+; CHECK-LE-NEXT: zip2 v2.2s, v0.2s, v1.2s
+; CHECK-LE-NEXT: zip1 v0.2s, v0.2s, v1.2s
+; CHECK-LE-NEXT: fmov w9, s2
+; CHECK-LE-NEXT: mov w8, v2.s[1]
+; CHECK-LE-NEXT: mov w10, v0.s[1]
+; CHECK-LE-NEXT: str h2, [x0, #6]
; CHECK-LE-NEXT: str h0, [x0]
-; CHECK-LE-NEXT: mov w8, v1.s[1]
-; CHECK-LE-NEXT: mov v2.d[1], v1.d[0]
; CHECK-LE-NEXT: lsr w9, w9, #16
-; CHECK-LE-NEXT: strb w9, [x0, #2]
-; CHECK-LE-NEXT: lsr w9, w8, #16
; CHECK-LE-NEXT: sturh w8, [x0, #9]
-; CHECK-LE-NEXT: rev64 v3.4s, v2.4s
-; CHECK-LE-NEXT: strb w9, [x0, #11]
-; CHECK-LE-NEXT: uzp1 v2.4s, v2.4s, v3.4s
-; CHECK-LE-NEXT: mov w10, v2.s[2]
-; CHECK-LE-NEXT: mov w11, v2.s[1]
-; CHECK-LE-NEXT: lsr w8, w10, #16
-; CHECK-LE-NEXT: lsr w9, w11, #16
-; CHECK-LE-NEXT: strh w10, [x0, #6]
-; CHECK-LE-NEXT: sturh w11, [x0, #3]
-; CHECK-LE-NEXT: strb w8, [x0, #8]
-; CHECK-LE-NEXT: strb w9, [x0, #5]
+; CHECK-LE-NEXT: lsr w8, w8, #16
+; CHECK-LE-NEXT: strb w9, [x0, #8]
+; CHECK-LE-NEXT: fmov w9, s0
+; CHECK-LE-NEXT: sturh w10, [x0, #3]
+; CHECK-LE-NEXT: lsr w10, w10, #16
+; CHECK-LE-NEXT: strb w8, [x0, #11]
+; CHECK-LE-NEXT: lsr w8, w9, #16
+; CHECK-LE-NEXT: strb w10, [x0, #5]
+; CHECK-LE-NEXT: strb w8, [x0, #2]
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i24_non_pow2_elt_size_intrinsic:
; CHECK-BE: // %bb.0: // %entry
-; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
; CHECK-BE-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-NEXT: mov v2.16b, v0.16b
-; CHECK-BE-NEXT: fmov w9, s0
-; CHECK-BE-NEXT: mov w8, v1.s[1]
+; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
+; CHECK-BE-NEXT: zip2 v2.2s, v0.2s, v1.2s
+; CHECK-BE-NEXT: zip1 v0.2s, v0.2s, v1.2s
+; CHECK-BE-NEXT: fmov w9, s2
+; CHECK-BE-NEXT: mov w8, v2.s[1]
+; CHECK-BE-NEXT: mov w10, v0.s[1]
+; CHECK-BE-NEXT: stur b2, [x0, #8]
; CHECK-BE-NEXT: stur b0, [x0, #2]
-; CHECK-BE-NEXT: mov v2.d[1], v1.d[0]
; CHECK-BE-NEXT: lsr w9, w9, #8
; CHECK-BE-NEXT: strb w8, [x0, #11]
-; CHECK-BE-NEXT: strh w9, [x0]
-; CHECK-BE-NEXT: lsr w9, w8, #8
-; CHECK-BE-NEXT: rev64 v3.4s, v2.4s
-; CHECK-BE-NEXT: sturh w9, [x0, #9]
-; CHECK-BE-NEXT: uzp1 v2.4s, v2.4s, v3.4s
-; CHECK-BE-NEXT: mov w10, v2.s[2]
-; CHECK-BE-NEXT: mov w11, v2.s[1]
-; CHECK-BE-NEXT: lsr w8, w10, #8
-; CHECK-BE-NEXT: lsr w9, w11, #8
-; CHECK-BE-NEXT: strb w10, [x0, #8]
-; CHECK-BE-NEXT: strb w11, [x0, #5]
-; CHECK-BE-NEXT: strh w8, [x0, #6]
-; CHECK-BE-NEXT: sturh w9, [x0, #3]
+; CHECK-BE-NEXT: lsr w8, w8, #8
+; CHECK-BE-NEXT: strh w9, [x0, #6]
+; CHECK-BE-NEXT: fmov w9, s0
+; CHECK-BE-NEXT: strb w10, [x0, #5]
+; CHECK-BE-NEXT: lsr w10, w10, #8
+; CHECK-BE-NEXT: sturh w8, [x0, #9]
+; CHECK-BE-NEXT: lsr w8, w9, #8
+; CHECK-BE-NEXT: sturh w10, [x0, #3]
+; CHECK-BE-NEXT: strh w8, [x0]
; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i24> @llvm.vector.interleave2.v4i24(<2 x i24> %v0, <2 x i24> %v1)
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
index 4300bcf317d12..1a51a03a4f5b3 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
@@ -50,25 +50,13 @@ exit:
define void @hang_when_merging_stores_after_legalisation_intrinsic(ptr %a, <2 x i32> %b) vscale_range(2,2) #0 {
-; CHECK-IAENABLED-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
-; CHECK-IAENABLED: // %bb.0:
-; CHECK-IAENABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-IAENABLED-NEXT: dup v0.4s, v0.s[0]
-; CHECK-IAENABLED-NEXT: mov v1.16b, v0.16b
-; CHECK-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
-; CHECK-IADISABLED: // %bb.0:
-; CHECK-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-IADISABLED-NEXT: adrp x8, .LCPI2_0
-; CHECK-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI2_0
-; CHECK-IADISABLED-NEXT: dup v0.4s, v0.s[0]
-; CHECK-IADISABLED-NEXT: ldr z1, [x8]
-; CHECK-IADISABLED-NEXT: mov z0.q, q0
-; CHECK-IADISABLED-NEXT: tbl z0.s, { z0.s }, z1.s
-; CHECK-IADISABLED-NEXT: str z0, [x0]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.4s, v0.s[0]
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; CHECK-NEXT: ret
%splat = shufflevector <2 x i32> %b, <2 x i32> poison, <4 x i32> zeroinitializer
%interleaved.vec = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %splat, <4 x i32> %splat)
store <8 x i32> %interleaved.vec, ptr %a, align 4
diff --git a/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll b/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll
index 30f944e0a050d..6d6473a6da5da 100644
--- a/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll
+++ b/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll
@@ -1654,20 +1654,15 @@ define void @deinterleave_nxptr_factor2(ptr %ptr) #2 {
define void @store_factor2_intrinsic(ptr %ptr, <16 x i16> %v0, <16 x i16> %v1) #0 {
; CHECK-LABEL: store_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.h, vl8
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI29_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI29_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h
-; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
-; CHECK-NEXT: tbl z1.h, { z1.h }, z4.h
-; CHECK-NEXT: tbl z0.h, { z0.h }, z4.h
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h
+; CHECK-NEXT: splice z4.h, p0, z4.h, z1.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: st2h { z4.h, z5.h }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <32 x i16> @llvm.vector.interleave2.v32i16(<16 x i16> %v0, <16 x i16> %v1)
store <32 x i16> %interleaved.vec, ptr %ptr, align 4
@@ -1722,20 +1717,15 @@ define void @store_factor4_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1, <4
define void @store_ptrvec_factor2_intrinsic(ptr %ptr, <4 x ptr> %v0, <4 x ptr> %v1) #0 {
; CHECK-LABEL: store_ptrvec_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI32_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI32_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.d, p0, z1.d, z3.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z2.d
-; CHECK-NEXT: tbl z1.d, { z1.d }, z4.d
-; CHECK-NEXT: tbl z0.d, { z0.d }, z4.d
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.d, p0, z5.d, z3.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z1.d
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: st2d { z4.d, z5.d }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <8 x ptr> @llvm.vector.interleave2.v8p0(<4 x ptr> %v0, <4 x ptr> %v1)
store <8 x ptr> %interleaved.vec, ptr %ptr, align 4
@@ -1791,28 +1781,25 @@ define void @store_factor2_wide_intrinsic(ptr %ptr, <8 x i64> %v0, <8 x i64> %v1
; CHECK-LABEL: store_factor2_wide_intrinsic:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
+; CHECK-NEXT: // kill: def $q6 killed $q6 def $z6
+; CHECK-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q7 killed $q7 def $z7
-; CHECK-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-NEXT: // kill: def $q5 killed $q5 def $z5
-; CHECK-NEXT: // kill: def $q4 killed $q4 def $z4
-; CHECK-NEXT: adrp x8, .LCPI35_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI35_0
-; CHECK-NEXT: splice z3.d, p0, z3.d, z7.d
-; CHECK-NEXT: splice z2.d, p0, z2.d, z6.d
-; CHECK-NEXT: splice z1.d, p0, z1.d, z5.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z4.d
-; CHECK-NEXT: ldr z7, [x8]
-; CHECK-NEXT: tbl z3.d, { z3.d }, z7.d
-; CHECK-NEXT: tbl z2.d, { z2.d }, z7.d
-; CHECK-NEXT: tbl z1.d, { z1.d }, z7.d
-; CHECK-NEXT: tbl z0.d, { z0.d }, z7.d
-; CHECK-NEXT: str z3, [x0, #3, mul vl]
+; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: splice z6.d, p0, z6.d, z7.d
+; CHECK-NEXT: splice z2.d, p0, z2.d, z3.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z5.d
+; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: zip2 z1.d, z2.d, z6.d
+; CHECK-NEXT: zip1 z2.d, z2.d, z6.d
+; CHECK-NEXT: zip2 z3.d, z0.d, z4.d
+; CHECK-NEXT: zip1 z0.d, z0.d, z4.d
+; CHECK-NEXT: str z1, [x0, #3, mul vl]
; CHECK-NEXT: str z2, [x0, #2, mul vl]
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
+; CHECK-NEXT: str z3, [x0, #1, mul vl]
; CHECK-NEXT: str z0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <16 x i64> @llvm.vector.interleave2.v16i64(<8 x i64> %v0, <8 x i64> %v1)
@@ -1823,22 +1810,15 @@ define void @store_factor2_wide_intrinsic(ptr %ptr, <8 x i64> %v0, <8 x i64> %v1
define void @store_min_not_max_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1) #1 {
; CHECK-LABEL: store_min_not_max_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI36_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI36_0
-; CHECK-NEXT: ptrue p1.d, vl4
-; CHECK-NEXT: splice z1.d, p0, z1.d, z3.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z2.d
-; CHECK-NEXT: ld1d { z2.d }, p1/z, [x8]
-; CHECK-NEXT: mov x8, #4 // =0x4
-; CHECK-NEXT: tbl z1.d, { z1.d }, z2.d
-; CHECK-NEXT: tbl z0.d, { z0.d }, z2.d
-; CHECK-NEXT: st1d { z1.d }, p1, [x0, x8, lsl #3]
-; CHECK-NEXT: st1d { z0.d }, p1, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.d, p0, z5.d, z3.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z1.d
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: st2d { z4.d, z5.d }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <8 x i64> @llvm.vector.interleave2.v8i64(<4 x i64> %v0, <4 x i64> %v1)
store <8 x i64> %interleaved.vec, ptr %ptr, align 4
@@ -1848,20 +1828,15 @@ define void @store_min_not_max_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1)
define void @store_min_ge_type_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1) #2 {
; CHECK-LABEL: store_min_ge_type_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: adrp x8, .LCPI37_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI37_0
-; CHECK-NEXT: splice z2.d, p0, z2.d, z3.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.d, p0, z5.d, z3.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z1.d
; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: ldr z1, [x8]
-; CHECK-NEXT: splice z0.d, p0, z0.d, z2.d
-; CHECK-NEXT: tbl z0.d, { z0.d }, z1.d
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: st2d { z4.d, z5.d }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <8 x i64> @llvm.vector.interleave2.v8i64(<4 x i64> %v0, <4 x i64> %v1)
store <8 x i64> %interleaved.vec, ptr %ptr, align 4
@@ -1916,20 +1891,15 @@ define void @store_float_factor3_intrinsic(ptr %ptr, <8 x float> %v0, <8 x float
define void @store_half_factor2_intrinsic(ptr %ptr, <16 x half> %v0, <16 x half> %v1) #0 {
; CHECK-LABEL: store_half_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.h, vl8
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI40_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI40_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h
-; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
-; CHECK-NEXT: tbl z1.h, { z1.h }, z4.h
-; CHECK-NEXT: tbl z0.h, { z0.h }, z4.h
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h
+; CHECK-NEXT: splice z4.h, p0, z4.h, z1.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: st2h { z4.h, z5.h }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <32 x half> @llvm.vector.interleave2.v32f16(<16 x half> %v0, <16 x half> %v1)
store <32 x half> %interleaved.vec, ptr %ptr, align 4
@@ -1939,12 +1909,12 @@ define void @store_half_factor2_intrinsic(ptr %ptr, <16 x half> %v0, <16 x half>
define void @store_bfloat_factor2_intrinsic(ptr %ptr, <16 x bfloat> %v0, <16 x bfloat> %v1) #0 {
; CHECK-LABEL: store_bfloat_factor2_intrinsic:
; CHECK: // %bb.0:
-; CHECK-NEXT: zip2 v4.8h, v1.8h, v3.8h
-; CHECK-NEXT: zip1 v1.8h, v1.8h, v3.8h
-; CHECK-NEXT: zip2 v3.8h, v0.8h, v2.8h
-; CHECK-NEXT: zip1 v0.8h, v0.8h, v2.8h
-; CHECK-NEXT: stp q1, q4, [x0, #32]
-; CHECK-NEXT: stp q0, q3, [x0]
+; CHECK-NEXT: mov v5.16b, v2.16b
+; CHECK-NEXT: // kill: def $q3 killed $q3 def $q2_q3
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: mov v2.16b, v1.16b
+; CHECK-NEXT: st2 { v4.8h, v5.8h }, [x0], #32
+; CHECK-NEXT: st2 { v2.8h, v3.8h }, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <32 x bfloat> @llvm.vector.interleave2.v32bf16(<16 x bfloat> %v0, <16 x bfloat> %v1)
store <32 x bfloat> %interleaved.vec, ptr %ptr, align 4
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll
index d87b6b0404874..4f4dac8fe9f65 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll
@@ -9,23 +9,15 @@ define void @store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1) {
; CHECK-COMPAT-LABEL: store_factor2_64bit:
; CHECK-COMPAT: // %bb.0:
; CHECK-COMPAT-NEXT: ptrue p0.s, vl2
-; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 def $z1
-; CHECK-COMPAT-NEXT: adrp x8, .LCPI0_0
-; CHECK-COMPAT-NEXT: splice z0.s, p0, z0.s, z1.s
-; CHECK-COMPAT-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
-; CHECK-COMPAT-NEXT: tbl z0.s, { z0.s }, z1.s
-; CHECK-COMPAT-NEXT: str q0, [x0]
+; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: store_factor2_64bit:
; CHECK-STREAMING: // %bb.0:
; CHECK-STREAMING-NEXT: ptrue p0.s, vl2
-; CHECK-STREAMING-NEXT: adrp x8, .LCPI0_0
-; CHECK-STREAMING-NEXT: splice z0.s, p0, { z0.s, z1.s }
-; CHECK-STREAMING-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
-; CHECK-STREAMING-NEXT: tbl z0.s, { z0.s }, z1.s
-; CHECK-STREAMING-NEXT: str q0, [x0]
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <4 x i32> @llvm.vector.interleave2.v4i32(
<2 x i32> %v0, <2 x i32> %v1)
@@ -36,30 +28,16 @@ define void @store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1) {
define void @store_factor2_128bit(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1) {
; CHECK-COMPAT-LABEL: store_factor2_128bit:
; CHECK-COMPAT: // %bb.0:
-; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 def $z0
-; CHECK-COMPAT-NEXT: mov z2.s, z1.s[3]
-; CHECK-COMPAT-NEXT: mov z3.s, z0.s[3]
-; CHECK-COMPAT-NEXT: mov z4.s, z1.s[2]
-; CHECK-COMPAT-NEXT: mov z5.s, z0.s[2]
-; CHECK-COMPAT-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-COMPAT-NEXT: zip1 z2.s, z3.s, z2.s
-; CHECK-COMPAT-NEXT: zip1 z3.s, z5.s, z4.s
-; CHECK-COMPAT-NEXT: zip1 z1.d, z3.d, z2.d
-; CHECK-COMPAT-NEXT: stp q0, q1, [x0]
+; CHECK-COMPAT-NEXT: ptrue p0.s, vl4
+; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: store_factor2_128bit:
; CHECK-STREAMING: // %bb.0:
-; CHECK-STREAMING-NEXT: mov z2.s, z1.s[3]
-; CHECK-STREAMING-NEXT: mov z3.s, z0.s[3]
-; CHECK-STREAMING-NEXT: mov z4.s, z1.s[2]
-; CHECK-STREAMING-NEXT: mov z5.s, z0.s[2]
-; CHECK-STREAMING-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-STREAMING-NEXT: zip1 z2.s, z3.s, z2.s
-; CHECK-STREAMING-NEXT: zip1 z3.s, z5.s, z4.s
-; CHECK-STREAMING-NEXT: zip1 z1.d, z3.d, z2.d
-; CHECK-STREAMING-NEXT: stp q0, q1, [x0]
+; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <8 x i32> @llvm.vector.interleave2.v8i32(
<4 x i32> %v0, <4 x i32> %v1)
@@ -157,40 +135,22 @@ define void @masked_store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1,
; CHECK-COMPAT-LABEL: masked_store_factor2_64bit:
; CHECK-COMPAT: // %bb.0:
; CHECK-COMPAT-NEXT: // kill: def $d2 killed $d2 def $z2
-; CHECK-COMPAT-NEXT: mov z3.s, z2.s[1]
; CHECK-COMPAT-NEXT: ptrue p0.s, vl2
-; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 def $z1
-; CHECK-COMPAT-NEXT: adrp x8, .LCPI6_0
-; CHECK-COMPAT-NEXT: splice z0.s, p0, z0.s, z1.s
-; CHECK-COMPAT-NEXT: ptrue p0.s, vl4
-; CHECK-COMPAT-NEXT: zip1 z2.h, z2.h, z3.h
-; CHECK-COMPAT-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-COMPAT-NEXT: uunpklo z2.s, z2.h
+; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1
; CHECK-COMPAT-NEXT: lsl z2.s, z2.s, #31
-; CHECK-COMPAT-NEXT: asr z1.s, z2.s, #31
-; CHECK-COMPAT-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
-; CHECK-COMPAT-NEXT: tbl z0.s, { z0.s }, z2.s
-; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z1.s, #0
-; CHECK-COMPAT-NEXT: st1w { z0.s }, p1, [x0]
+; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: asr z2.s, z2.s, #31
+; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: masked_store_factor2_64bit:
; CHECK-STREAMING: // %bb.0:
-; CHECK-STREAMING-NEXT: mov z3.s, z2.s[1]
-; CHECK-STREAMING-NEXT: ptrue p0.s, vl2
-; CHECK-STREAMING-NEXT: adrp x8, .LCPI6_0
-; CHECK-STREAMING-NEXT: splice z0.s, p0, { z0.s, z1.s }
-; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
-; CHECK-STREAMING-NEXT: zip1 z2.h, z2.h, z3.h
-; CHECK-STREAMING-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-STREAMING-NEXT: uunpklo z2.s, z2.h
; CHECK-STREAMING-NEXT: lsl z2.s, z2.s, #31
-; CHECK-STREAMING-NEXT: asr z1.s, z2.s, #31
-; CHECK-STREAMING-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
-; CHECK-STREAMING-NEXT: tbl z0.s, { z0.s }, z2.s
-; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z1.s, #0
-; CHECK-STREAMING-NEXT: st1w { z0.s }, p1, [x0]
+; CHECK-STREAMING-NEXT: ptrue p0.s, vl2
+; CHECK-STREAMING-NEXT: asr z2.s, z2.s, #31
+; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <4 x i32> @llvm.vector.interleave2.v4i32(
<2 x i32> %v0, <2 x i32> %v1)
@@ -204,61 +164,25 @@ define void @masked_store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1,
define void @masked_store_factor2_128bit(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i1> %mask) {
; CHECK-COMPAT-LABEL: masked_store_factor2_128bit:
; CHECK-COMPAT: // %bb.0:
-; CHECK-COMPAT-NEXT: adrp x8, .LCPI7_0
; CHECK-COMPAT-NEXT: // kill: def $d2 killed $d2 def $z2
-; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 def $z0
-; CHECK-COMPAT-NEXT: mov z4.s, z1.s[3]
-; CHECK-COMPAT-NEXT: mov z5.s, z0.s[3]
-; CHECK-COMPAT-NEXT: ldr q3, [x8, :lo12:.LCPI7_0]
-; CHECK-COMPAT-NEXT: mov z6.s, z1.s[2]
-; CHECK-COMPAT-NEXT: mov z7.s, z0.s[2]
; CHECK-COMPAT-NEXT: ptrue p0.s, vl4
-; CHECK-COMPAT-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-COMPAT-NEXT: mov x8, #4 // =0x4
-; CHECK-COMPAT-NEXT: tbl z3.h, { z2.h }, z3.h
-; CHECK-COMPAT-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-COMPAT-NEXT: zip1 z4.s, z5.s, z4.s
-; CHECK-COMPAT-NEXT: zip1 z5.s, z7.s, z6.s
+; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
; CHECK-COMPAT-NEXT: uunpklo z2.s, z2.h
-; CHECK-COMPAT-NEXT: uunpklo z3.s, z3.h
+; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
; CHECK-COMPAT-NEXT: lsl z2.s, z2.s, #31
-; CHECK-COMPAT-NEXT: lsl z3.s, z3.s, #31
; CHECK-COMPAT-NEXT: asr z2.s, z2.s, #31
-; CHECK-COMPAT-NEXT: asr z3.s, z3.s, #31
-; CHECK-COMPAT-NEXT: cmpne p2.s, p0/z, z2.s, #0
-; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z3.s, #0
-; CHECK-COMPAT-NEXT: zip1 z3.d, z5.d, z4.d
-; CHECK-COMPAT-NEXT: st1w { z3.s }, p1, [x0, x8, lsl #2]
-; CHECK-COMPAT-NEXT: st1w { z0.s }, p2, [x0]
+; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: masked_store_factor2_128bit:
; CHECK-STREAMING: // %bb.0:
-; CHECK-STREAMING-NEXT: adrp x8, .LCPI7_0
-; CHECK-STREAMING-NEXT: mov z4.s, z1.s[3]
-; CHECK-STREAMING-NEXT: mov z5.s, z0.s[3]
-; CHECK-STREAMING-NEXT: ldr q3, [x8, :lo12:.LCPI7_0]
-; CHECK-STREAMING-NEXT: mov z6.s, z1.s[2]
-; CHECK-STREAMING-NEXT: mov z7.s, z0.s[2]
-; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
-; CHECK-STREAMING-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-STREAMING-NEXT: mov x8, #4 // =0x4
-; CHECK-STREAMING-NEXT: tbl z3.h, { z2.h }, z3.h
-; CHECK-STREAMING-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-STREAMING-NEXT: zip1 z4.s, z5.s, z4.s
-; CHECK-STREAMING-NEXT: zip1 z5.s, z7.s, z6.s
; CHECK-STREAMING-NEXT: uunpklo z2.s, z2.h
-; CHECK-STREAMING-NEXT: uunpklo z3.s, z3.h
+; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
; CHECK-STREAMING-NEXT: lsl z2.s, z2.s, #31
-; CHECK-STREAMING-NEXT: lsl z3.s, z3.s, #31
; CHECK-STREAMING-NEXT: asr z2.s, z2.s, #31
-; CHECK-STREAMING-NEXT: asr z3.s, z3.s, #31
-; CHECK-STREAMING-NEXT: cmpne p2.s, p0/z, z2.s, #0
-; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z3.s, #0
-; CHECK-STREAMING-NEXT: zip1 z3.d, z5.d, z4.d
-; CHECK-STREAMING-NEXT: st1w { z3.s }, p1, [x0, x8, lsl #2]
-; CHECK-STREAMING-NEXT: st1w { z0.s }, p2, [x0]
+; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <8 x i32> @llvm.vector.interleave2.v8i32(
<4 x i32> %v0, <4 x i32> %v1)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
index 133bac768d59e..70f02aeb91c6f 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
@@ -266,11 +266,9 @@ define void @alloc_v4i8_intrinsic(ptr %st_ptr) nounwind {
; CHECK-NEXT: ptrue p0.h, vl4
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x20]
; CHECK-NEXT: ptrue p0.s, vl2
-; CHECK-NEXT: mov z1.h, z0.h[2]
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: fmov w9, s1
-; CHECK-NEXT: mov z0.s, w8
-; CHECK-NEXT: mov z1.s, w9
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8
; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
; CHECK-NEXT: st1b { z0.s }, p0, [x19]
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
index 986b776a9a586..3d7e5eec7be63 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
@@ -194,7 +194,9 @@ define void @hang_when_merging_stores_after_legalisation_intrinsic(ptr %a, <2 x
; CHECK-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.s, s0
-; CHECK-NEXT: stp q0, q0, [x0]
+; CHECK-NEXT: ptrue p0.s, vl4
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
@@ -219,15 +221,8 @@ define void @hang_when_merging_stores_after_legalisation_intrinsic(ptr %a, <2 x
define void @interleave_store_without_splat_intrinsic(ptr %a, <4 x i32> %v1, <4 x i32> %v2) {
; CHECK-LABEL: interleave_store_without_splat_intrinsic:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z2.s, z1.s[3]
-; CHECK-NEXT: mov z3.s, z0.s[3]
-; CHECK-NEXT: mov z4.s, z1.s[2]
-; CHECK-NEXT: mov z5.s, z0.s[2]
-; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-NEXT: zip1 z2.s, z3.s, z2.s
-; CHECK-NEXT: zip1 z3.s, z5.s, z4.s
-; CHECK-NEXT: zip1 z1.d, z3.d, z2.d
-; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ptrue p0.s, vl4
+; CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: interleave_store_without_splat_intrinsic:
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll b/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
index 98115a427b4ad..5b3463fc0d145 100644
--- a/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
@@ -898,14 +898,14 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; SVE-NEXT: .cfi_escape 0x0f, 0x09, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x30, 0x1e, 0x22 // sp + 16 + 48 * VG
; SVE-NEXT: .cfi_offset w29, -16
; SVE-NEXT: ptrue p0.d
-; SVE-NEXT: str z5, [sp, #5, mul vl]
-; SVE-NEXT: str z4, [sp, #4, mul vl]
-; SVE-NEXT: str z3, [sp, #3, mul vl]
-; SVE-NEXT: str z2, [sp, #2, mul vl]
-; SVE-NEXT: str z1, [sp, #1, mul vl]
-; SVE-NEXT: str z0, [sp]
-; SVE-NEXT: ld3d { z5.d - z7.d }, p0/z, [sp, #3, mul vl]
-; SVE-NEXT: ld3d { z24.d - z26.d }, p0/z, [sp]
+; SVE-NEXT: str z5, [sp, #2, mul vl]
+; SVE-NEXT: str z4, [sp, #1, mul vl]
+; SVE-NEXT: str z3, [sp]
+; SVE-NEXT: str z2, [sp, #5, mul vl]
+; SVE-NEXT: str z1, [sp, #4, mul vl]
+; SVE-NEXT: str z0, [sp, #3, mul vl]
+; SVE-NEXT: ld3d { z5.d - z7.d }, p0/z, [sp]
+; SVE-NEXT: ld3d { z24.d - z26.d }, p0/z, [sp, #3, mul vl]
; SVE-NEXT: uzp1 z0.d, z24.d, z5.d
; SVE-NEXT: uzp1 z1.d, z25.d, z6.d
; SVE-NEXT: uzp1 z2.d, z26.d, z7.d
@@ -923,14 +923,14 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; SME2-NEXT: .cfi_escape 0x0f, 0x09, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x30, 0x1e, 0x22 // sp + 16 + 48 * VG
; SME2-NEXT: .cfi_offset w29, -16
; SME2-NEXT: ptrue p0.d
-; SME2-NEXT: str z5, [sp, #5, mul vl]
-; SME2-NEXT: str z4, [sp, #4, mul vl]
-; SME2-NEXT: str z3, [sp, #3, mul vl]
-; SME2-NEXT: str z2, [sp, #2, mul vl]
-; SME2-NEXT: str z1, [sp, #1, mul vl]
-; SME2-NEXT: str z0, [sp]
-; SME2-NEXT: ld3d { z3.d - z5.d }, p0/z, [sp, #3, mul vl]
-; SME2-NEXT: ld3d { z24.d - z26.d }, p0/z, [sp]
+; SME2-NEXT: str z5, [sp, #2, mul vl]
+; SME2-NEXT: str z4, [sp, #1, mul vl]
+; SME2-NEXT: str z3, [sp]
+; SME2-NEXT: str z2, [sp, #5, mul vl]
+; SME2-NEXT: str z1, [sp, #4, mul vl]
+; SME2-NEXT: str z0, [sp, #3, mul vl]
+; SME2-NEXT: ld3d { z3.d - z5.d }, p0/z, [sp]
+; SME2-NEXT: ld3d { z24.d - z26.d }, p0/z, [sp, #3, mul vl]
; SME2-NEXT: uzp { z2.d, z3.d }, z24.d, z3.d
; SME2-NEXT: uzp { z6.d, z7.d }, z25.d, z4.d
; SME2-NEXT: uzp { z4.d, z5.d }, z26.d, z5.d
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-interleave-widen.ll b/llvm/test/CodeGen/AArch64/sve-vector-interleave-widen.ll
index d67488981bbcd..f0b3760dc30e1 100644
--- a/llvm/test/CodeGen/AArch64/sve-vector-interleave-widen.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vector-interleave-widen.ll
@@ -206,16 +206,16 @@ define void @interleave6_v3fp32(ptr %dst, <vscale x 3 x float> %a, <vscale x 3
; CHECK-NEXT: addvl x9, sp, #31
; CHECK-NEXT: rdvl x10, #4
; CHECK-NEXT: ptrue p1.d
-; CHECK-NEXT: st3w { z24.s - z26.s }, p0, [sp, #3, mul vl]
-; CHECK-NEXT: ldr z1, [sp, #5, mul vl]
-; CHECK-NEXT: ldr z2, [sp, #4, mul vl]
-; CHECK-NEXT: ldr z0, [sp, #3, mul vl]
-; CHECK-NEXT: st3w { z5.s - z7.s }, p0, [sp]
+; CHECK-NEXT: st3w { z24.s - z26.s }, p0, [sp]
+; CHECK-NEXT: ldr z1, [sp, #2, mul vl]
+; CHECK-NEXT: ldr z2, [sp, #1, mul vl]
+; CHECK-NEXT: ldr z0, [sp]
+; CHECK-NEXT: st3w { z5.s - z7.s }, p0, [sp, #3, mul vl]
; CHECK-NEXT: whilelo p0.s, xzr, x8
; CHECK-NEXT: cntw x8, all, mul #3
-; CHECK-NEXT: ldr z3, [sp, #2, mul vl]
-; CHECK-NEXT: ldr z4, [sp, #1, mul vl]
-; CHECK-NEXT: ldr z5, [sp]
+; CHECK-NEXT: ldr z3, [sp, #5, mul vl]
+; CHECK-NEXT: ldr z4, [sp, #4, mul vl]
+; CHECK-NEXT: ldr z5, [sp, #3, mul vl]
; CHECK-NEXT: add x9, x9, x8
; CHECK-NEXT: str z1, [sp, #36, mul vl]
; CHECK-NEXT: str z2, [sp, #35, mul vl]
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll b/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
index 32689d88c09ea..a5244f1879f57 100644
--- a/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
@@ -957,14 +957,14 @@ define <vscale x 12 x i64> @interleave6_nxv12i64(<vscale x 2 x i64> %vec0, <vsca
; SVE-NEXT: zip2 z1.d, z1.d, z4.d
; SVE-NEXT: zip2 z0.d, z0.d, z3.d
; SVE-NEXT: ptrue p0.d
-; SVE-NEXT: st3d { z24.d - z26.d }, p0, [sp]
-; SVE-NEXT: st3d { z0.d - z2.d }, p0, [sp, #3, mul vl]
-; SVE-NEXT: ldr z0, [sp]
-; SVE-NEXT: ldr z1, [sp, #1, mul vl]
-; SVE-NEXT: ldr z2, [sp, #2, mul vl]
-; SVE-NEXT: ldr z3, [sp, #3, mul vl]
-; SVE-NEXT: ldr z4, [sp, #4, mul vl]
-; SVE-NEXT: ldr z5, [sp, #5, mul vl]
+; SVE-NEXT: st3d { z24.d - z26.d }, p0, [sp, #3, mul vl]
+; SVE-NEXT: st3d { z0.d - z2.d }, p0, [sp]
+; SVE-NEXT: ldr z0, [sp, #3, mul vl]
+; SVE-NEXT: ldr z1, [sp, #4, mul vl]
+; SVE-NEXT: ldr z2, [sp, #5, mul vl]
+; SVE-NEXT: ldr z3, [sp]
+; SVE-NEXT: ldr z4, [sp, #1, mul vl]
+; SVE-NEXT: ldr z5, [sp, #2, mul vl]
; SVE-NEXT: addvl sp, sp, #6
; SVE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; SVE-NEXT: ret
@@ -983,14 +983,14 @@ define <vscale x 12 x i64> @interleave6_nxv12i64(<vscale x 2 x i64> %vec0, <vsca
; SME2-NEXT: mov z2.d, z25.d
; SME2-NEXT: mov z3.d, z7.d
; SME2-NEXT: ptrue p0.d
-; SME2-NEXT: st3d { z4.d - z6.d }, p0, [sp]
-; SME2-NEXT: ldr z0, [sp]
-; SME2-NEXT: st3d { z1.d - z3.d }, p0, [sp, #3, mul vl]
-; SME2-NEXT: ldr z1, [sp, #1, mul vl]
-; SME2-NEXT: ldr z2, [sp, #2, mul vl]
-; SME2-NEXT: ldr z3, [sp, #3, mul vl]
-; SME2-NEXT: ldr z4, [sp, #4, mul vl]
-; SME2-NEXT: ldr z5, [sp, #5, mul vl]
+; SME2-NEXT: st3d { z4.d - z6.d }, p0, [sp, #3, mul vl]
+; SME2-NEXT: ldr z0, [sp, #3, mul vl]
+; SME2-NEXT: st3d { z1.d - z3.d }, p0, [sp]
+; SME2-NEXT: ldr z1, [sp, #4, mul vl]
+; SME2-NEXT: ldr z2, [sp, #5, mul vl]
+; SME2-NEXT: ldr z3, [sp]
+; SME2-NEXT: ldr z4, [sp, #1, mul vl]
+; SME2-NEXT: ldr z5, [sp, #2, mul vl]
; SME2-NEXT: addvl sp, sp, #6
; SME2-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; SME2-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/tbl-loops.ll b/llvm/test/CodeGen/AArch64/tbl-loops.ll
index 4870243e0e4a4..731392f936eeb 100644
--- a/llvm/test/CodeGen/AArch64/tbl-loops.ll
+++ b/llvm/test/CodeGen/AArch64/tbl-loops.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
; RUN: llc --lower-interleaved-accesses=false -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
@@ -1064,159 +1064,82 @@ for.body: ; preds = %for.body.preheader5
define void @loop2_intrinsic(ptr noalias nocapture noundef writeonly %dst, ptr nocapture noundef readonly %data, i32 noundef %width) {
-; CHECK-IAENABLED-LABEL: loop2_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: subs w8, w2, #1
-; CHECK-IAENABLED-NEXT: b.lt .LBB4_6
-; CHECK-IAENABLED-NEXT: // %bb.1: // %for.body.preheader
-; CHECK-IAENABLED-NEXT: cmp w8, #2
-; CHECK-IAENABLED-NEXT: b.ls .LBB4_3
-; CHECK-IAENABLED-NEXT: // %bb.2: // %vector.memcheck
-; CHECK-IAENABLED-NEXT: ubfiz x9, x8, #1, #32
-; CHECK-IAENABLED-NEXT: add x9, x9, #2
-; CHECK-IAENABLED-NEXT: add x10, x0, x9
-; CHECK-IAENABLED-NEXT: add x9, x1, x9, lsl #2
-; CHECK-IAENABLED-NEXT: cmp x10, x1
-; CHECK-IAENABLED-NEXT: ccmp x9, x0, #0, hi
-; CHECK-IAENABLED-NEXT: b.ls .LBB4_7
-; CHECK-IAENABLED-NEXT: .LBB4_3:
-; CHECK-IAENABLED-NEXT: mov w10, wzr
-; CHECK-IAENABLED-NEXT: mov x8, x1
-; CHECK-IAENABLED-NEXT: mov x9, x0
-; CHECK-IAENABLED-NEXT: .LBB4_4: // %for.body.preheader1
-; CHECK-IAENABLED-NEXT: movi d0, #0000000000000000
-; CHECK-IAENABLED-NEXT: mov w11, #1132396544 // =0x437f0000
-; CHECK-IAENABLED-NEXT: sub w10, w2, w10
-; CHECK-IAENABLED-NEXT: fmov s1, w11
-; CHECK-IAENABLED-NEXT: .LBB4_5: // %for.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ldp s2, s3, [x8], #8
-; CHECK-IAENABLED-NEXT: fcmp s2, s1
-; CHECK-IAENABLED-NEXT: fcsel s4, s1, s2, gt
-; CHECK-IAENABLED-NEXT: fcmp s2, #0.0
-; CHECK-IAENABLED-NEXT: fcsel s2, s0, s4, mi
-; CHECK-IAENABLED-NEXT: fcmp s3, s1
-; CHECK-IAENABLED-NEXT: fcsel s4, s1, s3, gt
-; CHECK-IAENABLED-NEXT: fcmp s3, #0.0
-; CHECK-IAENABLED-NEXT: fcvtzs s2, s2
-; CHECK-IAENABLED-NEXT: fcsel s3, s0, s4, mi
-; CHECK-IAENABLED-NEXT: subs w10, w10, #1
-; CHECK-IAENABLED-NEXT: str b2, [x9]
-; CHECK-IAENABLED-NEXT: fcvtzs s3, s3
-; CHECK-IAENABLED-NEXT: stur b3, [x9, #1]
-; CHECK-IAENABLED-NEXT: add x9, x9, #2
-; CHECK-IAENABLED-NEXT: b.ne .LBB4_5
-; CHECK-IAENABLED-NEXT: .LBB4_6: // %for.cond.cleanup
-; CHECK-IAENABLED-NEXT: ret
-; CHECK-IAENABLED-NEXT: .LBB4_7: // %vector.ph
-; CHECK-IAENABLED-NEXT: add x11, x8, #1
-; CHECK-IAENABLED-NEXT: mov w8, #1132396544 // =0x437f0000
-; CHECK-IAENABLED-NEXT: and x10, x11, #0x1fffffffc
-; CHECK-IAENABLED-NEXT: dup v0.4s, w8
-; CHECK-IAENABLED-NEXT: and x12, x11, #0x1fffffffc
-; CHECK-IAENABLED-NEXT: add x8, x1, x10, lsl #3
-; CHECK-IAENABLED-NEXT: add x9, x0, x10, lsl #1
-; CHECK-IAENABLED-NEXT: .LBB4_8: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x1], #32
-; CHECK-IAENABLED-NEXT: subs x12, x12, #4
-; CHECK-IAENABLED-NEXT: fcmgt v3.4s, v1.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fcmgt v4.4s, v2.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fcmlt v5.4s, v1.4s, #0.0
-; CHECK-IAENABLED-NEXT: bsl v3.16b, v0.16b, v1.16b
-; CHECK-IAENABLED-NEXT: bsl v4.16b, v0.16b, v2.16b
-; CHECK-IAENABLED-NEXT: fcmlt v1.4s, v2.4s, #0.0
-; CHECK-IAENABLED-NEXT: bic v2.16b, v3.16b, v5.16b
-; CHECK-IAENABLED-NEXT: bic v1.16b, v4.16b, v1.16b
-; CHECK-IAENABLED-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: xtn v2.4h, v2.4s
-; CHECK-IAENABLED-NEXT: xtn v1.4h, v1.4s
-; CHECK-IAENABLED-NEXT: trn1 v1.8b, v2.8b, v1.8b
-; CHECK-IAENABLED-NEXT: str d1, [x0], #8
-; CHECK-IAENABLED-NEXT: b.ne .LBB4_8
-; CHECK-IAENABLED-NEXT: // %bb.9: // %middle.block
-; CHECK-IAENABLED-NEXT: cmp x11, x10
-; CHECK-IAENABLED-NEXT: b.ne .LBB4_4
-; CHECK-IAENABLED-NEXT: b .LBB4_6
-;
-; CHECK-IADISABLED-LABEL: loop2_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: subs w8, w2, #1
-; CHECK-IADISABLED-NEXT: b.lt .LBB4_6
-; CHECK-IADISABLED-NEXT: // %bb.1: // %for.body.preheader
-; CHECK-IADISABLED-NEXT: cmp w8, #2
-; CHECK-IADISABLED-NEXT: b.ls .LBB4_3
-; CHECK-IADISABLED-NEXT: // %bb.2: // %vector.memcheck
-; CHECK-IADISABLED-NEXT: ubfiz x9, x8, #1, #32
-; CHECK-IADISABLED-NEXT: add x9, x9, #2
-; CHECK-IADISABLED-NEXT: add x10, x0, x9
-; CHECK-IADISABLED-NEXT: add x9, x1, x9, lsl #2
-; CHECK-IADISABLED-NEXT: cmp x10, x1
-; CHECK-IADISABLED-NEXT: ccmp x9, x0, #0, hi
-; CHECK-IADISABLED-NEXT: b.ls .LBB4_7
-; CHECK-IADISABLED-NEXT: .LBB4_3:
-; CHECK-IADISABLED-NEXT: mov w10, wzr
-; CHECK-IADISABLED-NEXT: mov x8, x1
-; CHECK-IADISABLED-NEXT: mov x9, x0
-; CHECK-IADISABLED-NEXT: .LBB4_4: // %for.body.preheader1
-; CHECK-IADISABLED-NEXT: movi d0, #0000000000000000
-; CHECK-IADISABLED-NEXT: mov w11, #1132396544 // =0x437f0000
-; CHECK-IADISABLED-NEXT: sub w10, w2, w10
-; CHECK-IADISABLED-NEXT: fmov s1, w11
-; CHECK-IADISABLED-NEXT: .LBB4_5: // %for.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp s2, s3, [x8], #8
-; CHECK-IADISABLED-NEXT: fcmp s2, s1
-; CHECK-IADISABLED-NEXT: fcsel s4, s1, s2, gt
-; CHECK-IADISABLED-NEXT: fcmp s2, #0.0
-; CHECK-IADISABLED-NEXT: fcsel s2, s0, s4, mi
-; CHECK-IADISABLED-NEXT: fcmp s3, s1
-; CHECK-IADISABLED-NEXT: fcsel s4, s1, s3, gt
-; CHECK-IADISABLED-NEXT: fcmp s3, #0.0
-; CHECK-IADISABLED-NEXT: fcvtzs s2, s2
-; CHECK-IADISABLED-NEXT: fcsel s3, s0, s4, mi
-; CHECK-IADISABLED-NEXT: subs w10, w10, #1
-; CHECK-IADISABLED-NEXT: str b2, [x9]
-; CHECK-IADISABLED-NEXT: fcvtzs s3, s3
-; CHECK-IADISABLED-NEXT: stur b3, [x9, #1]
-; CHECK-IADISABLED-NEXT: add x9, x9, #2
-; CHECK-IADISABLED-NEXT: b.ne .LBB4_5
-; CHECK-IADISABLED-NEXT: .LBB4_6: // %for.cond.cleanup
-; CHECK-IADISABLED-NEXT: ret
-; CHECK-IADISABLED-NEXT: .LBB4_7: // %vector.ph
-; CHECK-IADISABLED-NEXT: add x11, x8, #1
-; CHECK-IADISABLED-NEXT: mov w8, #1132396544 // =0x437f0000
-; CHECK-IADISABLED-NEXT: and x10, x11, #0x1fffffffc
-; CHECK-IADISABLED-NEXT: dup v0.4s, w8
-; CHECK-IADISABLED-NEXT: and x12, x11, #0x1fffffffc
-; CHECK-IADISABLED-NEXT: add x8, x1, x10, lsl #3
-; CHECK-IADISABLED-NEXT: add x9, x0, x10, lsl #1
-; CHECK-IADISABLED-NEXT: .LBB4_8: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q2, q1, [x1], #32
-; CHECK-IADISABLED-NEXT: subs x12, x12, #4
-; CHECK-IADISABLED-NEXT: uzp1 v3.4s, v2.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v2.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fcmgt v2.4s, v3.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fcmgt v4.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: bsl v2.16b, v0.16b, v3.16b
-; CHECK-IADISABLED-NEXT: fcmlt v3.4s, v3.4s, #0.0
-; CHECK-IADISABLED-NEXT: bsl v4.16b, v0.16b, v1.16b
-; CHECK-IADISABLED-NEXT: fcmlt v1.4s, v1.4s, #0.0
-; CHECK-IADISABLED-NEXT: bic v2.16b, v2.16b, v3.16b
-; CHECK-IADISABLED-NEXT: bic v1.16b, v4.16b, v1.16b
-; CHECK-IADISABLED-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: xtn v2.4h, v2.4s
-; CHECK-IADISABLED-NEXT: xtn v1.4h, v1.4s
-; CHECK-IADISABLED-NEXT: trn1 v1.8b, v2.8b, v1.8b
-; CHECK-IADISABLED-NEXT: str d1, [x0], #8
-; CHECK-IADISABLED-NEXT: b.ne .LBB4_8
-; CHECK-IADISABLED-NEXT: // %bb.9: // %middle.block
-; CHECK-IADISABLED-NEXT: cmp x11, x10
-; CHECK-IADISABLED-NEXT: b.ne .LBB4_4
-; CHECK-IADISABLED-NEXT: b .LBB4_6
+; CHECK-LABEL: loop2_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: subs w8, w2, #1
+; CHECK-NEXT: b.lt .LBB4_6
+; CHECK-NEXT: // %bb.1: // %for.body.preheader
+; CHECK-NEXT: cmp w8, #2
+; CHECK-NEXT: b.ls .LBB4_3
+; CHECK-NEXT: // %bb.2: // %vector.memcheck
+; CHECK-NEXT: ubfiz x9, x8, #1, #32
+; CHECK-NEXT: add x9, x9, #2
+; CHECK-NEXT: add x10, x0, x9
+; CHECK-NEXT: add x9, x1, x9, lsl #2
+; CHECK-NEXT: cmp x10, x1
+; CHECK-NEXT: ccmp x9, x0, #0, hi
+; CHECK-NEXT: b.ls .LBB4_7
+; CHECK-NEXT: .LBB4_3:
+; CHECK-NEXT: mov w10, wzr
+; CHECK-NEXT: mov x8, x1
+; CHECK-NEXT: mov x9, x0
+; CHECK-NEXT: .LBB4_4: // %for.body.preheader1
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: mov w11, #1132396544 // =0x437f0000
+; CHECK-NEXT: sub w10, w2, w10
+; CHECK-NEXT: fmov s1, w11
+; CHECK-NEXT: .LBB4_5: // %for.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldp s2, s3, [x8], #8
+; CHECK-NEXT: fcmp s2, s1
+; CHECK-NEXT: fcsel s4, s1, s2, gt
+; CHECK-NEXT: fcmp s2, #0.0
+; CHECK-NEXT: fcsel s2, s0, s4, mi
+; CHECK-NEXT: fcmp s3, s1
+; CHECK-NEXT: fcsel s4, s1, s3, gt
+; CHECK-NEXT: fcmp s3, #0.0
+; CHECK-NEXT: fcvtzs s2, s2
+; CHECK-NEXT: fcsel s3, s0, s4, mi
+; CHECK-NEXT: subs w10, w10, #1
+; CHECK-NEXT: str b2, [x9]
+; CHECK-NEXT: fcvtzs s3, s3
+; CHECK-NEXT: stur b3, [x9, #1]
+; CHECK-NEXT: add x9, x9, #2
+; CHECK-NEXT: b.ne .LBB4_5
+; CHECK-NEXT: .LBB4_6: // %for.cond.cleanup
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB4_7: // %vector.ph
+; CHECK-NEXT: add x11, x8, #1
+; CHECK-NEXT: mov w8, #1132396544 // =0x437f0000
+; CHECK-NEXT: and x10, x11, #0x1fffffffc
+; CHECK-NEXT: dup v0.4s, w8
+; CHECK-NEXT: and x12, x11, #0x1fffffffc
+; CHECK-NEXT: add x8, x1, x10, lsl #3
+; CHECK-NEXT: add x9, x0, x10, lsl #1
+; CHECK-NEXT: .LBB4_8: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x1], #32
+; CHECK-NEXT: subs x12, x12, #4
+; CHECK-NEXT: fcmgt v3.4s, v1.4s, v0.4s
+; CHECK-NEXT: fcmgt v4.4s, v2.4s, v0.4s
+; CHECK-NEXT: fcmlt v5.4s, v1.4s, #0.0
+; CHECK-NEXT: bsl v3.16b, v0.16b, v1.16b
+; CHECK-NEXT: bsl v4.16b, v0.16b, v2.16b
+; CHECK-NEXT: fcmlt v1.4s, v2.4s, #0.0
+; CHECK-NEXT: bic v2.16b, v3.16b, v5.16b
+; CHECK-NEXT: bic v1.16b, v4.16b, v1.16b
+; CHECK-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-NEXT: xtn v2.4h, v2.4s
+; CHECK-NEXT: xtn v1.4h, v1.4s
+; CHECK-NEXT: zip1 v1.8h, v2.8h, v1.8h
+; CHECK-NEXT: xtn v1.8b, v1.8h
+; CHECK-NEXT: str d1, [x0], #8
+; CHECK-NEXT: b.ne .LBB4_8
+; CHECK-NEXT: // %bb.9: // %middle.block
+; CHECK-NEXT: cmp x11, x10
+; CHECK-NEXT: b.ne .LBB4_4
+; CHECK-NEXT: b .LBB4_6
entry:
%cmp19 = icmp sgt i32 %width, 0
br i1 %cmp19, label %for.body.preheader, label %for.cond.cleanup
diff --git a/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll b/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
index b63448c643074..e0ad97de0b25b 100644
--- a/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
+++ b/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
@@ -3,31 +3,17 @@
; RUN: llc -mtriple=aarch64-linux-gnu -lower-interleaved-accesses=false < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
define void @aarch64_vector_deinterleave_idx_ld2(ptr %ptr, i64 %idx) {
-; CHECK-IAENABLED-LABEL: aarch64_vector_deinterleave_idx_ld2:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: lsl x8, x1, #2
-; CHECK-IAENABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; CHECK-IAENABLED-NEXT: add x8, x8, #16
-; CHECK-IAENABLED-NEXT: add x10, x0, x9
-; CHECK-IAENABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; CHECK-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x10]
-; CHECK-IAENABLED-NEXT: str q0, [x0, x9]
-; CHECK-IAENABLED-NEXT: str q1, [x0, x8]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: aarch64_vector_deinterleave_idx_ld2:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: lsl x8, x1, #2
-; CHECK-IADISABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; CHECK-IADISABLED-NEXT: add x8, x8, #16
-; CHECK-IADISABLED-NEXT: add x9, x0, x9
-; CHECK-IADISABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x9]
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: str q2, [x9]
-; CHECK-IADISABLED-NEXT: str q0, [x0, x8]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: aarch64_vector_deinterleave_idx_ld2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: lsl x8, x1, #2
+; CHECK-NEXT: and x9, x8, #0xfffffffffffffff0
+; CHECK-NEXT: add x8, x8, #16
+; CHECK-NEXT: add x10, x0, x9
+; CHECK-NEXT: and x8, x8, #0xfffffffffffffff0
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x10]
+; CHECK-NEXT: str q0, [x0, x9]
+; CHECK-NEXT: str q1, [x0, x8]
+; CHECK-NEXT: ret
entry:
%idx1 = lshr i64 %idx, 2
%a1 = add i64 %idx, 4
@@ -131,3 +117,6 @@ entry:
store <4 x float> %m12_15, ptr %gep4, align 16
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-IADISABLED: {{.*}}
+; CHECK-IAENABLED: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/vector-interleave-store.ll b/llvm/test/CodeGen/AArch64/vector-interleave-store.ll
index e720275dc242e..71b034c902e22 100644
--- a/llvm/test/CodeGen/AArch64/vector-interleave-store.ll
+++ b/llvm/test/CodeGen/AArch64/vector-interleave-store.ll
@@ -3,23 +3,14 @@
; RUN: llc -mtriple=aarch64-linux-gnu -lower-interleaved-accesses=false < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
define void @aarch64_vector_interleave_idx_st2(ptr %ptr, i64 %idx, <4 x float> %v0, <4 x float> %v1) {
-; CHECK-IAENABLED-LABEL: aarch64_vector_interleave_idx_st2:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: lsr x8, x1, #2
-; CHECK-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-IAENABLED-NEXT: add x8, x0, x8, lsl #4
-; CHECK-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x8]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: aarch64_vector_interleave_idx_st2:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: lsr x8, x1, #2
-; CHECK-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: add x8, x0, x8, lsl #4
-; CHECK-IADISABLED-NEXT: stp q0, q2, [x8]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: aarch64_vector_interleave_idx_st2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: lsr x8, x1, #2
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: add x8, x0, x8, lsl #4
+; CHECK-NEXT: st2 { v0.4s, v1.4s }, [x8]
+; CHECK-NEXT: ret
entry:
%idx1 = lshr i64 %idx, 2
%gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx1
@@ -69,25 +60,13 @@ entry:
}
define void @wide_vector_interleave_st2(ptr %input0, ptr %input1, ptr %output) {
-; CHECK-IAENABLED-LABEL: wide_vector_interleave_st2:
-; CHECK-IAENABLED: // %bb.0:
-; CHECK-IAENABLED-NEXT: ldp q0, q2, [x0]
-; CHECK-IAENABLED-NEXT: ldp q1, q3, [x1]
-; CHECK-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x2], #32
-; CHECK-IAENABLED-NEXT: st2 { v2.4s, v3.4s }, [x2]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: wide_vector_interleave_st2:
-; CHECK-IADISABLED: // %bb.0:
-; CHECK-IADISABLED-NEXT: ldp q3, q0, [x1]
-; CHECK-IADISABLED-NEXT: ldp q2, q1, [x0]
-; CHECK-IADISABLED-NEXT: zip1 v4.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: zip2 v0.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v2.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v2.4s, v2.4s, v3.4s
-; CHECK-IADISABLED-NEXT: stp q4, q0, [x2, #32]
-; CHECK-IADISABLED-NEXT: stp q1, q2, [x2]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: wide_vector_interleave_st2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q2, [x0]
+; CHECK-NEXT: ldp q1, q3, [x1]
+; CHECK-NEXT: st2 { v0.4s, v1.4s }, [x2], #32
+; CHECK-NEXT: st2 { v2.4s, v3.4s }, [x2]
+; CHECK-NEXT: ret
%v0 = load <8 x i32>, ptr %input0, align 4
%v1 = load <8 x i32>, ptr %input1, align 4
%interleaved.vec = tail call <16 x i32> @llvm.vector.interleave2.v16i32(<8 x i32> %v0, <8 x i32> %v1)
@@ -361,29 +340,27 @@ define void @wide_vector_interleave_st3_i16_dreg(ptr %output, ptr %input0, ptr %
; CHECK-NEXT: .cfi_def_cfa_offset 192
; CHECK-NEXT: ldr q0, [x1]
; CHECK-NEXT: ldr d3, [x1, #16]
-; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x8, sp, #48
; CHECK-NEXT: ldr q1, [x2]
; CHECK-NEXT: ldr d4, [x2, #16]
; CHECK-NEXT: ldr q2, [x3]
; CHECK-NEXT: ldr d5, [x3, #16]
; CHECK-NEXT: st3 { v0.8h, v1.8h, v2.8h }, [x8]
-; CHECK-NEXT: add x8, sp, #48
+; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: st3 { v3.8h, v4.8h, v5.8h }, [x8]
-; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ldr q0, [sp, #80]
+; CHECK-NEXT: ldr x8, [sp, #16]
+; CHECK-NEXT: ldr q4, [sp]
; CHECK-NEXT: dup v1.2d, v0.d[1]
; CHECK-NEXT: str d1, [sp, #144]
-; CHECK-NEXT: ldr q1, [sp, #64]
+; CHECK-NEXT: ldp q2, q1, [sp, #48]
; CHECK-NEXT: ldr q3, [sp, #144]
-; CHECK-NEXT: str d1, [sp, #112]
-; CHECK-NEXT: ldp q2, q1, [sp]
+; CHECK-NEXT: str x8, [x0, #64]
; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #8
; CHECK-NEXT: mov v1.d[1], v0.d[0]
; CHECK-NEXT: ext v0.16b, v0.16b, v3.16b, #8
-; CHECK-NEXT: ldr q3, [sp, #48]
; CHECK-NEXT: stp q2, q1, [x0]
-; CHECK-NEXT: stp q0, q3, [x0, #32]
-; CHECK-NEXT: ldr q0, [sp, #112]
-; CHECK-NEXT: str d0, [x0, #64]
+; CHECK-NEXT: stp q0, q4, [x0, #32]
; CHECK-NEXT: add sp, sp, #192
; CHECK-NEXT: ret
%v0 = load <12 x i16>, ptr %input0, align 2
@@ -452,29 +429,27 @@ define void @wide_vector_interleave_st3_i8_dreg(ptr %output, ptr %input0, ptr %i
; CHECK-NEXT: .cfi_def_cfa_offset 192
; CHECK-NEXT: ldr q0, [x1]
; CHECK-NEXT: ldr d3, [x1, #16]
-; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x8, sp, #48
; CHECK-NEXT: ldr q1, [x2]
; CHECK-NEXT: ldr d4, [x2, #16]
; CHECK-NEXT: ldr q2, [x3]
; CHECK-NEXT: ldr d5, [x3, #16]
; CHECK-NEXT: st3 { v0.16b, v1.16b, v2.16b }, [x8]
-; CHECK-NEXT: add x8, sp, #48
+; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: st3 { v3.16b, v4.16b, v5.16b }, [x8]
-; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ldr q0, [sp, #80]
+; CHECK-NEXT: ldr x8, [sp, #16]
+; CHECK-NEXT: ldr q4, [sp]
; CHECK-NEXT: dup v1.2d, v0.d[1]
; CHECK-NEXT: str d1, [sp, #144]
-; CHECK-NEXT: ldr q1, [sp, #64]
+; CHECK-NEXT: ldp q2, q1, [sp, #48]
; CHECK-NEXT: ldr q3, [sp, #144]
-; CHECK-NEXT: str d1, [sp, #112]
-; CHECK-NEXT: ldp q2, q1, [sp]
+; CHECK-NEXT: str x8, [x0, #64]
; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #8
; CHECK-NEXT: mov v1.d[1], v0.d[0]
; CHECK-NEXT: ext v0.16b, v0.16b, v3.16b, #8
-; CHECK-NEXT: ldr q3, [sp, #48]
; CHECK-NEXT: stp q2, q1, [x0]
-; CHECK-NEXT: stp q0, q3, [x0, #32]
-; CHECK-NEXT: ldr q0, [sp, #112]
-; CHECK-NEXT: str d0, [x0, #64]
+; CHECK-NEXT: stp q0, q4, [x0, #32]
; CHECK-NEXT: add sp, sp, #192
; CHECK-NEXT: ret
%v0 = load <24 x i8>, ptr %input0, align 1
@@ -535,3 +510,6 @@ define void @wide_vector_interleave_st4_i8_dreg(ptr %output, ptr %input0, ptr %i
store <96 x i8> %interleave, ptr %output, align 1
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-IADISABLED: {{.*}}
+; CHECK-IAENABLED: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
index 963c28aeba32b..fac725dd74999 100644
--- a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
@@ -1075,12 +1075,10 @@ define void @vld2_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: .LBB17_1: // %vector.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldp q1, q0, [x0], #32
-; CHECK-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: fmul v1.4s, v2.4s, v2.4s
-; CHECK-NEXT: fmla v1.4s, v0.4s, v0.4s
-; CHECK-NEXT: str q1, [x1, x8]
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x0], #32
+; CHECK-NEXT: fmul v2.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v2.4s, v1.4s, v1.4s
+; CHECK-NEXT: str q2, [x1, x8]
; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: cmp x8, #1, lsl #12 // =4096
; CHECK-NEXT: b.ne .LBB17_1
@@ -1161,47 +1159,25 @@ while.end: ; preds = %vector.body
define void @vld4_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32 %numSamples) {
-; CHECK-IAENABLED-LABEL: vld4_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin19:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov x8, xzr
-; CHECK-IAENABLED-NEXT: .LBB19_1: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IAENABLED-NEXT: add x9, x1, x8
-; CHECK-IAENABLED-NEXT: add x8, x8, #32
-; CHECK-IAENABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IAENABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x9]
-; CHECK-IAENABLED-NEXT: b.ne .LBB19_1
-; CHECK-IAENABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld4_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin19:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov x8, xzr
-; CHECK-IADISABLED-NEXT: .LBB19_1: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IADISABLED-NEXT: add x9, x1, x8
-; CHECK-IADISABLED-NEXT: add x8, x8, #32
-; CHECK-IADISABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IADISABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v0.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: stp q1, q0, [x9]
-; CHECK-IADISABLED-NEXT: b.ne .LBB19_1
-; CHECK-IADISABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld4_intrinsic:
+; CHECK: .Lfunc_begin19:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: .LBB19_1: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
+; CHECK-NEXT: add x9, x1, x8
+; CHECK-NEXT: add x8, x8, #32
+; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
+; CHECK-NEXT: fmul v4.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v4.4s, v1.4s, v1.4s
+; CHECK-NEXT: fmul v5.4s, v2.4s, v2.4s
+; CHECK-NEXT: fmla v5.4s, v3.4s, v3.4s
+; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x9]
+; CHECK-NEXT: b.ne .LBB19_1
+; CHECK-NEXT: // %bb.2: // %while.end
+; CHECK-NEXT: ret
entry:
br label %vector.body
@@ -1248,16 +1224,12 @@ define void @twosrc_intrinsic(ptr nocapture readonly %pSrc, ptr nocapture readon
; CHECK-NEXT: add x9, x0, x8
; CHECK-NEXT: add x10, x1, x8
; CHECK-NEXT: add x8, x8, #32
-; CHECK-NEXT: ldp q1, q0, [x9]
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x9]
; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-NEXT: ldp q3, q2, [x10]
-; CHECK-NEXT: uzp1 v4.4s, v1.4s, v0.4s
-; CHECK-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: uzp1 v5.4s, v3.4s, v2.4s
-; CHECK-NEXT: uzp2 v1.4s, v3.4s, v2.4s
-; CHECK-NEXT: fmul v2.4s, v5.4s, v4.4s
-; CHECK-NEXT: fmla v2.4s, v0.4s, v1.4s
-; CHECK-NEXT: str q2, [x2], #16
+; CHECK-NEXT: ld2 { v2.4s, v3.4s }, [x10]
+; CHECK-NEXT: fmul v4.4s, v2.4s, v0.4s
+; CHECK-NEXT: fmla v4.4s, v1.4s, v3.4s
+; CHECK-NEXT: str q4, [x2], #16
; CHECK-NEXT: b.ne .LBB20_1
; CHECK-NEXT: // %bb.2: // %while.end
; CHECK-NEXT: ret
@@ -1295,41 +1267,22 @@ while.end: ; preds = %vector.body
define void @vld2_multiuse_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32 %numSamples) {
-; CHECK-IAENABLED-LABEL: vld2_multiuse_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin21:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov x8, xzr
-; CHECK-IAENABLED-NEXT: .LBB21_1: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0], #32
-; CHECK-IAENABLED-NEXT: fmul v2.4s, v0.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fmla v2.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: str q2, [x1, x8]
-; CHECK-IAENABLED-NEXT: add x8, x8, #16
-; CHECK-IAENABLED-NEXT: cmp x8, #1, lsl #12 // =4096
-; CHECK-IAENABLED-NEXT: b.ne .LBB21_1
-; CHECK-IAENABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld2_multiuse_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin21:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov x8, xzr
-; CHECK-IADISABLED-NEXT: .LBB21_1: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0], #32
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v1.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v1.4s, v0.4s, v0.4s
-; CHECK-IADISABLED-NEXT: str q1, [x1, x8]
-; CHECK-IADISABLED-NEXT: add x8, x8, #16
-; CHECK-IADISABLED-NEXT: cmp x8, #1, lsl #12 // =4096
-; CHECK-IADISABLED-NEXT: b.ne .LBB21_1
-; CHECK-IADISABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld2_multiuse_intrinsic:
+; CHECK: .Lfunc_begin21:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: .LBB21_1: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x0], #32
+; CHECK-NEXT: fmul v2.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v2.4s, v1.4s, v1.4s
+; CHECK-NEXT: str q2, [x1, x8]
+; CHECK-NEXT: add x8, x8, #16
+; CHECK-NEXT: cmp x8, #1, lsl #12 // =4096
+; CHECK-NEXT: b.ne .LBB21_1
+; CHECK-NEXT: // %bb.2: // %while.end
+; CHECK-NEXT: ret
entry:
br label %vector.body
@@ -1402,47 +1355,25 @@ while.end: ; preds = %vector.body
define void @vld4_multiuse_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32 %numSamples) {
-; CHECK-IAENABLED-LABEL: vld4_multiuse_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin23:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov x8, xzr
-; CHECK-IAENABLED-NEXT: .LBB23_1: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IAENABLED-NEXT: add x9, x1, x8
-; CHECK-IAENABLED-NEXT: add x8, x8, #32
-; CHECK-IAENABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IAENABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x9]
-; CHECK-IAENABLED-NEXT: b.ne .LBB23_1
-; CHECK-IAENABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld4_multiuse_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin23:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov x8, xzr
-; CHECK-IADISABLED-NEXT: .LBB23_1: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IADISABLED-NEXT: add x9, x1, x8
-; CHECK-IADISABLED-NEXT: add x8, x8, #32
-; CHECK-IADISABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IADISABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v0.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: stp q1, q0, [x9]
-; CHECK-IADISABLED-NEXT: b.ne .LBB23_1
-; CHECK-IADISABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld4_multiuse_intrinsic:
+; CHECK: .Lfunc_begin23:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: .LBB23_1: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
+; CHECK-NEXT: add x9, x1, x8
+; CHECK-NEXT: add x8, x8, #32
+; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
+; CHECK-NEXT: fmul v4.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v4.4s, v1.4s, v1.4s
+; CHECK-NEXT: fmul v5.4s, v2.4s, v2.4s
+; CHECK-NEXT: fmla v5.4s, v3.4s, v3.4s
+; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x9]
+; CHECK-NEXT: b.ne .LBB23_1
+; CHECK-NEXT: // %bb.2: // %while.end
+; CHECK-NEXT: ret
entry:
br label %vector.body
@@ -1534,18 +1465,18 @@ define void @transpose_s16_8x8_simpler2_intrinsic(ptr nocapture noundef %a) {
; CHECK-NEXT: .cfi_startproc
; CHECK-NEXT: // %bb.0: // %entry
; CHECK-NEXT: ldp q0, q1, [x0]
-; CHECK-NEXT: ldp q2, q3, [x0, #64]
-; CHECK-NEXT: ldp q4, q5, [x0, #96]
+; CHECK-NEXT: ldp q2, q3, [x0, #32]
+; CHECK-NEXT: ldp q4, q5, [x0, #64]
+; CHECK-NEXT: ldp q6, q7, [x0, #96]
; CHECK-NEXT: trn1 v0.8h, v0.8h, v1.8h
; CHECK-NEXT: zip1 v1.8h, v2.8h, v3.8h
-; CHECK-NEXT: trn1 v2.8h, v4.8h, v5.8h
-; CHECK-NEXT: ldp q3, q4, [x0, #32]
-; CHECK-NEXT: zip1 v3.8h, v3.8h, v4.8h
-; CHECK-NEXT: dup v1.4s, v1.s[0]
-; CHECK-NEXT: uzp1 v2.4s, v0.4s, v2.4s
-; CHECK-NEXT: zip1 v1.4s, v1.4s, v3.4s
-; CHECK-NEXT: zip2 v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: str q1, [x0]
+; CHECK-NEXT: zip1 v2.8h, v4.8h, v5.8h
+; CHECK-NEXT: trn1 v3.8h, v6.8h, v7.8h
+; CHECK-NEXT: trn1 v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: uzp1 v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: zip1 v2.4s, v0.4s, v1.4s
+; CHECK-NEXT: zip2 v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: str q2, [x0]
; CHECK-NEXT: str q0, [x0, #64]
; CHECK-NEXT: ret
entry:
@@ -1684,26 +1615,14 @@ define void @transpose_s16_8x8_intrinsic(ptr nocapture noundef %0, ptr nocapture
}
define void @store_factor2_intrinsic(ptr %ptr, <4 x i32> %a0, <4 x i32> %a1) {
-; CHECK-IAENABLED-LABEL: store_factor2_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin27:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0:
-; CHECK-IAENABLED-NEXT: trn1 v2.4s, v0.4s, v1.4s
-; CHECK-IAENABLED-NEXT: trn1 v3.4s, v1.4s, v0.4s
-; CHECK-IAENABLED-NEXT: st2 { v2.4s, v3.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: store_factor2_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin27:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0:
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp1 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: ext v0.16b, v2.16b, v0.16b, #8
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v2.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp1 v0.4s, v2.4s, v0.4s
-; CHECK-IADISABLED-NEXT: stp q0, q1, [x0]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: store_factor2_intrinsic:
+; CHECK: .Lfunc_begin27:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: trn1 v2.4s, v0.4s, v1.4s
+; CHECK-NEXT: trn1 v3.4s, v1.4s, v0.4s
+; CHECK-NEXT: st2 { v2.4s, v3.4s }, [x0]
+; CHECK-NEXT: ret
%v0 = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%v1 = shufflevector <4 x i32> %a1, <4 x i32> %a0, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%interleaved.vec = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %v0, <4 x i32> %v1)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
index a5971fb1f0310..34f57538deb41 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
@@ -9,21 +9,39 @@
define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr %p) {
; CHECK-LABEL: vector_interleave_store_v32i1_v16i1:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: lui a1, 11
+; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
+; CHECK-NEXT: addi a1, a1, -1366
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a1
+; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 8
+; CHECK-NEXT: vslidedown.vi v11, v9, 8
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v10
+; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v9, v11
+; CHECK-NEXT: vsll.vi v11, v12, 8
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v10, a1, v8
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
+; CHECK-NEXT: vmsne.vi v9, v10, 0
+; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vslideup.vi v0, v8, 2
+; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 16
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vwaddu.vv v12, v8, v10
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vwmaccu.vx v12, a2, v10
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vmsne.vi v8, v12, 0
-; CHECK-NEXT: vsm.v v8, (a0)
+; CHECK-NEXT: vsm.v v9, (a0)
; CHECK-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
store <32 x i1> %res, ptr %p
@@ -34,10 +52,25 @@ define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr
define void @vector_interleave_store_v16i16_v8i16_align1(<8 x i16> %a, <8 x i16> %b, ptr %p) {
; CHECK-LABEL: vector_interleave_store_v16i16_v8i16_align1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: li a1, 170
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a1
+; CHECK-NEXT: vslidedown.vi v10, v8, 4
+; CHECK-NEXT: vslidedown.vi v11, v9, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v10
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsll.vi v8, v13, 16
; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a1, v9
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v8, 8
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vse8.v v10, (a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index bce071e988f0e..0ac5860e3299b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -226,97 +226,145 @@ define {<3 x i32>, <3 x i32>, <3 x i32>} @vector_deinterleave3_v3i32_v9i32(<9 x
define {<15 x i32>, <15 x i32>, <15 x i32>} @vector_deinterleave3_v15i32_v45i32(<45 x i32> %v) nounwind {
; RV32-LABEL: vector_deinterleave3_v15i32_v45i32:
; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -640
-; RV32-NEXT: sw ra, 636(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw s0, 632(sp) # 4-byte Folded Spill
-; RV32-NEXT: addi s0, sp, 640
+; RV32-NEXT: addi sp, sp, -656
+; RV32-NEXT: sw ra, 652(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s0, 648(sp) # 4-byte Folded Spill
+; RV32-NEXT: addi s0, sp, 656
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: andi sp, sp, -128
-; RV32-NEXT: addi a1, sp, 252
-; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vse32.v v23, (a1)
-; RV32-NEXT: addi a1, sp, 248
-; RV32-NEXT: vse32.v v22, (a1)
-; RV32-NEXT: addi a1, sp, 244
-; RV32-NEXT: vse32.v v21, (a1)
-; RV32-NEXT: addi a1, sp, 240
-; RV32-NEXT: vse32.v v20, (a1)
-; RV32-NEXT: addi a1, sp, 236
-; RV32-NEXT: vse32.v v19, (a1)
-; RV32-NEXT: addi a1, sp, 232
-; RV32-NEXT: vse32.v v18, (a1)
-; RV32-NEXT: addi a1, sp, 228
-; RV32-NEXT: vse32.v v17, (a1)
-; RV32-NEXT: addi a1, sp, 224
-; RV32-NEXT: vse32.v v16, (a1)
-; RV32-NEXT: addi a1, sp, 220
-; RV32-NEXT: vse32.v v15, (a1)
-; RV32-NEXT: addi a1, sp, 216
-; RV32-NEXT: vse32.v v14, (a1)
-; RV32-NEXT: addi a1, sp, 212
-; RV32-NEXT: vse32.v v13, (a1)
-; RV32-NEXT: addi a1, sp, 208
-; RV32-NEXT: vse32.v v12, (a1)
-; RV32-NEXT: addi a1, sp, 204
-; RV32-NEXT: vse32.v v11, (a1)
-; RV32-NEXT: addi a1, sp, 200
-; RV32-NEXT: vse32.v v10, (a1)
-; RV32-NEXT: addi a1, sp, 196
-; RV32-NEXT: vse32.v v9, (a1)
-; RV32-NEXT: addi a1, sp, 192
-; RV32-NEXT: vse32.v v8, (a1)
-; RV32-NEXT: addi a2, a0, 64
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vle32.v v8, (a2)
+; RV32-NEXT: vmv1r.v v2, v23
+; RV32-NEXT: vmv1r.v v0, v21
+; RV32-NEXT: vmv1r.v v24, v19
+; RV32-NEXT: addi a1, sp, 640
+; RV32-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: vmv1r.v v24, v17
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 640
+; RV32-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 640
+; RV32-NEXT: vs2r.v v16, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: vmv1r.v v16, v15
+; RV32-NEXT: vmv1r.v v24, v13
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 6
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 640
+; RV32-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: vmv1r.v v24, v11
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 640
+; RV32-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: vmv1r.v v24, v9
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 10
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 640
+; RV32-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: addi a1, a0, 64
+; RV32-NEXT: vle32.v v24, (a1)
; RV32-NEXT: addi a2, sp, 384
-; RV32-NEXT: vse32.v v8, (a2)
-; RV32-NEXT: addi a3, a0, 96
+; RV32-NEXT: vse32.v v24, (a2)
+; RV32-NEXT: addi a1, a0, 96
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vle32.v v8, (a3)
-; RV32-NEXT: addi a3, sp, 416
-; RV32-NEXT: vse32.v v8, (a3)
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: addi a3, sp, 64
-; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vse32.v v8, (a3)
+; RV32-NEXT: vle32.v v9, (a1)
+; RV32-NEXT: addi a1, sp, 416
+; RV32-NEXT: vse32.v v9, (a1)
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vle32.v v12, (a1)
+; RV32-NEXT: vle32.v v24, (a0)
; RV32-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; RV32-NEXT: vslidedown.vi v16, v12, 8
-; RV32-NEXT: mv a1, sp
-; RV32-NEXT: vslidedown.vi v8, v8, 8
+; RV32-NEXT: vslidedown.vi v28, v24, 8
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vse32.v v12, (a1)
-; RV32-NEXT: addi a3, sp, 32
-; RV32-NEXT: vse32.v v16, (a3)
-; RV32-NEXT: addi a3, sp, 96
-; RV32-NEXT: vse32.v v8, (a3)
+; RV32-NEXT: vse32.v v28, (a1)
; RV32-NEXT: lw a0, 112(a0)
; RV32-NEXT: sw a0, 432(sp)
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vle32.v v8, (a2)
+; RV32-NEXT: vle32.v v28, (a2)
; RV32-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; RV32-NEXT: vslidedown.vi v12, v8, 8
+; RV32-NEXT: vslidedown.vi v4, v28, 8
+; RV32-NEXT: vsetivli zero, 8, e32, m2, tu, ma
+; RV32-NEXT: vslideup.vi v22, v2, 1
+; RV32-NEXT: vslideup.vi v0, v22, 1
+; RV32-NEXT: vslideup.vi v20, v0, 1
+; RV32-NEXT: addi a0, sp, 640
+; RV32-NEXT: vl2r.v v22, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v22, v20, 1
+; RV32-NEXT: vslideup.vi v18, v22, 1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 640
+; RV32-NEXT: vl2r.v v20, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v20, v18, 1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 640
+; RV32-NEXT: vl2r.v v18, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v18, v20, 1
+; RV32-NEXT: vslideup.vi v14, v16, 1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 6
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 640
+; RV32-NEXT: vl2r.v v16, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v16, v14, 1
+; RV32-NEXT: vslideup.vi v12, v16, 1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 640
+; RV32-NEXT: vl2r.v v14, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v14, v12, 1
+; RV32-NEXT: addi a0, sp, 96
+; RV32-NEXT: vse32.v v28, (a0)
+; RV32-NEXT: vslideup.vi v10, v14, 1
; RV32-NEXT: addi a0, sp, 128
-; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vse32.v v8, (a0)
+; RV32-NEXT: vse32.v v4, (a0)
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 10
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 640
+; RV32-NEXT: vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v12, v10, 1
+; RV32-NEXT: addi a0, sp, 224
+; RV32-NEXT: vse32.v v24, (a0)
+; RV32-NEXT: addi a0, sp, 192
+; RV32-NEXT: vslideup.vi v8, v12, 1
+; RV32-NEXT: vse32.v v18, (a0)
; RV32-NEXT: addi a0, sp, 160
-; RV32-NEXT: vse32.v v12, (a0)
-; RV32-NEXT: vlseg3e32.v v20, (a3)
-; RV32-NEXT: vlseg3e32.v v12, (a1)
+; RV32-NEXT: vse32.v v8, (a0)
+; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vlseg3e32.v v20, (a1)
+; RV32-NEXT: vlseg3e32.v v12, (a0)
; RV32-NEXT: vmv4r.v v28, v20
; RV32-NEXT: vmv2r.v v30, v8
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vslideup.vi v8, v28, 8
-; RV32-NEXT: vmv2r.v v12, v14
; RV32-NEXT: vmv2r.v v20, v22
-; RV32-NEXT: vslideup.vi v12, v20, 8
+; RV32-NEXT: vmv2r.v v12, v14
; RV32-NEXT: vslideup.vi v16, v24, 8
-; RV32-NEXT: addi sp, s0, -640
-; RV32-NEXT: lw ra, 636(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw s0, 632(sp) # 4-byte Folded Reload
-; RV32-NEXT: addi sp, sp, 640
+; RV32-NEXT: vslideup.vi v12, v20, 8
+; RV32-NEXT: addi sp, s0, -656
+; RV32-NEXT: lw ra, 652(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw s0, 648(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 656
; RV32-NEXT: ret
;
; RV64-LABEL: vector_deinterleave3_v15i32_v45i32:
@@ -325,92 +373,142 @@ define {<15 x i32>, <15 x i32>, <15 x i32>} @vector_deinterleave3_v15i32_v45i32(
; RV64-NEXT: sd ra, 632(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s0, 624(sp) # 8-byte Folded Spill
; RV64-NEXT: addi s0, sp, 640
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: andi sp, sp, -128
+; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64-NEXT: vmv1r.v v2, v23
+; RV64-NEXT: vmv1r.v v0, v21
+; RV64-NEXT: vmv1r.v v24, v19
+; RV64-NEXT: addi a1, sp, 624
+; RV64-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vmv1r.v v24, v17
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vs2r.v v16, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vmv1r.v v16, v15
+; RV64-NEXT: vmv1r.v v24, v13
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 6
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vmv1r.v v24, v11
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vmv1r.v v24, v9
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 10
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: addi a1, a0, 64
+; RV64-NEXT: vle32.v v24, (a1)
; RV64-NEXT: addi a1, a0, 112
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-NEXT: vle32.v v24, (a1)
-; RV64-NEXT: addi a1, sp, 252
-; RV64-NEXT: vse32.v v23, (a1)
-; RV64-NEXT: addi a1, sp, 248
-; RV64-NEXT: vse32.v v22, (a1)
-; RV64-NEXT: addi a1, sp, 244
-; RV64-NEXT: vse32.v v21, (a1)
-; RV64-NEXT: addi a1, sp, 240
-; RV64-NEXT: vse32.v v20, (a1)
-; RV64-NEXT: addi a1, sp, 236
-; RV64-NEXT: vse32.v v19, (a1)
-; RV64-NEXT: addi a1, sp, 232
-; RV64-NEXT: vse32.v v18, (a1)
-; RV64-NEXT: addi a1, sp, 228
-; RV64-NEXT: vse32.v v17, (a1)
-; RV64-NEXT: addi a1, sp, 224
-; RV64-NEXT: vse32.v v16, (a1)
-; RV64-NEXT: addi a1, sp, 220
-; RV64-NEXT: vse32.v v15, (a1)
-; RV64-NEXT: addi a1, sp, 216
-; RV64-NEXT: vse32.v v14, (a1)
-; RV64-NEXT: addi a1, sp, 212
-; RV64-NEXT: vse32.v v13, (a1)
-; RV64-NEXT: addi a1, sp, 208
-; RV64-NEXT: vse32.v v12, (a1)
-; RV64-NEXT: addi a1, sp, 204
-; RV64-NEXT: vse32.v v11, (a1)
-; RV64-NEXT: addi a1, sp, 200
-; RV64-NEXT: vse32.v v10, (a1)
-; RV64-NEXT: addi a1, sp, 196
-; RV64-NEXT: vse32.v v9, (a1)
-; RV64-NEXT: addi a1, sp, 192
-; RV64-NEXT: vse32.v v8, (a1)
-; RV64-NEXT: addi a2, a0, 64
+; RV64-NEXT: vle32.v v9, (a1)
+; RV64-NEXT: addi a1, sp, 384
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT: vle32.v v8, (a2)
-; RV64-NEXT: addi a2, sp, 384
-; RV64-NEXT: vse32.v v8, (a2)
-; RV64-NEXT: addi a3, a0, 96
+; RV64-NEXT: vse32.v v24, (a1)
+; RV64-NEXT: addi a2, a0, 96
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV64-NEXT: vle32.v v8, (a3)
-; RV64-NEXT: addi a3, sp, 416
-; RV64-NEXT: vse32.v v8, (a3)
-; RV64-NEXT: addi a3, sp, 432
+; RV64-NEXT: vle32.v v11, (a2)
+; RV64-NEXT: addi a2, sp, 416
+; RV64-NEXT: vse32.v v11, (a2)
+; RV64-NEXT: addi a2, sp, 432
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-NEXT: vse32.v v24, (a3)
+; RV64-NEXT: vse32.v v9, (a2)
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV64-NEXT: vle32.v v8, (a0)
+; RV64-NEXT: vle32.v v24, (a0)
+; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; RV64-NEXT: vslidedown.vi v28, v24, 8
; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT: vse32.v v8, (a0)
+; RV64-NEXT: vse32.v v28, (a0)
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV64-NEXT: vle32.v v12, (a1)
+; RV64-NEXT: vle32.v v28, (a1)
; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; RV64-NEXT: vslidedown.vi v16, v12, 8
-; RV64-NEXT: mv a0, sp
-; RV64-NEXT: vslidedown.vi v8, v8, 8
-; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT: vse32.v v12, (a0)
-; RV64-NEXT: addi a1, sp, 32
-; RV64-NEXT: vse32.v v16, (a1)
+; RV64-NEXT: vslidedown.vi v4, v28, 8
+; RV64-NEXT: vsetivli zero, 8, e32, m2, tu, ma
+; RV64-NEXT: vslideup.vi v22, v2, 1
+; RV64-NEXT: vslideup.vi v0, v22, 1
+; RV64-NEXT: vslideup.vi v20, v0, 1
+; RV64-NEXT: addi a1, sp, 624
+; RV64-NEXT: vl2r.v v22, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v22, v20, 1
+; RV64-NEXT: vslideup.vi v18, v22, 1
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vl2r.v v20, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v20, v18, 1
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vl2r.v v18, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v18, v20, 1
+; RV64-NEXT: vslideup.vi v14, v16, 1
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 6
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vl2r.v v16, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v16, v14, 1
+; RV64-NEXT: vslideup.vi v12, v16, 1
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vl2r.v v14, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v14, v12, 1
; RV64-NEXT: addi a1, sp, 96
+; RV64-NEXT: vse32.v v28, (a1)
+; RV64-NEXT: vslideup.vi v10, v14, 1
+; RV64-NEXT: addi a1, sp, 128
+; RV64-NEXT: vse32.v v4, (a1)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 10
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vl2r.v v12, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v12, v10, 1
+; RV64-NEXT: addi a1, sp, 224
+; RV64-NEXT: vse32.v v24, (a1)
+; RV64-NEXT: addi a1, sp, 192
+; RV64-NEXT: vslideup.vi v8, v12, 1
+; RV64-NEXT: vse32.v v18, (a1)
+; RV64-NEXT: addi a1, sp, 160
; RV64-NEXT: vse32.v v8, (a1)
-; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV64-NEXT: vle32.v v8, (a2)
-; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; RV64-NEXT: vslidedown.vi v12, v8, 8
-; RV64-NEXT: addi a2, sp, 128
-; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT: vse32.v v8, (a2)
-; RV64-NEXT: addi a2, sp, 160
-; RV64-NEXT: vse32.v v12, (a2)
-; RV64-NEXT: vlseg3e32.v v20, (a1)
-; RV64-NEXT: vlseg3e32.v v12, (a0)
+; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-NEXT: vlseg3e32.v v20, (a0)
+; RV64-NEXT: vlseg3e32.v v12, (a1)
; RV64-NEXT: vmv4r.v v28, v20
; RV64-NEXT: vmv2r.v v30, v8
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-NEXT: vslideup.vi v8, v28, 8
-; RV64-NEXT: vmv2r.v v12, v14
; RV64-NEXT: vmv2r.v v20, v22
-; RV64-NEXT: vslideup.vi v12, v20, 8
+; RV64-NEXT: vmv2r.v v12, v14
; RV64-NEXT: vslideup.vi v16, v24, 8
+; RV64-NEXT: vslideup.vi v12, v20, 8
; RV64-NEXT: addi sp, s0, -640
; RV64-NEXT: ld ra, 632(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 624(sp) # 8-byte Folded Reload
@@ -423,92 +521,142 @@ define {<15 x i32>, <15 x i32>, <15 x i32>} @vector_deinterleave3_v15i32_v45i32(
; ZVZIP-NEXT: sd ra, 632(sp) # 8-byte Folded Spill
; ZVZIP-NEXT: sd s0, 624(sp) # 8-byte Folded Spill
; ZVZIP-NEXT: addi s0, sp, 640
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: sub sp, sp, a1
; ZVZIP-NEXT: andi sp, sp, -128
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vmv1r.v v2, v23
+; ZVZIP-NEXT: vmv1r.v v0, v21
+; ZVZIP-NEXT: vmv1r.v v24, v19
+; ZVZIP-NEXT: addi a1, sp, 624
+; ZVZIP-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: vmv1r.v v24, v17
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vs2r.v v16, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: vmv1r.v v16, v15
+; ZVZIP-NEXT: vmv1r.v v24, v13
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 6
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: vmv1r.v v24, v11
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: vmv1r.v v24, v9
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 10
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: addi a1, a0, 64
+; ZVZIP-NEXT: vle32.v v24, (a1)
; ZVZIP-NEXT: addi a1, a0, 112
; ZVZIP-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVZIP-NEXT: vle32.v v24, (a1)
-; ZVZIP-NEXT: addi a1, sp, 252
-; ZVZIP-NEXT: vse32.v v23, (a1)
-; ZVZIP-NEXT: addi a1, sp, 248
-; ZVZIP-NEXT: vse32.v v22, (a1)
-; ZVZIP-NEXT: addi a1, sp, 244
-; ZVZIP-NEXT: vse32.v v21, (a1)
-; ZVZIP-NEXT: addi a1, sp, 240
-; ZVZIP-NEXT: vse32.v v20, (a1)
-; ZVZIP-NEXT: addi a1, sp, 236
-; ZVZIP-NEXT: vse32.v v19, (a1)
-; ZVZIP-NEXT: addi a1, sp, 232
-; ZVZIP-NEXT: vse32.v v18, (a1)
-; ZVZIP-NEXT: addi a1, sp, 228
-; ZVZIP-NEXT: vse32.v v17, (a1)
-; ZVZIP-NEXT: addi a1, sp, 224
-; ZVZIP-NEXT: vse32.v v16, (a1)
-; ZVZIP-NEXT: addi a1, sp, 220
-; ZVZIP-NEXT: vse32.v v15, (a1)
-; ZVZIP-NEXT: addi a1, sp, 216
-; ZVZIP-NEXT: vse32.v v14, (a1)
-; ZVZIP-NEXT: addi a1, sp, 212
-; ZVZIP-NEXT: vse32.v v13, (a1)
-; ZVZIP-NEXT: addi a1, sp, 208
-; ZVZIP-NEXT: vse32.v v12, (a1)
-; ZVZIP-NEXT: addi a1, sp, 204
-; ZVZIP-NEXT: vse32.v v11, (a1)
-; ZVZIP-NEXT: addi a1, sp, 200
-; ZVZIP-NEXT: vse32.v v10, (a1)
-; ZVZIP-NEXT: addi a1, sp, 196
-; ZVZIP-NEXT: vse32.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 192
-; ZVZIP-NEXT: vse32.v v8, (a1)
-; ZVZIP-NEXT: addi a2, a0, 64
+; ZVZIP-NEXT: vle32.v v9, (a1)
+; ZVZIP-NEXT: addi a1, sp, 384
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vle32.v v8, (a2)
-; ZVZIP-NEXT: addi a2, sp, 384
-; ZVZIP-NEXT: vse32.v v8, (a2)
-; ZVZIP-NEXT: addi a3, a0, 96
+; ZVZIP-NEXT: vse32.v v24, (a1)
+; ZVZIP-NEXT: addi a2, a0, 96
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vle32.v v8, (a3)
-; ZVZIP-NEXT: addi a3, sp, 416
-; ZVZIP-NEXT: vse32.v v8, (a3)
-; ZVZIP-NEXT: addi a3, sp, 432
+; ZVZIP-NEXT: vle32.v v11, (a2)
+; ZVZIP-NEXT: addi a2, sp, 416
+; ZVZIP-NEXT: vse32.v v11, (a2)
+; ZVZIP-NEXT: addi a2, sp, 432
; ZVZIP-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVZIP-NEXT: vse32.v v24, (a3)
+; ZVZIP-NEXT: vse32.v v9, (a2)
; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vle32.v v24, (a0)
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v28, v24, 8
; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vse32.v v8, (a0)
+; ZVZIP-NEXT: vse32.v v28, (a0)
; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZVZIP-NEXT: vle32.v v12, (a1)
+; ZVZIP-NEXT: vle32.v v28, (a1)
; ZVZIP-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v16, v12, 8
-; ZVZIP-NEXT: mv a0, sp
-; ZVZIP-NEXT: vslidedown.vi v8, v8, 8
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vse32.v v12, (a0)
-; ZVZIP-NEXT: addi a1, sp, 32
-; ZVZIP-NEXT: vse32.v v16, (a1)
+; ZVZIP-NEXT: vslidedown.vi v4, v28, 8
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v22, v2, 1
+; ZVZIP-NEXT: vslideup.vi v0, v22, 1
+; ZVZIP-NEXT: vslideup.vi v20, v0, 1
+; ZVZIP-NEXT: addi a1, sp, 624
+; ZVZIP-NEXT: vl2r.v v22, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v22, v20, 1
+; ZVZIP-NEXT: vslideup.vi v18, v22, 1
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vl2r.v v20, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v20, v18, 1
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vl2r.v v18, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v18, v20, 1
+; ZVZIP-NEXT: vslideup.vi v14, v16, 1
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 6
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vl2r.v v16, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v16, v14, 1
+; ZVZIP-NEXT: vslideup.vi v12, v16, 1
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vl2r.v v14, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v14, v12, 1
; ZVZIP-NEXT: addi a1, sp, 96
+; ZVZIP-NEXT: vse32.v v28, (a1)
+; ZVZIP-NEXT: vslideup.vi v10, v14, 1
+; ZVZIP-NEXT: addi a1, sp, 128
+; ZVZIP-NEXT: vse32.v v4, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 10
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vl2r.v v12, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v12, v10, 1
+; ZVZIP-NEXT: addi a1, sp, 224
+; ZVZIP-NEXT: vse32.v v24, (a1)
+; ZVZIP-NEXT: addi a1, sp, 192
+; ZVZIP-NEXT: vslideup.vi v8, v12, 1
+; ZVZIP-NEXT: vse32.v v18, (a1)
+; ZVZIP-NEXT: addi a1, sp, 160
; ZVZIP-NEXT: vse32.v v8, (a1)
-; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZVZIP-NEXT: vle32.v v8, (a2)
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v12, v8, 8
-; ZVZIP-NEXT: addi a2, sp, 128
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vse32.v v8, (a2)
-; ZVZIP-NEXT: addi a2, sp, 160
-; ZVZIP-NEXT: vse32.v v12, (a2)
-; ZVZIP-NEXT: vlseg3e32.v v20, (a1)
-; ZVZIP-NEXT: vlseg3e32.v v12, (a0)
+; ZVZIP-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vlseg3e32.v v20, (a0)
+; ZVZIP-NEXT: vlseg3e32.v v12, (a1)
; ZVZIP-NEXT: vmv4r.v v28, v20
; ZVZIP-NEXT: vmv2r.v v30, v8
; ZVZIP-NEXT: vmv4r.v v8, v12
; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v28, 8
-; ZVZIP-NEXT: vmv2r.v v12, v14
; ZVZIP-NEXT: vmv2r.v v20, v22
-; ZVZIP-NEXT: vslideup.vi v12, v20, 8
+; ZVZIP-NEXT: vmv2r.v v12, v14
; ZVZIP-NEXT: vslideup.vi v16, v24, 8
+; ZVZIP-NEXT: vslideup.vi v12, v20, 8
; ZVZIP-NEXT: addi sp, s0, -640
; ZVZIP-NEXT: ld ra, 632(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 624(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
index 23aaec74ce9de..16689a6f1f86f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
@@ -585,7 +585,10 @@ define {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i
; CHECK-NEXT: vmv.v.v v13, v12
; CHECK-NEXT: vmv.v.v v14, v12
; CHECK-NEXT: vmv.v.v v15, v12
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vsseg4e8.v v12, (a1)
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: add a3, a1, a2
@@ -593,29 +596,27 @@ define {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i
; CHECK-NEXT: vl1r.v v13, (a1)
; CHECK-NEXT: vmsne.vi v12, v12, 0
; CHECK-NEXT: vmsne.vi v0, v13, 0
-; CHECK-NEXT: add a3, a3, a2
-; CHECK-NEXT: vl1r.v v13, (a3)
+; CHECK-NEXT: slli a4, a2, 1
+; CHECK-NEXT: add a1, a1, a4
+; CHECK-NEXT: vl1r.v v13, (a1)
; CHECK-NEXT: srli a1, a2, 2
-; CHECK-NEXT: srli a4, a2, 3
+; CHECK-NEXT: srli a2, a2, 3
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vx v0, v12, a4
+; CHECK-NEXT: vslideup.vx v0, v12, a2
; CHECK-NEXT: vsetvli a5, zero, e8, m1, ta, ma
; CHECK-NEXT: vmsne.vi v12, v13, 0
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: vl1r.v v13, (a2)
-; CHECK-NEXT: add a4, a1, a4
-; CHECK-NEXT: vsetvli zero, a4, e8, mf2, tu, ma
+; CHECK-NEXT: add a3, a3, a4
+; CHECK-NEXT: vl1r.v v13, (a3)
+; CHECK-NEXT: add a2, a1, a2
+; CHECK-NEXT: vsetvli zero, a2, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v0, v12, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmsne.vi v12, v13, 0
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v12, a4
+; CHECK-NEXT: vslideup.vx v0, v12, a2
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0), v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg4e8.v v8, (a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index e58ee62d1a90f..5de1c9f539891 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -117,14 +117,14 @@ define {<vscale x 5 x i32>, <vscale x 5 x i32>, <vscale x 5 x i32>} @vector_dein
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv2r.v v8, v14
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: vlseg3e32.v v12, (a0)
; CHECK-NEXT: vlseg3e32.v v20, (a1)
@@ -696,14 +696,14 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vmv1r.v v10, v13
; CHECK-NEXT: vmv1r.v v11, v14
; CHECK-NEXT: vmv1r.v v8, v21
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vmv1r.v v9, v12
; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: vmv1r.v v12, v15
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg5e8.v v8, (a0)
@@ -738,7 +738,10 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -746,10 +749,7 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e8.v v12, (a0)
; CHECK-NEXT: vlseg5e8.v v18, (a1)
@@ -779,7 +779,10 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -787,10 +790,7 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e16.v v12, (a0)
; CHECK-NEXT: vlseg5e16.v v18, (a1)
@@ -820,7 +820,10 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -828,10 +831,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e32.v v12, (a0)
; CHECK-NEXT: vlseg5e32.v v18, (a1)
@@ -861,7 +861,10 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -869,10 +872,7 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e64.v v12, (a0)
; CHECK-NEXT: vlseg5e64.v v18, (a1)
@@ -921,7 +921,10 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: sub a0, a0, a1
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v24, v10, 1, v0
@@ -929,10 +932,7 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vslidedown.vx v0, v8, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v28, v10, 1, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg6e8.v v8, (a0)
@@ -969,16 +969,16 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e8.v v24, (a0)
; CHECK-NEXT: vlseg6e8.v v18, (a1)
@@ -1010,16 +1010,16 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e16.v v24, (a0)
; CHECK-NEXT: vlseg6e16.v v18, (a1)
@@ -1051,16 +1051,16 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e32.v v24, (a0)
; CHECK-NEXT: vlseg6e32.v v18, (a1)
@@ -1092,16 +1092,16 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e64.v v24, (a0)
; CHECK-NEXT: vlseg6e64.v v18, (a1)
@@ -1168,14 +1168,14 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vmv1r.v v8, v23
; CHECK-NEXT: vmv1r.v v9, v14
; CHECK-NEXT: vmv1r.v v12, v25
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vmv1r.v v13, v26
; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: vmv1r.v v14, v27
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg7e8.v v8, (a0)
@@ -1215,7 +1215,10 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -1225,10 +1228,7 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e8.v v14, (a0)
; CHECK-NEXT: vlseg7e8.v v22, (a1)
@@ -1262,7 +1262,10 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -1272,10 +1275,7 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e16.v v14, (a0)
; CHECK-NEXT: vlseg7e16.v v22, (a1)
@@ -1309,7 +1309,10 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -1319,10 +1322,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e32.v v14, (a0)
; CHECK-NEXT: vlseg7e32.v v22, (a1)
@@ -1356,7 +1356,10 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -1366,10 +1369,7 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e64.v v14, (a0)
; CHECK-NEXT: vlseg7e64.v v22, (a1)
@@ -1431,17 +1431,17 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v28, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: vmerge.vim v24, v10, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v26, v10, 1, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg8e8.v v18, (a0)
@@ -1483,12 +1483,12 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg8e8.v v0, (a0)
@@ -1525,12 +1525,12 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vlseg8e16.v v0, (a0)
@@ -1567,12 +1567,12 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-NEXT: vlseg8e32.v v0, (a0)
@@ -1609,12 +1609,12 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vlseg8e64.v v0, (a0)
@@ -1997,11 +1997,6 @@ define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @vector_d
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v10, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -2062,11 +2057,6 @@ define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @ve
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v10, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -2127,11 +2117,6 @@ define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @vecto
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v10, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -2452,13 +2437,6 @@ define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -2499,7 +2477,10 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -2507,10 +2488,7 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e16.v v12, (a0)
; CHECK-NEXT: vlseg5e16.v v18, (a1)
@@ -2539,13 +2517,6 @@ define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -2586,7 +2557,10 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -2594,10 +2568,7 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e16.v v12, (a0)
; CHECK-NEXT: vlseg5e16.v v18, (a1)
@@ -2626,13 +2597,6 @@ define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -2673,7 +2637,10 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -2681,10 +2648,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e32.v v12, (a0)
; CHECK-NEXT: vlseg5e32.v v18, (a1)
@@ -2733,7 +2697,10 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -2741,10 +2708,7 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e64.v v12, (a0)
; CHECK-NEXT: vlseg5e64.v v18, (a1)
@@ -2773,15 +2737,6 @@ define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -2822,16 +2777,16 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e16.v v24, (a0)
; CHECK-NEXT: vlseg6e16.v v18, (a1)
@@ -2863,15 +2818,6 @@ define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -2912,16 +2858,16 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e16.v v24, (a0)
; CHECK-NEXT: vlseg6e16.v v18, (a1)
@@ -2953,15 +2899,6 @@ define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -3002,16 +2939,16 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e32.v v24, (a0)
; CHECK-NEXT: vlseg6e32.v v18, (a1)
@@ -3063,16 +3000,16 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e64.v v24, (a0)
; CHECK-NEXT: vlseg6e64.v v18, (a1)
@@ -3104,15 +3041,6 @@ define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v12, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v12, a0
-; CHECK-NEXT: vslidedown.vx v12, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v12, a0
-; CHECK-NEXT: vslidedown.vx v12, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v12, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -3153,7 +3081,10 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -3163,10 +3094,7 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e16.v v14, (a0)
; CHECK-NEXT: vlseg7e16.v v22, (a1)
@@ -3199,15 +3127,6 @@ define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v12, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v12, a0
-; CHECK-NEXT: vslidedown.vx v12, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v12, a0
-; CHECK-NEXT: vslidedown.vx v12, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v12, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -3248,7 +3167,10 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -3258,10 +3180,7 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e16.v v14, (a0)
; CHECK-NEXT: vlseg7e16.v v22, (a1)
@@ -3294,15 +3213,6 @@ define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v12, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v12, a0
-; CHECK-NEXT: vslidedown.vx v12, v8, a0
-; CHECK-NEXT: vslideup.vx v8, v12, a0
-; CHECK-NEXT: vslidedown.vx v12, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v12, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -3343,7 +3253,10 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -3353,10 +3266,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e32.v v14, (a0)
; CHECK-NEXT: vlseg7e32.v v22, (a1)
@@ -3409,7 +3319,10 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -3419,10 +3332,7 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e64.v v14, (a0)
; CHECK-NEXT: vlseg7e64.v v22, (a1)
@@ -3495,12 +3405,12 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vlseg8e16.v v0, (a0)
@@ -3577,12 +3487,12 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vlseg8e16.v v0, (a0)
@@ -3659,12 +3569,12 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-NEXT: vlseg8e32.v v0, (a0)
@@ -3721,12 +3631,12 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vlseg8e64.v v0, (a0)
@@ -3824,22 +3734,57 @@ define <vscale x 1 x float> @vector_deinterleave_nxv1f32_nxv8f32_oneactive2(<vsc
define { <8 x float>, <8 x float> } @interleave_deinterleave2(<8 x float> %a, <8 x float> %b) {
; V-LABEL: interleave_deinterleave2:
; V: # %bb.0: # %entry
-; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; V-NEXT: vwaddu.vv v12, v8, v10
-; V-NEXT: li a0, -1
-; V-NEXT: vwmaccu.vx v12, a0, v10
+; V-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; V-NEXT: vslidedown.vi v12, v10, 4
+; V-NEXT: vslidedown.vi v14, v8, 4
+; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; V-NEXT: vzext.vf2 v16, v12
; V-NEXT: li a0, 32
-; V-NEXT: vnsrl.wx v10, v12, a0
-; V-NEXT: vnsrl.wi v8, v12, 0
+; V-NEXT: vsll.vx v12, v16, a0
+; V-NEXT: li a1, 170
+; V-NEXT: vmv.s.x v0, a1
+; V-NEXT: vzext.vf2 v16, v14
+; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; V-NEXT: vmerge.vvm v12, v16, v12, v0
+; V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; V-NEXT: vwaddu.vv v14, v8, v10
+; V-NEXT: li a1, -1
+; V-NEXT: vwmaccu.vx v14, a1, v10
+; V-NEXT: vnsrl.wi v8, v14, 0
+; V-NEXT: vnsrl.wi v10, v12, 0
+; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; V-NEXT: vslideup.vi v8, v10, 4
+; V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; V-NEXT: vnsrl.wx v10, v14, a0
+; V-NEXT: vnsrl.wx v14, v12, a0
+; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; V-NEXT: vslideup.vi v10, v14, 4
; V-NEXT: ret
;
; ZVZIP-LABEL: interleave_deinterleave2:
; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v12, v10, 4
+; ZVZIP-NEXT: vslidedown.vi v14, v8, 4
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v16, v9, v12
+; ZVZIP-NEXT: vzip.vv v12, v14, v9
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vmerge.vvm v12, v12, v16, v0
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v14, v8, v10
+; ZVZIP-NEXT: vnsrl.wi v10, v12, 0
+; ZVZIP-NEXT: vnsrl.wi v8, v14, 0
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 4
; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vnsrl.wx v16, v12, a0
+; ZVZIP-NEXT: vnsrl.wx v10, v14, a0
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vzip.vv v12, v8, v10
-; ZVZIP-NEXT: vnsrl.wx v10, v12, a0
-; ZVZIP-NEXT: vnsrl.wi v8, v12, 0
+; ZVZIP-NEXT: vslideup.vi v10, v16, 4
; ZVZIP-NEXT: ret
entry:
%0 = call <16 x float> @llvm.vector.interleave2.v16f32(<8 x float> %a, <8 x float> %b)
@@ -3854,18 +3799,47 @@ define <16 x float> @deinterleave_interleave2(<16 x float> %arg) {
; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; V-NEXT: vnsrl.wx v12, v8, a0
; V-NEXT: vnsrl.wi v14, v8, 0
+; V-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; V-NEXT: vslidedown.vi v8, v12, 4
+; V-NEXT: vslidedown.vi v10, v14, 4
+; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; V-NEXT: vzext.vf2 v16, v8
+; V-NEXT: vsll.vx v16, v16, a0
+; V-NEXT: li a0, 170
+; V-NEXT: vmv.s.x v0, a0
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; V-NEXT: vwaddu.vv v8, v14, v12
+; V-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; V-NEXT: vzext.vf2 v14, v10
; V-NEXT: li a0, -1
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; V-NEXT: vwmaccu.vx v8, a0, v12
+; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; V-NEXT: vmerge.vvm v12, v14, v16, v0
+; V-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; V-NEXT: vslideup.vi v8, v12, 8
; V-NEXT: ret
;
; ZVZIP-LABEL: deinterleave_interleave2:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: li a0, 32
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vnsrl.wx v12, v8, a0
-; ZVZIP-NEXT: vnsrl.wi v14, v8, 0
-; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: vnsrl.wx v14, v8, a0
+; ZVZIP-NEXT: vnsrl.wi v16, v8, 0
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v8, v14, 4
+; ZVZIP-NEXT: vslidedown.vi v10, v16, 4
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v9, v8
+; ZVZIP-NEXT: vzip.vv v8, v10, v11
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vmerge.vvm v12, v8, v12, v0
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v8, v16, v14
+; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 8
; ZVZIP-NEXT: ret
entry:
%0 = call { <8 x float>, <8 x float> } @llvm.vector.deinterleave2.v16f32(<16 x float> %arg)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index 56a68500747dd..d20c4b7fb661c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -11,53 +11,92 @@
define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; CHECK-LABEL: vector_interleave_v32i1_v16i1:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: lui a0, 11
+; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
+; CHECK-NEXT: addi a0, a0, -1366
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 8
+; CHECK-NEXT: vslidedown.vi v11, v9, 8
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v10
+; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v9, v11
+; CHECK-NEXT: vsll.vi v11, v12, 8
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v10, a0, v8
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
+; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v8, 2
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 16
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vwaddu.vv v12, v8, v10
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vwmaccu.vx v12, a1, v10
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v32i1_v16i1:
; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVBB-NEXT: vmv.v.i v9, 0
+; ZVBB-NEXT: vmerge.vim v10, v9, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v8
+; ZVBB-NEXT: lui a0, 11
+; ZVBB-NEXT: vmerge.vim v8, v9, 1, v0
+; ZVBB-NEXT: addi a0, a0, -1366
+; ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVBB-NEXT: vmv.s.x v0, a0
+; ZVBB-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; ZVBB-NEXT: vslidedown.vi v9, v10, 8
+; ZVBB-NEXT: vslidedown.vi v11, v8, 8
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v9
+; ZVBB-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vi v9, v8, 8
+; ZVBB-NEXT: vwaddu.wv v9, v9, v10
+; ZVBB-NEXT: vwsll.vi v8, v11, 8
+; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVBB-NEXT: vmerge.vvm v8, v12, v8, v0
+; ZVBB-NEXT: vmsne.vi v0, v9, 0
+; ZVBB-NEXT: vmsne.vi v8, v8, 0
; ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVBB-NEXT: vslideup.vi v0, v8, 2
-; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZVBB-NEXT: vmv.v.i v8, 0
-; ZVBB-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVBB-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; ZVBB-NEXT: vslidedown.vi v10, v8, 16
-; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVBB-NEXT: vwsll.vi v12, v10, 8
-; ZVBB-NEXT: vwaddu.wv v12, v12, v8
-; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZVBB-NEXT: vmsne.vi v0, v12, 0
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v32i1_v16i1:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v9, v0
+; ZVZIP-NEXT: vmv.v.i v10, 0
+; ZVZIP-NEXT: vmv1r.v v0, v8
+; ZVZIP-NEXT: vmerge.vim v8, v10, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v9
+; ZVZIP-NEXT: lui a0, 11
+; ZVZIP-NEXT: vmerge.vim v9, v10, 1, v0
+; ZVZIP-NEXT: addi a0, a0, -1366
+; ZVZIP-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 8
+; ZVZIP-NEXT: vslidedown.vi v11, v9, 8
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v13, v12, v10
+; ZVZIP-NEXT: vzip.vv v12, v11, v10
+; ZVZIP-NEXT: vzip.vv v10, v9, v8
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVZIP-NEXT: vmerge.vvm v8, v12, v13, v0
+; ZVZIP-NEXT: vmsne.vi v0, v10, 0
+; ZVZIP-NEXT: vmsne.vi v8, v8, 0
; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVZIP-NEXT: vslideup.vi v0, v8, 2
-; ZVZIP-NEXT: li a0, 32
-; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZVZIP-NEXT: vmv.v.i v8, 0
-; ZVZIP-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVZIP-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v10, v8, 16
-; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v12, v8, v10
-; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZVZIP-NEXT: vmsne.vi v0, v12, 0
; ZVZIP-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
ret <32 x i1> %res
@@ -66,29 +105,64 @@ define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: vector_interleave_v16i16_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: li a0, 170
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vslidedown.vi v8, v8, 4
+; CHECK-NEXT: vslidedown.vi v11, v9, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v8, v10, v9
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsll.vi v10, v13, 16
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v8, a0, v10
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v8, a0, v9
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 8
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16i16_v8i16:
; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v8
+; ZVBB-NEXT: li a0, 170
+; ZVBB-NEXT: vmv.s.x v0, a0
+; ZVBB-NEXT: vslidedown.vi v8, v8, 4
+; ZVBB-NEXT: vslidedown.vi v11, v9, 4
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v8
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vi v8, v9, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v10
+; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vmv1r.v v11, v8
-; ZVBB-NEXT: vwsll.vi v8, v10, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v11
+; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
+; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 8
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16i16_v8i16:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslidedown.vi v8, v9, 4
+; ZVZIP-NEXT: vslidedown.vi v11, v10, 4
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v13, v12, v8
+; ZVZIP-NEXT: vzip.vv v12, v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v10, v9
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vmerge.vvm v10, v12, v13, v0
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 8
; ZVZIP-NEXT: ret
%res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)
ret <16 x i16> %res
@@ -97,30 +171,63 @@ define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: vector_interleave_v8i32_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: vslidedown.vi v8, v9, 2
+; CHECK-NEXT: vslidedown.vi v11, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv.v.i v0, 10
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v8, v10, v9
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsll.vx v10, v12, a0
+; CHECK-NEXT: vzext.vf2 v12, v11
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v8, a0, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v8, a0, v9
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8i32_v4i32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v8
+; ZVBB-NEXT: vslidedown.vi v8, v8, 2
+; ZVBB-NEXT: vmv.v.i v0, 10
+; ZVBB-NEXT: vslidedown.vi v11, v9, 2
; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vwsll.vx v8, v10, a0
-; ZVBB-NEXT: vwaddu.wv v8, v8, v11
+; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v8
+; ZVBB-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vx v8, v9, a0
+; ZVBB-NEXT: vwaddu.wv v8, v8, v10
+; ZVBB-NEXT: vwsll.vx v9, v11, a0
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
+; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 4
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8i32_v4i32:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslidedown.vi v8, v9, 2
+; ZVZIP-NEXT: vslidedown.vi v11, v10, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v13, v12, v8
+; ZVZIP-NEXT: vzip.vv v12, v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v10, v9
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vmerge.vvm v10, v12, v13, v0
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 4
; ZVZIP-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)
ret <8 x i32> %res
@@ -129,40 +236,33 @@ define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: vector_interleave_v4i64_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 1
; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: lui a0, 12304
-; CHECK-NEXT: addi a0, a0, 512
-; CHECK-NEXT: vmv.s.x v10, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vsext.vf2 v12, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4i64_v2i64:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVBB-NEXT: vmv.v.i v0, 1
; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; ZVBB-NEXT: vslideup.vi v8, v9, 1
+; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 2
-; ZVBB-NEXT: lui a0, 12304
-; ZVBB-NEXT: addi a0, a0, 512
-; ZVBB-NEXT: vmv.s.x v10, a0
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vsext.vf2 v12, v10
-; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
-; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4i64_v2i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vpairo.vv v10, v8, v9
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 2
; ZVZIP-NEXT: ret
%res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
ret <4 x i64> %res
@@ -236,20 +336,8 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; CHECK-NEXT: mv a0, sp
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsseg4e32.v v8, (a0)
-; CHECK-NEXT: addi a1, sp, 24
-; CHECK-NEXT: vle32.v v9, (a1)
-; CHECK-NEXT: addi a1, sp, 8
-; CHECK-NEXT: vle32.v v10, (a1)
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v9, 2
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
@@ -259,20 +347,8 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZVBB-NEXT: mv a0, sp
; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
-; ZVBB-NEXT: addi a1, sp, 24
-; ZVBB-NEXT: vle32.v v9, (a1)
-; ZVBB-NEXT: addi a1, sp, 8
-; ZVBB-NEXT: vle32.v v10, (a1)
-; ZVBB-NEXT: vle32.v v8, (a0)
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 2
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a0)
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 2
-; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vle64.v v8, (a0)
; ZVBB-NEXT: addi sp, sp, 32
; ZVBB-NEXT: ret
;
@@ -282,20 +358,8 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZVZIP-NEXT: mv a0, sp
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVZIP-NEXT: vsseg4e32.v v8, (a0)
-; ZVZIP-NEXT: addi a1, sp, 24
-; ZVZIP-NEXT: vle32.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 8
-; ZVZIP-NEXT: vle32.v v10, (a1)
-; ZVZIP-NEXT: vle32.v v8, (a0)
-; ZVZIP-NEXT: addi a0, sp, 16
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vle32.v v10, (a0)
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v9, 2
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave4.v8i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d)
@@ -600,36 +664,8 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; CHECK-NEXT: mv a0, sp
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vsseg8e8.v v8, (a0)
-; CHECK-NEXT: addi a1, sp, 10
-; CHECK-NEXT: vle8.v v9, (a1)
-; CHECK-NEXT: addi a1, sp, 8
-; CHECK-NEXT: vle8.v v10, (a1)
-; CHECK-NEXT: addi a1, sp, 12
-; CHECK-NEXT: vle8.v v11, (a1)
-; CHECK-NEXT: addi a1, sp, 2
-; CHECK-NEXT: vle8.v v12, (a1)
-; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: addi a0, sp, 4
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v9, 2
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v12, 2
-; CHECK-NEXT: addi a0, sp, 14
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vle8.v v12, (a0)
-; CHECK-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v11, 4
-; CHECK-NEXT: vslideup.vi v8, v9, 4
-; CHECK-NEXT: addi a0, sp, 6
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v12, 6
-; CHECK-NEXT: vslideup.vi v8, v9, 6
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
@@ -639,36 +675,8 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZVBB-NEXT: mv a0, sp
; ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; ZVBB-NEXT: vsseg8e8.v v8, (a0)
-; ZVBB-NEXT: addi a1, sp, 10
-; ZVBB-NEXT: vle8.v v9, (a1)
-; ZVBB-NEXT: addi a1, sp, 8
-; ZVBB-NEXT: vle8.v v10, (a1)
-; ZVBB-NEXT: addi a1, sp, 12
-; ZVBB-NEXT: vle8.v v11, (a1)
-; ZVBB-NEXT: addi a1, sp, 2
-; ZVBB-NEXT: vle8.v v12, (a1)
-; ZVBB-NEXT: vle8.v v8, (a0)
-; ZVBB-NEXT: addi a0, sp, 4
-; ZVBB-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 2
-; ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVBB-NEXT: vle8.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v8, v12, 2
-; ZVBB-NEXT: addi a0, sp, 14
-; ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVBB-NEXT: vle8.v v12, (a0)
-; ZVBB-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v11, 4
-; ZVBB-NEXT: vslideup.vi v8, v9, 4
-; ZVBB-NEXT: addi a0, sp, 6
-; ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVBB-NEXT: vle8.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v12, 6
-; ZVBB-NEXT: vslideup.vi v8, v9, 6
-; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 8
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
@@ -678,36 +686,8 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZVZIP-NEXT: mv a0, sp
; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; ZVZIP-NEXT: vsseg8e8.v v8, (a0)
-; ZVZIP-NEXT: addi a1, sp, 10
-; ZVZIP-NEXT: vle8.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 8
-; ZVZIP-NEXT: vle8.v v10, (a1)
-; ZVZIP-NEXT: addi a1, sp, 12
-; ZVZIP-NEXT: vle8.v v11, (a1)
-; ZVZIP-NEXT: addi a1, sp, 2
-; ZVZIP-NEXT: vle8.v v12, (a1)
-; ZVZIP-NEXT: vle8.v v8, (a0)
-; ZVZIP-NEXT: addi a0, sp, 4
-; ZVZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v9, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-NEXT: vle8.v v9, (a0)
-; ZVZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 2
-; ZVZIP-NEXT: addi a0, sp, 14
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-NEXT: vle8.v v12, (a0)
-; ZVZIP-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 4
-; ZVZIP-NEXT: vslideup.vi v8, v9, 4
-; ZVZIP-NEXT: addi a0, sp, 6
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-NEXT: vle8.v v9, (a0)
-; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v12, 6
-; ZVZIP-NEXT: vslideup.vi v8, v9, 6
-; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 8
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a0)
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
%res = call <16 x i8> @llvm.vector.interleave8.v16i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g, <2 x i8> %h)
@@ -719,25 +699,34 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: vector_interleave_v4f16_v2f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 1
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f16_v2f16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVBB-NEXT: vwsll.vi v10, v9, 16
-; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
+; ZVBB-NEXT: vmv.v.i v0, 1
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; ZVBB-NEXT: vslideup.vi v8, v9, 1
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 2
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f16_v2f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vpairo.vv v11, v8, v9
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v11, 2
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
%res = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b)
@@ -747,25 +736,34 @@ define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v4bf16_v2bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 1
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVBB-NEXT: vwsll.vi v10, v9, 16
-; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
+; ZVBB-NEXT: vmv.v.i v0, 1
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; ZVBB-NEXT: vslideup.vi v8, v9, 1
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 2
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vpairo.vv v11, v8, v9
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v11, 2
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
%res = call <4 x bfloat> @llvm.vector.interleave2.v4bf16(<2 x bfloat> %a, <2 x bfloat> %b)
@@ -775,26 +773,62 @@ define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloa
define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
; CHECK-LABEL: vector_interleave_v8f16_v4f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v0, 10
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vslidedown.vi v11, v8, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v10
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsll.vi v11, v12, 16
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v13, v11, v0
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v8, 4
+; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8f16_v4f16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVBB-NEXT: vmv.v.i v0, 10
+; ZVBB-NEXT: vslidedown.vi v10, v8, 2
+; ZVBB-NEXT: vslidedown.vi v11, v9, 2
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v10
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v13, v11, 16
; ZVBB-NEXT: vwsll.vi v10, v9, 16
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vmerge.vvm v9, v12, v13, v0
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v10, v9, 4
+; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8f16_v4f16:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslidedown.vi v10, v9, 2
+; ZVZIP-NEXT: vslidedown.vi v11, v8, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vzip.vv v13, v12, v10
+; ZVZIP-NEXT: vzip.vv v12, v11, v10
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vmerge.vvm v11, v12, v13, v0
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v11, 4
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)
ret <8 x half> %res
@@ -803,26 +837,62 @@ define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v8bf16_v4bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v0, 10
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vslidedown.vi v11, v8, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v10
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsll.vi v11, v12, 16
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v13, v11, v0
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v8, 4
+; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVBB-NEXT: vmv.v.i v0, 10
+; ZVBB-NEXT: vslidedown.vi v10, v8, 2
+; ZVBB-NEXT: vslidedown.vi v11, v9, 2
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v10
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v13, v11, 16
; ZVBB-NEXT: vwsll.vi v10, v9, 16
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vmerge.vvm v9, v12, v13, v0
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v10, v9, 4
+; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslidedown.vi v10, v9, 2
+; ZVZIP-NEXT: vslidedown.vi v11, v8, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vzip.vv v13, v12, v10
+; ZVZIP-NEXT: vzip.vv v12, v11, v10
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vmerge.vvm v11, v12, v13, v0
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v11, 4
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%res = call <8 x bfloat> @llvm.vector.interleave2.v8bf16(<4 x bfloat> %a, <4 x bfloat> %b)
ret <8 x bfloat> %res
@@ -831,27 +901,35 @@ define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloa
define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: vector_interleave_v4f32_v2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 1
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f32_v2f32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vx v10, v9, a0
-; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
+; ZVBB-NEXT: vmv.v.i v0, 1
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; ZVBB-NEXT: vslideup.vi v8, v9, 1
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 2
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f32_v2f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vpairo.vv v11, v8, v9
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v11, 2
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)
ret <4 x float> %res
@@ -860,29 +938,64 @@ define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b
define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: vector_interleave_v16f16_v8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: li a0, 170
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vslidedown.vi v8, v8, 4
+; CHECK-NEXT: vslidedown.vi v11, v9, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v8, v10, v9
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsll.vi v10, v13, 16
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v8, a0, v10
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v8, a0, v9
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 8
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16f16_v8f16:
; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v8
+; ZVBB-NEXT: li a0, 170
+; ZVBB-NEXT: vmv.s.x v0, a0
+; ZVBB-NEXT: vslidedown.vi v8, v8, 4
+; ZVBB-NEXT: vslidedown.vi v11, v9, 4
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v8
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vi v8, v9, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v10
+; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vmv1r.v v11, v8
-; ZVBB-NEXT: vwsll.vi v8, v10, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v11
+; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
+; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 8
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16f16_v8f16:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslidedown.vi v8, v9, 4
+; ZVZIP-NEXT: vslidedown.vi v11, v10, 4
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v13, v12, v8
+; ZVZIP-NEXT: vzip.vv v12, v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v10, v9
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vmerge.vvm v10, v12, v13, v0
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 8
; ZVZIP-NEXT: ret
%res = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b)
ret <16 x half> %res
@@ -891,29 +1004,64 @@ define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b)
define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v16bf16_v8bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: li a0, 170
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vslidedown.vi v8, v8, 4
+; CHECK-NEXT: vslidedown.vi v11, v9, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v8, v10, v9
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsll.vi v10, v13, 16
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v8, a0, v10
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v8, a0, v9
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 8
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v8
+; ZVBB-NEXT: li a0, 170
+; ZVBB-NEXT: vmv.s.x v0, a0
+; ZVBB-NEXT: vslidedown.vi v8, v8, 4
+; ZVBB-NEXT: vslidedown.vi v11, v9, 4
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v8
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vi v8, v9, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v10
+; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vmv1r.v v11, v8
-; ZVBB-NEXT: vwsll.vi v8, v10, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v11
+; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
+; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 8
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslidedown.vi v8, v9, 4
+; ZVZIP-NEXT: vslidedown.vi v11, v10, 4
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v13, v12, v8
+; ZVZIP-NEXT: vzip.vv v12, v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v10, v9
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vmerge.vvm v10, v12, v13, v0
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 8
; ZVZIP-NEXT: ret
%res = call <16 x bfloat> @llvm.vector.interleave2.v16bf16(<8 x bfloat> %a, <8 x bfloat> %b)
ret <16 x bfloat> %res
@@ -922,30 +1070,63 @@ define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfl
define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: vector_interleave_v8f32_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: vslidedown.vi v8, v9, 2
+; CHECK-NEXT: vslidedown.vi v11, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv.v.i v0, 10
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v8, v10, v9
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsll.vx v10, v12, a0
+; CHECK-NEXT: vzext.vf2 v12, v11
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v8, a0, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v8, a0, v9
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8f32_v4f32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v8
+; ZVBB-NEXT: vslidedown.vi v8, v8, 2
+; ZVBB-NEXT: vmv.v.i v0, 10
+; ZVBB-NEXT: vslidedown.vi v11, v9, 2
; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vwsll.vx v8, v10, a0
-; ZVBB-NEXT: vwaddu.wv v8, v8, v11
+; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v8
+; ZVBB-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vx v8, v9, a0
+; ZVBB-NEXT: vwaddu.wv v8, v8, v10
+; ZVBB-NEXT: vwsll.vx v9, v11, a0
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
+; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 4
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8f32_v4f32:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslidedown.vi v8, v9, 2
+; ZVZIP-NEXT: vslidedown.vi v11, v10, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vzip.vv v13, v12, v8
+; ZVZIP-NEXT: vzip.vv v12, v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v10, v9
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vmerge.vvm v10, v12, v13, v0
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 4
; ZVZIP-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)
ret <8 x float> %res
@@ -954,40 +1135,34 @@ define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b
define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: vector_interleave_v4f64_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 1
; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: lui a0, 12304
-; CHECK-NEXT: addi a0, a0, 512
-; CHECK-NEXT: vmv.s.x v10, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vsext.vf2 v12, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f64_v2f64:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVBB-NEXT: vmv.v.i v0, 1
; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; ZVBB-NEXT: vslideup.vi v8, v9, 1
+; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 2
-; ZVBB-NEXT: lui a0, 12304
-; ZVBB-NEXT: addi a0, a0, 512
-; ZVBB-NEXT: vmv.s.x v10, a0
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vsext.vf2 v12, v10
-; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
-; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f64_v2f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vpairo.vv v12, v10, v9
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 2
; ZVZIP-NEXT: ret
%res = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)
ret <4 x double> %res
@@ -1061,20 +1236,8 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
; CHECK-NEXT: mv a0, sp
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsseg4e32.v v8, (a0)
-; CHECK-NEXT: addi a1, sp, 24
-; CHECK-NEXT: vle32.v v9, (a1)
-; CHECK-NEXT: addi a1, sp, 8
-; CHECK-NEXT: vle32.v v10, (a1)
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v9, 2
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
@@ -1084,20 +1247,8 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
; ZVBB-NEXT: mv a0, sp
; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
-; ZVBB-NEXT: addi a1, sp, 24
-; ZVBB-NEXT: vle32.v v9, (a1)
-; ZVBB-NEXT: addi a1, sp, 8
-; ZVBB-NEXT: vle32.v v10, (a1)
-; ZVBB-NEXT: vle32.v v8, (a0)
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 2
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a0)
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 2
-; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vle64.v v8, (a0)
; ZVBB-NEXT: addi sp, sp, 32
; ZVBB-NEXT: ret
;
@@ -1107,20 +1258,8 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
; ZVZIP-NEXT: mv a0, sp
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVZIP-NEXT: vsseg4e32.v v8, (a0)
-; ZVZIP-NEXT: addi a1, sp, 24
-; ZVZIP-NEXT: vle32.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 8
-; ZVZIP-NEXT: vle32.v v10, (a1)
-; ZVZIP-NEXT: vle32.v v8, (a0)
-; ZVZIP-NEXT: addi a0, sp, 16
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vle32.v v10, (a0)
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v9, 2
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave4.v8f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d)
@@ -1716,36 +1855,8 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
; CHECK-NEXT: mv a0, sp
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vsseg8e16.v v8, (a0)
-; CHECK-NEXT: addi a1, sp, 10
-; CHECK-NEXT: vle16.v v9, (a1)
-; CHECK-NEXT: addi a1, sp, 8
-; CHECK-NEXT: vle16.v v10, (a1)
-; CHECK-NEXT: addi a1, sp, 12
-; CHECK-NEXT: vle16.v v11, (a1)
-; CHECK-NEXT: addi a1, sp, 2
-; CHECK-NEXT: vle16.v v12, (a1)
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: addi a0, sp, 4
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v9, 1
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v12, 1
-; CHECK-NEXT: addi a0, sp, 14
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v12, (a0)
-; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v11, 2
-; CHECK-NEXT: vslideup.vi v8, v9, 2
-; CHECK-NEXT: addi a0, sp, 6
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v12, 3
-; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
@@ -1755,36 +1866,8 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVBB-NEXT: mv a0, sp
; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
-; ZVBB-NEXT: addi a1, sp, 10
-; ZVBB-NEXT: vle16.v v9, (a1)
-; ZVBB-NEXT: addi a1, sp, 8
-; ZVBB-NEXT: vle16.v v10, (a1)
-; ZVBB-NEXT: addi a1, sp, 12
-; ZVBB-NEXT: vle16.v v11, (a1)
-; ZVBB-NEXT: addi a1, sp, 2
-; ZVBB-NEXT: vle16.v v12, (a1)
-; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: addi a0, sp, 4
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 1
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v8, v12, 1
-; ZVBB-NEXT: addi a0, sp, 14
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v12, (a0)
-; ZVBB-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v11, 2
-; ZVBB-NEXT: vslideup.vi v8, v9, 2
-; ZVBB-NEXT: addi a0, sp, 6
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v12, 3
-; ZVBB-NEXT: vslideup.vi v8, v9, 3
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
@@ -1794,36 +1877,8 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVZIP-NEXT: mv a0, sp
; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVZIP-NEXT: vsseg8e16.v v8, (a0)
-; ZVZIP-NEXT: addi a1, sp, 10
-; ZVZIP-NEXT: vle16.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 8
-; ZVZIP-NEXT: vle16.v v10, (a1)
-; ZVZIP-NEXT: addi a1, sp, 12
-; ZVZIP-NEXT: vle16.v v11, (a1)
-; ZVZIP-NEXT: addi a1, sp, 2
-; ZVZIP-NEXT: vle16.v v12, (a1)
-; ZVZIP-NEXT: vle16.v v8, (a0)
-; ZVZIP-NEXT: addi a0, sp, 4
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v9, 1
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v9, (a0)
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 1
-; ZVZIP-NEXT: addi a0, sp, 14
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v12, (a0)
-; ZVZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 2
-; ZVZIP-NEXT: vslideup.vi v8, v9, 2
-; ZVZIP-NEXT: addi a0, sp, 6
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v9, (a0)
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v12, 3
-; ZVZIP-NEXT: vslideup.vi v8, v9, 3
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: vle16.v v8, (a0)
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave8.v8f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g, <1 x half> %h)
@@ -1837,36 +1892,8 @@ define <8 x bfloat> @vector_interleave8_v8bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
; CHECK-NEXT: mv a0, sp
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vsseg8e16.v v8, (a0)
-; CHECK-NEXT: addi a1, sp, 10
-; CHECK-NEXT: vle16.v v9, (a1)
-; CHECK-NEXT: addi a1, sp, 8
-; CHECK-NEXT: vle16.v v10, (a1)
-; CHECK-NEXT: addi a1, sp, 12
-; CHECK-NEXT: vle16.v v11, (a1)
-; CHECK-NEXT: addi a1, sp, 2
-; CHECK-NEXT: vle16.v v12, (a1)
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: addi a0, sp, 4
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v9, 1
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v12, 1
-; CHECK-NEXT: addi a0, sp, 14
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v12, (a0)
-; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v11, 2
-; CHECK-NEXT: vslideup.vi v8, v9, 2
-; CHECK-NEXT: addi a0, sp, 6
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v12, 3
-; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
@@ -1876,36 +1903,8 @@ define <8 x bfloat> @vector_interleave8_v8bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
; ZVBB-NEXT: mv a0, sp
; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
-; ZVBB-NEXT: addi a1, sp, 10
-; ZVBB-NEXT: vle16.v v9, (a1)
-; ZVBB-NEXT: addi a1, sp, 8
-; ZVBB-NEXT: vle16.v v10, (a1)
-; ZVBB-NEXT: addi a1, sp, 12
-; ZVBB-NEXT: vle16.v v11, (a1)
-; ZVBB-NEXT: addi a1, sp, 2
-; ZVBB-NEXT: vle16.v v12, (a1)
-; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: addi a0, sp, 4
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 1
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v8, v12, 1
-; ZVBB-NEXT: addi a0, sp, 14
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v12, (a0)
-; ZVBB-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v11, 2
-; ZVBB-NEXT: vslideup.vi v8, v9, 2
-; ZVBB-NEXT: addi a0, sp, 6
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v12, 3
-; ZVBB-NEXT: vslideup.vi v8, v9, 3
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
@@ -1915,36 +1914,8 @@ define <8 x bfloat> @vector_interleave8_v8bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
; ZVZIP-NEXT: mv a0, sp
; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVZIP-NEXT: vsseg8e16.v v8, (a0)
-; ZVZIP-NEXT: addi a1, sp, 10
-; ZVZIP-NEXT: vle16.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 8
-; ZVZIP-NEXT: vle16.v v10, (a1)
-; ZVZIP-NEXT: addi a1, sp, 12
-; ZVZIP-NEXT: vle16.v v11, (a1)
-; ZVZIP-NEXT: addi a1, sp, 2
-; ZVZIP-NEXT: vle16.v v12, (a1)
-; ZVZIP-NEXT: vle16.v v8, (a0)
-; ZVZIP-NEXT: addi a0, sp, 4
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v9, 1
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v9, (a0)
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 1
-; ZVZIP-NEXT: addi a0, sp, 14
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v12, (a0)
-; ZVZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 2
-; ZVZIP-NEXT: vslideup.vi v8, v9, 2
-; ZVZIP-NEXT: addi a0, sp, 6
-; ZVZIP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v9, (a0)
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v12, 3
-; ZVZIP-NEXT: vslideup.vi v8, v9, 3
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: vle16.v v8, (a0)
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
%res = call <8 x bfloat> @llvm.vector.interleave8.v8bf16(<1 x bfloat> %a, <1 x bfloat> %b, <1 x bfloat> %c, <1 x bfloat> %d, <1 x bfloat> %e, <1 x bfloat> %f, <1 x bfloat> %g, <1 x bfloat> %h)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index b4053654e42f2..ba91f6677b7f1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -494,13 +494,14 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vsseg3e8.v v14, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: vl2r.v v8, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2r.v v8, (a2)
; CHECK-NEXT: vmsne.vi v10, v8, 0
; CHECK-NEXT: vl2r.v v8, (a0)
-; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: slli a2, a1, 2
+; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: vl2r.v v8, (a2)
+; CHECK-NEXT: vl2r.v v8, (a0)
; CHECK-NEXT: vmsne.vi v11, v8, 0
; CHECK-NEXT: srli a0, a1, 2
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
@@ -535,13 +536,14 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vsseg3e8.v v14, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: slli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: vl2r.v v8, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2r.v v8, (a2)
; ZVBB-NEXT: vmsne.vi v10, v8, 0
; ZVBB-NEXT: vl2r.v v8, (a0)
-; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a0, a0, a2
; ZVBB-NEXT: vmsne.vi v0, v8, 0
-; ZVBB-NEXT: vl2r.v v8, (a2)
+; ZVBB-NEXT: vl2r.v v8, (a0)
; ZVBB-NEXT: vmsne.vi v11, v8, 0
; ZVBB-NEXT: srli a0, a1, 2
; ZVBB-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
@@ -573,9 +575,10 @@ define <vscale x 48 x i8> @vector_interleave_nxv48i8_nxv16i8(<vscale x 16 x i8>
; CHECK-NEXT: vsseg3e8.v v8, (a0)
; CHECK-NEXT: vl2r.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2r.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2r.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2r.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -597,9 +600,10 @@ define <vscale x 48 x i8> @vector_interleave_nxv48i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-NEXT: vsseg3e8.v v8, (a0)
; ZVBB-NEXT: vl2r.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2r.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2r.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2r.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -626,9 +630,10 @@ define <vscale x 24 x i16> @vector_interleave_nxv24i16_nxv8i16(<vscale x 8 x i16
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: vl2re16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re16.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re16.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re16.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -650,9 +655,10 @@ define <vscale x 24 x i16> @vector_interleave_nxv24i16_nxv8i16(<vscale x 8 x i16
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: vl2re16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re16.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re16.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re16.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -679,9 +685,10 @@ define <vscale x 12 x i32> @vector_interleave_nxv12i32_nxv4i32(<vscale x 4 x i32
; CHECK-NEXT: vsseg3e32.v v8, (a0)
; CHECK-NEXT: vl2re32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re32.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re32.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re32.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -703,9 +710,10 @@ define <vscale x 12 x i32> @vector_interleave_nxv12i32_nxv4i32(<vscale x 4 x i32
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
; ZVBB-NEXT: vl2re32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re32.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re32.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re32.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -732,9 +740,10 @@ define <vscale x 6 x i64> @vector_interleave_nxv6i64_nxv2i64(<vscale x 2 x i64>
; CHECK-NEXT: vsseg3e64.v v8, (a0)
; CHECK-NEXT: vl2re64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re64.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re64.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re64.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -756,9 +765,10 @@ define <vscale x 6 x i64> @vector_interleave_nxv6i64_nxv2i64(<vscale x 2 x i64>
; ZVBB-NEXT: vsseg3e64.v v8, (a0)
; ZVBB-NEXT: vl2re64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re64.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re64.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re64.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -793,14 +803,16 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vsseg4e8.v v14, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 2
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a2, a4, a2
-; CHECK-NEXT: vl2r.v v8, (a2)
-; CHECK-NEXT: vmsne.vi v10, v8, 0
+; CHECK-NEXT: add a4, a0, a4
; CHECK-NEXT: vl2r.v v8, (a4)
-; CHECK-NEXT: vmsne.vi v11, v8, 0
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vmsne.vi v10, v8, 0
; CHECK-NEXT: vl2r.v v8, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vmsne.vi v11, v8, 0
+; CHECK-NEXT: vl2r.v v8, (a2)
; CHECK-NEXT: vmsne.vi v12, v8, 0
; CHECK-NEXT: vl2r.v v8, (a0)
; CHECK-NEXT: vmsne.vi v0, v8, 0
@@ -838,14 +850,16 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vsseg4e8.v v14, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: slli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 2
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a2, a4, a2
-; ZVBB-NEXT: vl2r.v v8, (a2)
-; ZVBB-NEXT: vmsne.vi v10, v8, 0
+; ZVBB-NEXT: add a4, a0, a4
; ZVBB-NEXT: vl2r.v v8, (a4)
-; ZVBB-NEXT: vmsne.vi v11, v8, 0
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vmsne.vi v10, v8, 0
; ZVBB-NEXT: vl2r.v v8, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vmsne.vi v11, v8, 0
+; ZVBB-NEXT: vl2r.v v8, (a2)
; ZVBB-NEXT: vmsne.vi v12, v8, 0
; ZVBB-NEXT: vl2r.v v8, (a0)
; ZVBB-NEXT: vmsne.vi v0, v8, 0
@@ -877,14 +891,16 @@ define <vscale x 64 x i8> @vector_interleave_nxv64i8_nxv16i8(<vscale x 16 x i8>
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vsseg4e8.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 2
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl2r.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2r.v v14, (a1)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2r.v v14, (a2)
; CHECK-NEXT: vl2r.v v8, (a0)
-; CHECK-NEXT: vl2r.v v10, (a2)
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl2r.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -901,14 +917,16 @@ define <vscale x 64 x i8> @vector_interleave_nxv64i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; ZVBB-NEXT: vsseg4e8.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2r.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2r.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2r.v v14, (a2)
; ZVBB-NEXT: vl2r.v v8, (a0)
-; ZVBB-NEXT: vl2r.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2r.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -929,13 +947,14 @@ define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv8i8(<vscale x 8 x i8> %a
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg4e8.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1r.v v10, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1r.v v11, (a1)
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: add a2, a1, a2
+; CHECK-NEXT: vl1r.v v11, (a2)
; CHECK-NEXT: vl1r.v v8, (a0)
-; CHECK-NEXT: vl1r.v v9, (a2)
+; CHECK-NEXT: vl1r.v v9, (a1)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add sp, sp, a0
@@ -952,13 +971,14 @@ define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv8i8(<vscale x 8 x i8> %a
; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg4e8.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1r.v v10, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1r.v v11, (a1)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1r.v v11, (a2)
; ZVBB-NEXT: vl1r.v v8, (a0)
-; ZVBB-NEXT: vl1r.v v9, (a2)
+; ZVBB-NEXT: vl1r.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -980,14 +1000,16 @@ define <vscale x 16 x i32> @vector_interleave_nxv16i32_nxv4i32(<vscale x 4 x i32
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT: vsseg4e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 2
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl2re32.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re32.v v14, (a1)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re32.v v14, (a2)
; CHECK-NEXT: vl2re32.v v8, (a0)
-; CHECK-NEXT: vl2re32.v v10, (a2)
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl2re32.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -1004,14 +1026,16 @@ define <vscale x 16 x i32> @vector_interleave_nxv16i32_nxv4i32(<vscale x 4 x i32
; ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re32.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re32.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re32.v v14, (a2)
; ZVBB-NEXT: vl2re32.v v8, (a0)
-; ZVBB-NEXT: vl2re32.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re32.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -1033,14 +1057,16 @@ define <vscale x 8 x i64> @vector_interleave_nxv8i64_nxv2i64(<vscale x 2 x i64>
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-NEXT: vsseg4e64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 2
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl2re64.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re64.v v14, (a1)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re64.v v14, (a2)
; CHECK-NEXT: vl2re64.v v8, (a0)
-; CHECK-NEXT: vl2re64.v v10, (a2)
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl2re64.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -1057,14 +1083,16 @@ define <vscale x 8 x i64> @vector_interleave_nxv8i64_nxv2i64(<vscale x 2 x i64>
; ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; ZVBB-NEXT: vsseg4e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re64.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re64.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re64.v v14, (a2)
; ZVBB-NEXT: vl2re64.v v8, (a0)
-; ZVBB-NEXT: vl2re64.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re64.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -1097,51 +1125,54 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vmv1r.v v22, v14
; CHECK-NEXT: vmv1r.v v23, v8
; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg5e8.v v20, (a0)
-; CHECK-NEXT: vmv1r.v v14, v19
-; CHECK-NEXT: vmv1r.v v16, v9
-; CHECK-NEXT: vmv1r.v v17, v25
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 2
-; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: slli a0, a1, 2
+; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsseg5e8.v v13, (a1)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsseg5e8.v v20, (a1)
+; CHECK-NEXT: vmv1r.v v14, v19
+; CHECK-NEXT: vmv1r.v v16, v9
+; CHECK-NEXT: vmv1r.v v17, v25
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vsseg5e8.v v13, (a2)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a3, a0, 1
+; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl1r.v v8, (a4)
-; CHECK-NEXT: add a4, a4, a2
-; CHECK-NEXT: vl1r.v v9, (a4)
-; CHECK-NEXT: vl1r.v v10, (a0)
-; CHECK-NEXT: vl1r.v v11, (a3)
-; CHECK-NEXT: add a0, a1, a2
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; CHECK-NEXT: add a4, a3, a0
+; CHECK-NEXT: add a5, a1, a4
+; CHECK-NEXT: vl1r.v v9, (a5)
+; CHECK-NEXT: vl1r.v v10, (a1)
+; CHECK-NEXT: add a5, a1, a0
+; CHECK-NEXT: vl1r.v v11, (a5)
+; CHECK-NEXT: add a5, a2, a0
+; CHECK-NEXT: vsetvli a6, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v12, v8, 0
-; CHECK-NEXT: vl1r.v v8, (a0)
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: vl1r.v v9, (a0)
+; CHECK-NEXT: vl1r.v v8, (a5)
+; CHECK-NEXT: add a3, a2, a3
+; CHECK-NEXT: vl1r.v v9, (a3)
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: add a4, a4, a2
-; CHECK-NEXT: vl1r.v v10, (a4)
+; CHECK-NEXT: slli a3, a0, 2
+; CHECK-NEXT: add a1, a1, a3
+; CHECK-NEXT: vl1r.v v10, (a1)
; CHECK-NEXT: vmsne.vi v13, v8, 0
-; CHECK-NEXT: vl1r.v v11, (a1)
+; CHECK-NEXT: vl1r.v v11, (a2)
; CHECK-NEXT: vmsne.vi v9, v10, 0
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: vl1r.v v10, (a0)
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: srli a1, a2, 2
-; CHECK-NEXT: vl1r.v v11, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: add a4, a2, a4
+; CHECK-NEXT: vl1r.v v10, (a4)
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: srli a1, a0, 2
+; CHECK-NEXT: vl1r.v v11, (a2)
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vx v0, v12, a1
; CHECK-NEXT: vslideup.vx v9, v13, a1
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v8, v10, 0
-; CHECK-NEXT: srli a2, a2, 1
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v9, a2
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v0, v9, a0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 10
; CHECK-NEXT: mul a0, a0, a1
@@ -1171,51 +1202,54 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vmv1r.v v22, v14
; ZVBB-NEXT: vmv1r.v v23, v8
; ZVBB-NEXT: vmerge.vim v24, v16, 1, v0
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg5e8.v v20, (a0)
-; ZVBB-NEXT: vmv1r.v v14, v19
-; ZVBB-NEXT: vmv1r.v v16, v9
-; ZVBB-NEXT: vmv1r.v v17, v25
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a2, a1, 2
-; ZVBB-NEXT: add a1, a2, a1
+; ZVBB-NEXT: slli a0, a1, 2
+; ZVBB-NEXT: add a1, a0, a1
; ZVBB-NEXT: add a1, sp, a1
; ZVBB-NEXT: addi a1, a1, 16
-; ZVBB-NEXT: vsseg5e8.v v13, (a1)
-; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vsseg5e8.v v20, (a1)
+; ZVBB-NEXT: vmv1r.v v14, v19
+; ZVBB-NEXT: vmv1r.v v16, v9
+; ZVBB-NEXT: vmv1r.v v17, v25
+; ZVBB-NEXT: addi a2, sp, 16
+; ZVBB-NEXT: vsseg5e8.v v13, (a2)
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a3, a0, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1r.v v8, (a4)
-; ZVBB-NEXT: add a4, a4, a2
-; ZVBB-NEXT: vl1r.v v9, (a4)
-; ZVBB-NEXT: vl1r.v v10, (a0)
-; ZVBB-NEXT: vl1r.v v11, (a3)
-; ZVBB-NEXT: add a0, a1, a2
-; ZVBB-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; ZVBB-NEXT: add a4, a3, a0
+; ZVBB-NEXT: add a5, a1, a4
+; ZVBB-NEXT: vl1r.v v9, (a5)
+; ZVBB-NEXT: vl1r.v v10, (a1)
+; ZVBB-NEXT: add a5, a1, a0
+; ZVBB-NEXT: vl1r.v v11, (a5)
+; ZVBB-NEXT: add a5, a2, a0
+; ZVBB-NEXT: vsetvli a6, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v12, v8, 0
-; ZVBB-NEXT: vl1r.v v8, (a0)
-; ZVBB-NEXT: add a0, a0, a2
-; ZVBB-NEXT: vl1r.v v9, (a0)
+; ZVBB-NEXT: vl1r.v v8, (a5)
+; ZVBB-NEXT: add a3, a2, a3
+; ZVBB-NEXT: vl1r.v v9, (a3)
; ZVBB-NEXT: vmsne.vi v0, v10, 0
-; ZVBB-NEXT: add a4, a4, a2
-; ZVBB-NEXT: vl1r.v v10, (a4)
+; ZVBB-NEXT: slli a3, a0, 2
+; ZVBB-NEXT: add a1, a1, a3
+; ZVBB-NEXT: vl1r.v v10, (a1)
; ZVBB-NEXT: vmsne.vi v13, v8, 0
-; ZVBB-NEXT: vl1r.v v11, (a1)
+; ZVBB-NEXT: vl1r.v v11, (a2)
; ZVBB-NEXT: vmsne.vi v9, v10, 0
-; ZVBB-NEXT: add a0, a0, a2
-; ZVBB-NEXT: vl1r.v v10, (a0)
-; ZVBB-NEXT: add a0, a0, a2
-; ZVBB-NEXT: srli a1, a2, 2
-; ZVBB-NEXT: vl1r.v v11, (a0)
-; ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; ZVBB-NEXT: add a4, a2, a4
+; ZVBB-NEXT: vl1r.v v10, (a4)
+; ZVBB-NEXT: add a2, a2, a3
+; ZVBB-NEXT: srli a1, a0, 2
+; ZVBB-NEXT: vl1r.v v11, (a2)
+; ZVBB-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; ZVBB-NEXT: vslideup.vx v0, v12, a1
; ZVBB-NEXT: vslideup.vx v9, v13, a1
-; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v8, v10, 0
-; ZVBB-NEXT: srli a2, a2, 1
-; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v0, v9, a2
+; ZVBB-NEXT: srli a0, a0, 1
+; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v0, v9, a0
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: li a1, 10
; ZVBB-NEXT: mul a0, a0, a1
@@ -1249,35 +1283,38 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e8.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e8.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1r.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1r.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1r.v v11, (a5)
; RV32-NEXT: vl1r.v v8, (a0)
-; RV32-NEXT: vl1r.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1r.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1r.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1r.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1r.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1r.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1r.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1r.v v12, (a0)
; RV32-NEXT: vl1r.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1r.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1r.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1r.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1r.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -1315,35 +1352,38 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e8.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e8.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1r.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1r.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1r.v v11, (a5)
; RV64-NEXT: vl1r.v v8, (a0)
-; RV64-NEXT: vl1r.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1r.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1r.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1r.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1r.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1r.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1r.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1r.v v12, (a0)
; RV64-NEXT: vl1r.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1r.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1r.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1r.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1r.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -1381,35 +1421,38 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
-; ZVBB-RV32-NEXT: vsseg5e8.v v22, (a0)
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: vsseg5e8.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e8.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1r.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1r.v v11, (a5)
; ZVBB-RV32-NEXT: vl1r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1r.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1r.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1r.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1r.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1r.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1r.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1r.v v12, (a0)
; ZVBB-RV32-NEXT: vl1r.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1r.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1r.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1r.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1r.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -1447,35 +1490,38 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e8.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e8.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1r.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1r.v v11, (a5)
; ZVBB-RV64-NEXT: vl1r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1r.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1r.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1r.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1r.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1r.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1r.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1r.v v12, (a0)
; ZVBB-RV64-NEXT: vl1r.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1r.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1r.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1r.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1r.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -1513,35 +1559,38 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e8.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e8.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1r.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1r.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1r.v v11, (a5)
; ZVZIP-NEXT: vl1r.v v8, (a0)
-; ZVZIP-NEXT: vl1r.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1r.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1r.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1r.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1r.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1r.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1r.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1r.v v12, (a0)
; ZVZIP-NEXT: vl1r.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1r.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1r.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1r.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1r.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -1575,15 +1624,17 @@ define <vscale x 40 x i8> @vector_interleave_nxv40i8_nxv8i8(<vscale x 8 x i8> %a
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg5e8.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1r.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1r.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1r.v v11, (a2)
; CHECK-NEXT: vl1r.v v8, (a0)
-; CHECK-NEXT: vl1r.v v9, (a2)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1r.v v12, (a1)
+; CHECK-NEXT: vl1r.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1r.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
; CHECK-NEXT: add a0, a1, a0
@@ -1602,15 +1653,17 @@ define <vscale x 40 x i8> @vector_interleave_nxv40i8_nxv8i8(<vscale x 8 x i8> %a
; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg5e8.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1r.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1r.v v11, (a2)
; ZVBB-NEXT: vl1r.v v8, (a0)
-; ZVBB-NEXT: vl1r.v v9, (a2)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1r.v v12, (a1)
+; ZVBB-NEXT: vl1r.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1r.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
; ZVBB-NEXT: add a0, a1, a0
@@ -1644,35 +1697,38 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e32.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e32.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re32.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re32.v v11, (a5)
; RV32-NEXT: vl1re32.v v8, (a0)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re32.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re32.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re32.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re32.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re32.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re32.v v12, (a0)
; RV32-NEXT: vl1re32.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re32.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re32.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -1710,35 +1766,38 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e32.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e32.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re32.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re32.v v11, (a5)
; RV64-NEXT: vl1re32.v v8, (a0)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re32.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re32.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re32.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re32.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re32.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re32.v v12, (a0)
; RV64-NEXT: vl1re32.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re32.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re32.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -1776,35 +1835,38 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e32.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e32.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re32.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re32.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re32.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -1842,35 +1904,38 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e32.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e32.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re32.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re32.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re32.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -1908,35 +1973,38 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e32.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e32.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re32.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re32.v v11, (a5)
; ZVZIP-NEXT: vl1re32.v v8, (a0)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re32.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re32.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re32.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re32.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re32.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re32.v v12, (a0)
; ZVZIP-NEXT: vl1re32.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re32.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re32.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -1980,35 +2048,38 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e64.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e64.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re64.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re64.v v11, (a5)
; RV32-NEXT: vl1re64.v v8, (a0)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re64.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re64.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re64.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re64.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re64.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re64.v v12, (a0)
; RV32-NEXT: vl1re64.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re64.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re64.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -2046,35 +2117,38 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e64.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e64.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re64.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re64.v v11, (a5)
; RV64-NEXT: vl1re64.v v8, (a0)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re64.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re64.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re64.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re64.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re64.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re64.v v12, (a0)
; RV64-NEXT: vl1re64.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re64.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re64.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -2112,35 +2186,38 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e64.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e64.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re64.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re64.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re64.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -2178,35 +2255,38 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e64.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e64.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re64.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re64.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re64.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -2244,35 +2324,38 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e64.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e64.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re64.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re64.v v11, (a5)
; ZVZIP-NEXT: vl1re64.v v8, (a0)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re64.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re64.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re64.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re64.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re64.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re64.v v12, (a0)
; ZVZIP-NEXT: vl1re64.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re64.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re64.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -2319,60 +2402,64 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vmv1r.v v18, v25
; CHECK-NEXT: vmv1r.v v19, v11
; CHECK-NEXT: vmv1r.v v20, v13
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a0, 6
-; CHECK-NEXT: mul a1, a1, a0
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg6e8.v v15, (a1)
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsseg6e8.v v15, (a0)
; CHECK-NEXT: vmv1r.v v15, v22
; CHECK-NEXT: vmv1r.v v16, v8
; CHECK-NEXT: vmv1r.v v17, v24
; CHECK-NEXT: vmv1r.v v18, v10
; CHECK-NEXT: vmv1r.v v19, v12
-; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a1, 6
+; CHECK-NEXT: mul a2, a2, a1
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vsseg6e8.v v14, (a2)
-; CHECK-NEXT: vl1r.v v8, (a1)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: add a1, a1, a0
-; CHECK-NEXT: add a3, a2, a0
-; CHECK-NEXT: vl1r.v v9, (a1)
-; CHECK-NEXT: add a4, a3, a0
-; CHECK-NEXT: add a5, a4, a0
-; CHECK-NEXT: add a6, a5, a0
-; CHECK-NEXT: vl1r.v v10, (a6)
-; CHECK-NEXT: add a6, a6, a0
-; CHECK-NEXT: vl1r.v v11, (a6)
-; CHECK-NEXT: vl1r.v v12, (a4)
-; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
+; CHECK-NEXT: vl1r.v v8, (a0)
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: vl1r.v v9, (a3)
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: add a4, a2, a3
+; CHECK-NEXT: vl1r.v v10, (a4)
+; CHECK-NEXT: add a4, a3, a1
+; CHECK-NEXT: add a5, a2, a4
+; CHECK-NEXT: vl1r.v v11, (a5)
+; CHECK-NEXT: slli a5, a1, 1
+; CHECK-NEXT: add a6, a2, a5
+; CHECK-NEXT: vl1r.v v12, (a6)
+; CHECK-NEXT: add a6, a5, a1
+; CHECK-NEXT: vsetvli a7, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v14, v8, 0
-; CHECK-NEXT: vl1r.v v13, (a5)
+; CHECK-NEXT: add a7, a2, a6
+; CHECK-NEXT: vl1r.v v13, (a7)
; CHECK-NEXT: vmsne.vi v15, v10, 0
; CHECK-NEXT: vl1r.v v8, (a2)
-; CHECK-NEXT: add a1, a1, a0
-; CHECK-NEXT: vl1r.v v9, (a3)
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: vl1r.v v9, (a2)
; CHECK-NEXT: vmsne.vi v16, v12, 0
-; CHECK-NEXT: add a2, a1, a0
-; CHECK-NEXT: add a3, a2, a0
+; CHECK-NEXT: add a3, a0, a3
; CHECK-NEXT: vl1r.v v10, (a3)
; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v11, (a3)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1r.v v11, (a4)
+; CHECK-NEXT: add a5, a0, a5
; CHECK-NEXT: vmsne.vi v9, v10, 0
-; CHECK-NEXT: vl1r.v v10, (a1)
-; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: vl1r.v v11, (a2)
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v15, v14, a1
-; CHECK-NEXT: vslideup.vx v0, v16, a1
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vl1r.v v10, (a5)
+; CHECK-NEXT: add a0, a0, a6
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: vl1r.v v11, (a0)
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v15, v14, a2
+; CHECK-NEXT: vslideup.vx v0, v16, a2
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v8, v10, 0
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v15, a0
+; CHECK-NEXT: srli a1, a1, 1
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v0, v15, a1
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a2
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 12
; CHECK-NEXT: mul a0, a0, a1
@@ -2405,60 +2492,64 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vmv1r.v v18, v25
; ZVBB-NEXT: vmv1r.v v19, v11
; ZVBB-NEXT: vmv1r.v v20, v13
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: li a0, 6
-; ZVBB-NEXT: mul a1, a1, a0
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
-; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg6e8.v v15, (a1)
+; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vsseg6e8.v v15, (a0)
; ZVBB-NEXT: vmv1r.v v15, v22
; ZVBB-NEXT: vmv1r.v v16, v8
; ZVBB-NEXT: vmv1r.v v17, v24
; ZVBB-NEXT: vmv1r.v v18, v10
; ZVBB-NEXT: vmv1r.v v19, v12
-; ZVBB-NEXT: addi a2, sp, 16
+; ZVBB-NEXT: csrr a2, vlenb
+; ZVBB-NEXT: li a1, 6
+; ZVBB-NEXT: mul a2, a2, a1
+; ZVBB-NEXT: add a2, sp, a2
+; ZVBB-NEXT: addi a2, a2, 16
; ZVBB-NEXT: vsseg6e8.v v14, (a2)
-; ZVBB-NEXT: vl1r.v v8, (a1)
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: add a1, a1, a0
-; ZVBB-NEXT: add a3, a2, a0
-; ZVBB-NEXT: vl1r.v v9, (a1)
-; ZVBB-NEXT: add a4, a3, a0
-; ZVBB-NEXT: add a5, a4, a0
-; ZVBB-NEXT: add a6, a5, a0
-; ZVBB-NEXT: vl1r.v v10, (a6)
-; ZVBB-NEXT: add a6, a6, a0
-; ZVBB-NEXT: vl1r.v v11, (a6)
-; ZVBB-NEXT: vl1r.v v12, (a4)
-; ZVBB-NEXT: vsetvli a4, zero, e8, m2, ta, ma
+; ZVBB-NEXT: vl1r.v v8, (a0)
+; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: vl1r.v v9, (a3)
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: add a4, a2, a3
+; ZVBB-NEXT: vl1r.v v10, (a4)
+; ZVBB-NEXT: add a4, a3, a1
+; ZVBB-NEXT: add a5, a2, a4
+; ZVBB-NEXT: vl1r.v v11, (a5)
+; ZVBB-NEXT: slli a5, a1, 1
+; ZVBB-NEXT: add a6, a2, a5
+; ZVBB-NEXT: vl1r.v v12, (a6)
+; ZVBB-NEXT: add a6, a5, a1
+; ZVBB-NEXT: vsetvli a7, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v14, v8, 0
-; ZVBB-NEXT: vl1r.v v13, (a5)
+; ZVBB-NEXT: add a7, a2, a6
+; ZVBB-NEXT: vl1r.v v13, (a7)
; ZVBB-NEXT: vmsne.vi v15, v10, 0
; ZVBB-NEXT: vl1r.v v8, (a2)
-; ZVBB-NEXT: add a1, a1, a0
-; ZVBB-NEXT: vl1r.v v9, (a3)
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: vl1r.v v9, (a2)
; ZVBB-NEXT: vmsne.vi v16, v12, 0
-; ZVBB-NEXT: add a2, a1, a0
-; ZVBB-NEXT: add a3, a2, a0
+; ZVBB-NEXT: add a3, a0, a3
; ZVBB-NEXT: vl1r.v v10, (a3)
; ZVBB-NEXT: vmsne.vi v0, v8, 0
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1r.v v11, (a4)
+; ZVBB-NEXT: add a5, a0, a5
; ZVBB-NEXT: vmsne.vi v9, v10, 0
-; ZVBB-NEXT: vl1r.v v10, (a1)
-; ZVBB-NEXT: srli a1, a0, 2
-; ZVBB-NEXT: vl1r.v v11, (a2)
-; ZVBB-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vx v15, v14, a1
-; ZVBB-NEXT: vslideup.vx v0, v16, a1
-; ZVBB-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; ZVBB-NEXT: vl1r.v v10, (a5)
+; ZVBB-NEXT: add a0, a0, a6
+; ZVBB-NEXT: srli a2, a1, 2
+; ZVBB-NEXT: vl1r.v v11, (a0)
+; ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vx v15, v14, a2
+; ZVBB-NEXT: vslideup.vx v0, v16, a2
+; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v8, v10, 0
-; ZVBB-NEXT: srli a0, a0, 1
-; ZVBB-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v0, v15, a0
+; ZVBB-NEXT: srli a1, a1, 1
+; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v0, v15, a1
; ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v9, a1
+; ZVBB-NEXT: vslideup.vx v8, v9, a2
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: li a1, 12
; ZVBB-NEXT: mul a0, a0, a1
@@ -2489,52 +2580,56 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e8.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e8.v v20, (a1)
-; RV32-NEXT: vl1r.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1r.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1r.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1r.v v13, (a6)
-; RV32-NEXT: vl1r.v v10, (a4)
-; RV32-NEXT: vl1r.v v11, (a5)
-; RV32-NEXT: vl1r.v v8, (a1)
-; RV32-NEXT: vl1r.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e8.v v20, (a2)
+; RV32-NEXT: vl1r.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1r.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1r.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1r.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1r.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1r.v v11, (a7)
+; RV32-NEXT: vl1r.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1r.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1r.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1r.v v19, (a3)
-; RV32-NEXT: vl1r.v v16, (a0)
-; RV32-NEXT: vl1r.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1r.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1r.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1r.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8r.v v16, (a2)
+; RV32-NEXT: vl8r.v v16, (a1)
; RV32-NEXT: vl8r.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -2560,52 +2655,56 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e8.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e8.v v20, (a1)
-; RV64-NEXT: vl1r.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1r.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1r.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1r.v v13, (a6)
-; RV64-NEXT: vl1r.v v10, (a4)
-; RV64-NEXT: vl1r.v v11, (a5)
-; RV64-NEXT: vl1r.v v8, (a1)
-; RV64-NEXT: vl1r.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e8.v v20, (a2)
+; RV64-NEXT: vl1r.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1r.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1r.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1r.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1r.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1r.v v11, (a7)
+; RV64-NEXT: vl1r.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1r.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1r.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1r.v v19, (a3)
-; RV64-NEXT: vl1r.v v16, (a0)
-; RV64-NEXT: vl1r.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1r.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1r.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1r.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8r.v v16, (a2)
+; RV64-NEXT: vl8r.v v16, (a1)
; RV64-NEXT: vl8r.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -2631,52 +2730,56 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e8.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e8.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1r.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1r.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1r.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1r.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1r.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1r.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e8.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1r.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1r.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1r.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1r.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1r.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1r.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1r.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1r.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1r.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1r.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1r.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1r.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1r.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1r.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1r.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8r.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8r.v v16, (a1)
; ZVBB-RV32-NEXT: vl8r.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -2702,52 +2805,56 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e8.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e8.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1r.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1r.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1r.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1r.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1r.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1r.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e8.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1r.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1r.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1r.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1r.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1r.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1r.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1r.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1r.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1r.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1r.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1r.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1r.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1r.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1r.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1r.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8r.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8r.v v16, (a1)
; ZVBB-RV64-NEXT: vl8r.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -2773,52 +2880,56 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e8.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e8.v v20, (a1)
-; ZVZIP-NEXT: vl1r.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1r.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1r.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1r.v v13, (a6)
-; ZVZIP-NEXT: vl1r.v v10, (a4)
-; ZVZIP-NEXT: vl1r.v v11, (a5)
-; ZVZIP-NEXT: vl1r.v v8, (a1)
-; ZVZIP-NEXT: vl1r.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e8.v v20, (a2)
+; ZVZIP-NEXT: vl1r.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1r.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1r.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1r.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1r.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1r.v v11, (a7)
+; ZVZIP-NEXT: vl1r.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1r.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1r.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1r.v v19, (a3)
-; ZVZIP-NEXT: vl1r.v v16, (a0)
-; ZVZIP-NEXT: vl1r.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1r.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1r.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1r.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8r.v v16, (a2)
+; ZVZIP-NEXT: vl8r.v v16, (a1)
; ZVZIP-NEXT: vl8r.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -2841,15 +2952,17 @@ define <vscale x 48 x i8> @vector_interleave_nxv48i8_nxv8i8(<vscale x 8 x i8> %a
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg6e8.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1r.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1r.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1r.v v11, (a2)
; CHECK-NEXT: vl1r.v v8, (a0)
-; CHECK-NEXT: vl1r.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1r.v v12, (a3)
+; CHECK-NEXT: vl1r.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1r.v v12, (a0)
; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: vl1r.v v13, (a1)
; CHECK-NEXT: csrr a0, vlenb
@@ -2870,15 +2983,17 @@ define <vscale x 48 x i8> @vector_interleave_nxv48i8_nxv8i8(<vscale x 8 x i8> %a
; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg6e8.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1r.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1r.v v11, (a2)
; ZVBB-NEXT: vl1r.v v8, (a0)
-; ZVBB-NEXT: vl1r.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1r.v v12, (a3)
+; ZVBB-NEXT: vl1r.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1r.v v12, (a0)
; ZVBB-NEXT: add a1, a3, a1
; ZVBB-NEXT: vl1r.v v13, (a1)
; ZVBB-NEXT: csrr a0, vlenb
@@ -2911,52 +3026,56 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e32.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e32.v v20, (a1)
-; RV32-NEXT: vl1re32.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re32.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re32.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re32.v v13, (a6)
-; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: vl1re32.v v11, (a5)
-; RV32-NEXT: vl1re32.v v8, (a1)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e32.v v20, (a2)
+; RV32-NEXT: vl1re32.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re32.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re32.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re32.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re32.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re32.v v11, (a7)
+; RV32-NEXT: vl1re32.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re32.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re32.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re32.v v19, (a3)
-; RV32-NEXT: vl1re32.v v16, (a0)
-; RV32-NEXT: vl1re32.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re32.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re32.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re32.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re32.v v16, (a2)
+; RV32-NEXT: vl8re32.v v16, (a1)
; RV32-NEXT: vl8re32.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -2982,52 +3101,56 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e32.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e32.v v20, (a1)
-; RV64-NEXT: vl1re32.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re32.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re32.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re32.v v13, (a6)
-; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: vl1re32.v v11, (a5)
-; RV64-NEXT: vl1re32.v v8, (a1)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e32.v v20, (a2)
+; RV64-NEXT: vl1re32.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re32.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re32.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re32.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re32.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re32.v v11, (a7)
+; RV64-NEXT: vl1re32.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re32.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re32.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re32.v v19, (a3)
-; RV64-NEXT: vl1re32.v v16, (a0)
-; RV64-NEXT: vl1re32.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re32.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re32.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re32.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re32.v v16, (a2)
+; RV64-NEXT: vl8re32.v v16, (a1)
; RV64-NEXT: vl8re32.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3053,52 +3176,56 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e32.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e32.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re32.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e32.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re32.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re32.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re32.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re32.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re32.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re32.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re32.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re32.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -3124,52 +3251,56 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e32.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e32.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re32.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e32.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re32.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re32.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re32.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re32.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re32.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re32.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re32.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re32.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3195,52 +3326,56 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e32.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e32.v v20, (a1)
-; ZVZIP-NEXT: vl1re32.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re32.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re32.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re32.v v13, (a6)
-; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: vl1re32.v v11, (a5)
-; ZVZIP-NEXT: vl1re32.v v8, (a1)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e32.v v20, (a2)
+; ZVZIP-NEXT: vl1re32.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re32.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re32.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re32.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re32.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re32.v v11, (a7)
+; ZVZIP-NEXT: vl1re32.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re32.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re32.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re32.v v19, (a3)
-; ZVZIP-NEXT: vl1re32.v v16, (a0)
-; ZVZIP-NEXT: vl1re32.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re32.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re32.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re32.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re32.v v16, (a2)
+; ZVZIP-NEXT: vl8re32.v v16, (a1)
; ZVZIP-NEXT: vl8re32.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3271,52 +3406,56 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e64.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e64.v v20, (a1)
-; RV32-NEXT: vl1re64.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re64.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re64.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re64.v v13, (a6)
-; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: vl1re64.v v11, (a5)
-; RV32-NEXT: vl1re64.v v8, (a1)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e64.v v20, (a2)
+; RV32-NEXT: vl1re64.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re64.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re64.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re64.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re64.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re64.v v11, (a7)
+; RV32-NEXT: vl1re64.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re64.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re64.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re64.v v19, (a3)
-; RV32-NEXT: vl1re64.v v16, (a0)
-; RV32-NEXT: vl1re64.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re64.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re64.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re64.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re64.v v16, (a2)
+; RV32-NEXT: vl8re64.v v16, (a1)
; RV32-NEXT: vl8re64.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -3342,52 +3481,56 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e64.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e64.v v20, (a1)
-; RV64-NEXT: vl1re64.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re64.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re64.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re64.v v13, (a6)
-; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: vl1re64.v v11, (a5)
-; RV64-NEXT: vl1re64.v v8, (a1)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e64.v v20, (a2)
+; RV64-NEXT: vl1re64.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re64.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re64.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re64.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re64.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re64.v v11, (a7)
+; RV64-NEXT: vl1re64.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re64.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re64.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re64.v v19, (a3)
-; RV64-NEXT: vl1re64.v v16, (a0)
-; RV64-NEXT: vl1re64.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re64.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re64.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re64.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re64.v v16, (a2)
+; RV64-NEXT: vl8re64.v v16, (a1)
; RV64-NEXT: vl8re64.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3413,52 +3556,56 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e64.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e64.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re64.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e64.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re64.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re64.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re64.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re64.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re64.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re64.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re64.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re64.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -3483,53 +3630,57 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV64-NEXT: vmv1r.v v23, v13
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e64.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e64.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re64.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e64.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re64.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re64.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re64.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re64.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re64.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re64.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re64.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re64.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3555,52 +3706,56 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e64.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e64.v v20, (a1)
-; ZVZIP-NEXT: vl1re64.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re64.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re64.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re64.v v13, (a6)
-; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: vl1re64.v v11, (a5)
-; ZVZIP-NEXT: vl1re64.v v8, (a1)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e64.v v20, (a2)
+; ZVZIP-NEXT: vl1re64.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re64.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re64.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re64.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re64.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re64.v v11, (a7)
+; ZVZIP-NEXT: vl1re64.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re64.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re64.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re64.v v19, (a3)
-; ZVZIP-NEXT: vl1re64.v v16, (a0)
-; ZVZIP-NEXT: vl1re64.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re64.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re64.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re64.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re64.v v16, (a2)
+; ZVZIP-NEXT: vl8re64.v v16, (a1)
; ZVZIP-NEXT: vl8re64.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3640,53 +3795,58 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: vmv1r.v v24, v18
; CHECK-NEXT: vmv1r.v v25, v10
; CHECK-NEXT: vmerge.vim v26, v30, 1, v0
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a0, a3, 3
+; CHECK-NEXT: sub a3, a0, a3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg7e8.v v20, (a1)
+; CHECK-NEXT: vsseg7e8.v v20, (a3)
; CHECK-NEXT: vmv1r.v v16, v29
; CHECK-NEXT: vmv1r.v v18, v9
; CHECK-NEXT: vmv1r.v v20, v11
; CHECK-NEXT: vmv1r.v v21, v27
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a0, a2, 3
-; CHECK-NEXT: sub a2, a0, a2
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vsseg7e8.v v15, (a2)
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vsseg7e8.v v15, (a1)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: add a3, a1, a0
-; CHECK-NEXT: add a4, a3, a0
+; CHECK-NEXT: slli a2, a0, 1
+; CHECK-NEXT: add a4, a3, a2
; CHECK-NEXT: vl1r.v v8, (a4)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vl1r.v v9, (a4)
-; CHECK-NEXT: vl1r.v v10, (a1)
-; CHECK-NEXT: vl1r.v v11, (a3)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vl1r.v v12, (a4)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vl1r.v v13, (a4)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: add a4, a2, a0
+; CHECK-NEXT: add a5, a3, a4
+; CHECK-NEXT: vl1r.v v9, (a5)
+; CHECK-NEXT: vl1r.v v10, (a3)
+; CHECK-NEXT: add a5, a3, a0
+; CHECK-NEXT: vl1r.v v11, (a5)
+; CHECK-NEXT: slli a5, a0, 2
+; CHECK-NEXT: add a6, a3, a5
+; CHECK-NEXT: vl1r.v v12, (a6)
+; CHECK-NEXT: add a6, a5, a0
+; CHECK-NEXT: add a7, a3, a6
+; CHECK-NEXT: vl1r.v v13, (a7)
+; CHECK-NEXT: add a7, a5, a2
+; CHECK-NEXT: add a3, a3, a7
+; CHECK-NEXT: vsetvli t0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v14, v8, 0
-; CHECK-NEXT: vl1r.v v8, (a4)
-; CHECK-NEXT: add a1, a2, a0
-; CHECK-NEXT: vl1r.v v9, (a2)
+; CHECK-NEXT: vl1r.v v8, (a3)
+; CHECK-NEXT: vl1r.v v9, (a1)
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: add a2, a1, a0
-; CHECK-NEXT: add a3, a2, a0
-; CHECK-NEXT: vl1r.v v10, (a3)
+; CHECK-NEXT: add a4, a1, a4
+; CHECK-NEXT: vl1r.v v10, (a4)
; CHECK-NEXT: vmsne.vi v15, v12, 0
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v11, (a3)
+; CHECK-NEXT: add a5, a1, a5
+; CHECK-NEXT: vl1r.v v11, (a5)
+; CHECK-NEXT: add a3, a1, a0
; CHECK-NEXT: vmsne.vi v16, v8, 0
-; CHECK-NEXT: vl1r.v v12, (a1)
+; CHECK-NEXT: vl1r.v v12, (a3)
+; CHECK-NEXT: add a2, a1, a2
; CHECK-NEXT: vl1r.v v13, (a2)
; CHECK-NEXT: vmsne.vi v9, v10, 0
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v10, (a3)
+; CHECK-NEXT: add a6, a1, a6
+; CHECK-NEXT: vl1r.v v10, (a6)
; CHECK-NEXT: vmsne.vi v8, v12, 0
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v11, (a3)
+; CHECK-NEXT: add a1, a1, a7
+; CHECK-NEXT: vl1r.v v11, (a1)
; CHECK-NEXT: vmsne.vi v12, v10, 0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
@@ -3732,53 +3892,58 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: vmv1r.v v24, v18
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmerge.vim v26, v30, 1, v0
-; ZVBB-NEXT: addi a1, sp, 16
+; ZVBB-NEXT: csrr a3, vlenb
+; ZVBB-NEXT: slli a0, a3, 3
+; ZVBB-NEXT: sub a3, a0, a3
+; ZVBB-NEXT: add a3, sp, a3
+; ZVBB-NEXT: addi a3, a3, 16
; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg7e8.v v20, (a1)
+; ZVBB-NEXT: vsseg7e8.v v20, (a3)
; ZVBB-NEXT: vmv1r.v v16, v29
; ZVBB-NEXT: vmv1r.v v18, v9
; ZVBB-NEXT: vmv1r.v v20, v11
; ZVBB-NEXT: vmv1r.v v21, v27
-; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: slli a0, a2, 3
-; ZVBB-NEXT: sub a2, a0, a2
-; ZVBB-NEXT: add a2, sp, a2
-; ZVBB-NEXT: addi a2, a2, 16
-; ZVBB-NEXT: vsseg7e8.v v15, (a2)
+; ZVBB-NEXT: addi a1, sp, 16
+; ZVBB-NEXT: vsseg7e8.v v15, (a1)
; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: add a3, a1, a0
-; ZVBB-NEXT: add a4, a3, a0
+; ZVBB-NEXT: slli a2, a0, 1
+; ZVBB-NEXT: add a4, a3, a2
; ZVBB-NEXT: vl1r.v v8, (a4)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vl1r.v v9, (a4)
-; ZVBB-NEXT: vl1r.v v10, (a1)
-; ZVBB-NEXT: vl1r.v v11, (a3)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vl1r.v v12, (a4)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vl1r.v v13, (a4)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; ZVBB-NEXT: add a4, a2, a0
+; ZVBB-NEXT: add a5, a3, a4
+; ZVBB-NEXT: vl1r.v v9, (a5)
+; ZVBB-NEXT: vl1r.v v10, (a3)
+; ZVBB-NEXT: add a5, a3, a0
+; ZVBB-NEXT: vl1r.v v11, (a5)
+; ZVBB-NEXT: slli a5, a0, 2
+; ZVBB-NEXT: add a6, a3, a5
+; ZVBB-NEXT: vl1r.v v12, (a6)
+; ZVBB-NEXT: add a6, a5, a0
+; ZVBB-NEXT: add a7, a3, a6
+; ZVBB-NEXT: vl1r.v v13, (a7)
+; ZVBB-NEXT: add a7, a5, a2
+; ZVBB-NEXT: add a3, a3, a7
+; ZVBB-NEXT: vsetvli t0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v14, v8, 0
-; ZVBB-NEXT: vl1r.v v8, (a4)
-; ZVBB-NEXT: add a1, a2, a0
-; ZVBB-NEXT: vl1r.v v9, (a2)
+; ZVBB-NEXT: vl1r.v v8, (a3)
+; ZVBB-NEXT: vl1r.v v9, (a1)
; ZVBB-NEXT: vmsne.vi v0, v10, 0
-; ZVBB-NEXT: add a2, a1, a0
-; ZVBB-NEXT: add a3, a2, a0
-; ZVBB-NEXT: vl1r.v v10, (a3)
+; ZVBB-NEXT: add a4, a1, a4
+; ZVBB-NEXT: vl1r.v v10, (a4)
; ZVBB-NEXT: vmsne.vi v15, v12, 0
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a5, a1, a5
+; ZVBB-NEXT: vl1r.v v11, (a5)
+; ZVBB-NEXT: add a3, a1, a0
; ZVBB-NEXT: vmsne.vi v16, v8, 0
-; ZVBB-NEXT: vl1r.v v12, (a1)
+; ZVBB-NEXT: vl1r.v v12, (a3)
+; ZVBB-NEXT: add a2, a1, a2
; ZVBB-NEXT: vl1r.v v13, (a2)
; ZVBB-NEXT: vmsne.vi v9, v10, 0
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v10, (a3)
+; ZVBB-NEXT: add a6, a1, a6
+; ZVBB-NEXT: vl1r.v v10, (a6)
; ZVBB-NEXT: vmsne.vi v8, v12, 0
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a1, a1, a7
+; ZVBB-NEXT: vl1r.v v11, (a1)
; ZVBB-NEXT: vmsne.vi v12, v10, 0
; ZVBB-NEXT: srli a1, a0, 2
; ZVBB-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
@@ -3824,59 +3989,63 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e8.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e8.v v21, (a2)
+; RV32-NEXT: vsseg7e8.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e8.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1r.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1r.v v11, (a4)
-; RV32-NEXT: vl1r.v v8, (a1)
-; RV32-NEXT: vl1r.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1r.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1r.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1r.v v14, (a4)
-; RV32-NEXT: vl1r.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1r.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1r.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1r.v v11, (a5)
+; RV32-NEXT: vl1r.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1r.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1r.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1r.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1r.v v14, (a2)
+; RV32-NEXT: vl1r.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1r.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1r.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1r.v v16, (a2)
-; RV32-NEXT: vl1r.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1r.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1r.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1r.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1r.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1r.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8r.v v16, (a0)
-; RV32-NEXT: vl8r.v v8, (a2)
+; RV32-NEXT: vl8r.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -3905,59 +4074,63 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e8.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e8.v v21, (a2)
+; RV64-NEXT: vsseg7e8.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e8.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1r.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1r.v v11, (a4)
-; RV64-NEXT: vl1r.v v8, (a1)
-; RV64-NEXT: vl1r.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1r.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1r.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1r.v v14, (a4)
-; RV64-NEXT: vl1r.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1r.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1r.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1r.v v11, (a5)
+; RV64-NEXT: vl1r.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1r.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1r.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1r.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1r.v v14, (a2)
+; RV64-NEXT: vl1r.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1r.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1r.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1r.v v16, (a2)
-; RV64-NEXT: vl1r.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1r.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1r.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1r.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1r.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1r.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8r.v v16, (a0)
-; RV64-NEXT: vl8r.v v8, (a2)
+; RV64-NEXT: vl8r.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -3986,59 +4159,63 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e8.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e8.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e8.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e8.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1r.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1r.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1r.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1r.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1r.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1r.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1r.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1r.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1r.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1r.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1r.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1r.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1r.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1r.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1r.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1r.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1r.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1r.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1r.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1r.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1r.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1r.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1r.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1r.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8r.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8r.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -4067,59 +4244,63 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e8.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e8.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e8.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e8.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1r.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1r.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1r.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1r.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1r.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1r.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1r.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1r.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1r.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1r.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1r.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1r.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1r.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1r.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1r.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1r.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1r.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1r.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1r.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1r.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1r.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1r.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1r.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1r.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8r.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8r.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4148,59 +4329,63 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e8.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e8.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e8.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e8.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1r.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1r.v v11, (a4)
-; ZVZIP-NEXT: vl1r.v v8, (a1)
-; ZVZIP-NEXT: vl1r.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1r.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1r.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1r.v v14, (a4)
-; ZVZIP-NEXT: vl1r.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1r.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1r.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1r.v v11, (a5)
+; ZVZIP-NEXT: vl1r.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1r.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1r.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1r.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1r.v v14, (a2)
+; ZVZIP-NEXT: vl1r.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1r.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1r.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1r.v v16, (a2)
-; ZVZIP-NEXT: vl1r.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1r.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1r.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1r.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1r.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1r.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8r.v v16, (a0)
-; ZVZIP-NEXT: vl8r.v v8, (a2)
+; ZVZIP-NEXT: vl8r.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4235,59 +4420,63 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e16.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e16.v v21, (a2)
+; RV32-NEXT: vsseg7e16.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e16.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v11, (a4)
-; RV32-NEXT: vl1re16.v v8, (a1)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v14, (a4)
-; RV32-NEXT: vl1re16.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re16.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re16.v v11, (a5)
+; RV32-NEXT: vl1re16.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re16.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re16.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re16.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re16.v v14, (a2)
+; RV32-NEXT: vl1re16.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re16.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re16.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re16.v v16, (a2)
-; RV32-NEXT: vl1re16.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re16.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re16.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re16.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re16.v v16, (a0)
-; RV32-NEXT: vl8re16.v v8, (a2)
+; RV32-NEXT: vl8re16.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -4316,59 +4505,63 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e16.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e16.v v21, (a2)
+; RV64-NEXT: vsseg7e16.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e16.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v11, (a4)
-; RV64-NEXT: vl1re16.v v8, (a1)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v14, (a4)
-; RV64-NEXT: vl1re16.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re16.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v19, (a3)
-; RV64-NEXT: vl1re16.v v16, (a2)
-; RV64-NEXT: vl1re16.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re16.v v11, (a5)
+; RV64-NEXT: vl1re16.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re16.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re16.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re16.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re16.v v14, (a2)
+; RV64-NEXT: vl1re16.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re16.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re16.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
+; RV64-NEXT: vl1re16.v v16, (a2)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re16.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re16.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re16.v v21, (a1)
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re16.v v16, (a0)
-; RV64-NEXT: vl8re16.v v8, (a2)
+; RV64-NEXT: vl8re16.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4397,59 +4590,63 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -4478,59 +4675,63 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4559,59 +4760,63 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e16.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e16.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e16.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e16.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v11, (a4)
-; ZVZIP-NEXT: vl1re16.v v8, (a1)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v14, (a4)
-; ZVZIP-NEXT: vl1re16.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re16.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
+; ZVZIP-NEXT: vl1re16.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re16.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re16.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re16.v v14, (a2)
+; ZVZIP-NEXT: vl1re16.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re16.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re16.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re16.v v16, (a2)
-; ZVZIP-NEXT: vl1re16.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re16.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re16.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re16.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re16.v v16, (a0)
-; ZVZIP-NEXT: vl8re16.v v8, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4646,59 +4851,63 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e32.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e32.v v21, (a2)
+; RV32-NEXT: vsseg7e32.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e32.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v11, (a4)
-; RV32-NEXT: vl1re32.v v8, (a1)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v14, (a4)
-; RV32-NEXT: vl1re32.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re32.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re32.v v11, (a5)
+; RV32-NEXT: vl1re32.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re32.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re32.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re32.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re32.v v14, (a2)
+; RV32-NEXT: vl1re32.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re32.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re32.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re32.v v16, (a2)
-; RV32-NEXT: vl1re32.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re32.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re32.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re32.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re32.v v16, (a0)
-; RV32-NEXT: vl8re32.v v8, (a2)
+; RV32-NEXT: vl8re32.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -4727,59 +4936,63 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e32.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e32.v v21, (a2)
+; RV64-NEXT: vsseg7e32.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e32.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v11, (a4)
-; RV64-NEXT: vl1re32.v v8, (a1)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v14, (a4)
-; RV64-NEXT: vl1re32.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re32.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re32.v v11, (a5)
+; RV64-NEXT: vl1re32.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re32.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re32.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re32.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re32.v v14, (a2)
+; RV64-NEXT: vl1re32.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re32.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re32.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re32.v v16, (a2)
-; RV64-NEXT: vl1re32.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re32.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re32.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re32.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re32.v v16, (a0)
-; RV64-NEXT: vl8re32.v v8, (a2)
+; RV64-NEXT: vl8re32.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4808,59 +5021,63 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e32.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e32.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e32.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e32.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re32.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re32.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re32.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re32.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re32.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re32.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re32.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re32.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re32.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -4889,59 +5106,63 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e32.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e32.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e32.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e32.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re32.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re32.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re32.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re32.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re32.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re32.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re32.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re32.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re32.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4970,59 +5191,63 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e32.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e32.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e32.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e32.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v11, (a4)
-; ZVZIP-NEXT: vl1re32.v v8, (a1)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v14, (a4)
-; ZVZIP-NEXT: vl1re32.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re32.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re32.v v11, (a5)
+; ZVZIP-NEXT: vl1re32.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re32.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re32.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re32.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re32.v v14, (a2)
+; ZVZIP-NEXT: vl1re32.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re32.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re32.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re32.v v16, (a2)
-; ZVZIP-NEXT: vl1re32.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re32.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re32.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re32.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re32.v v16, (a0)
-; ZVZIP-NEXT: vl8re32.v v8, (a2)
+; ZVZIP-NEXT: vl8re32.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -5056,59 +5281,63 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e64.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e64.v v21, (a2)
+; RV32-NEXT: vsseg7e64.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e64.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v11, (a4)
-; RV32-NEXT: vl1re64.v v8, (a1)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v14, (a4)
-; RV32-NEXT: vl1re64.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re64.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re64.v v11, (a5)
+; RV32-NEXT: vl1re64.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re64.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re64.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re64.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re64.v v14, (a2)
+; RV32-NEXT: vl1re64.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re64.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re64.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re64.v v16, (a2)
-; RV32-NEXT: vl1re64.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re64.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re64.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re64.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re64.v v16, (a0)
-; RV32-NEXT: vl8re64.v v8, (a2)
+; RV32-NEXT: vl8re64.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -5137,59 +5366,63 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e64.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e64.v v21, (a2)
+; RV64-NEXT: vsseg7e64.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e64.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v11, (a4)
-; RV64-NEXT: vl1re64.v v8, (a1)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v14, (a4)
-; RV64-NEXT: vl1re64.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re64.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re64.v v11, (a5)
+; RV64-NEXT: vl1re64.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re64.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re64.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re64.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re64.v v14, (a2)
+; RV64-NEXT: vl1re64.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re64.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re64.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re64.v v16, (a2)
-; RV64-NEXT: vl1re64.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re64.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re64.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re64.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re64.v v16, (a0)
-; RV64-NEXT: vl8re64.v v8, (a2)
+; RV64-NEXT: vl8re64.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -5218,59 +5451,63 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e64.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e64.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e64.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e64.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re64.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re64.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re64.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re64.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re64.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re64.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re64.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re64.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re64.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -5299,59 +5536,63 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e64.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e64.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e64.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e64.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re64.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re64.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re64.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re64.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re64.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re64.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re64.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re64.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re64.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -5380,59 +5621,63 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e64.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e64.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e64.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e64.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v11, (a4)
-; ZVZIP-NEXT: vl1re64.v v8, (a1)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v14, (a4)
-; ZVZIP-NEXT: vl1re64.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re64.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re64.v v11, (a5)
+; ZVZIP-NEXT: vl1re64.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re64.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re64.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re64.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re64.v v14, (a2)
+; ZVZIP-NEXT: vl1re64.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re64.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re64.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re64.v v16, (a2)
-; ZVZIP-NEXT: vl1re64.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re64.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re64.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re64.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re64.v v16, (a0)
-; ZVZIP-NEXT: vl8re64.v v8, (a2)
+; ZVZIP-NEXT: vl8re64.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -5474,68 +5719,75 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: vmv1r.v v6, v11
; CHECK-NEXT: vmv1r.v v7, v23
; CHECK-NEXT: vmv1r.v v8, v13
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg8e8.v v1, (a1)
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsseg8e8.v v1, (a0)
; CHECK-NEXT: vmv1r.v v17, v24
; CHECK-NEXT: vmv1r.v v19, v28
; CHECK-NEXT: vmv1r.v v21, v10
; CHECK-NEXT: vmv1r.v v23, v12
-; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vsseg8e8.v v16, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: add a3, a1, a0
-; CHECK-NEXT: add a4, a3, a0
-; CHECK-NEXT: vl1r.v v8, (a4)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vl1r.v v9, (a4)
-; CHECK-NEXT: vl1r.v v10, (a1)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vl1r.v v11, (a3)
-; CHECK-NEXT: add a1, a4, a0
-; CHECK-NEXT: add a3, a1, a0
-; CHECK-NEXT: vl1r.v v12, (a3)
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v13, (a3)
-; CHECK-NEXT: add a3, a2, a0
-; CHECK-NEXT: add a5, a3, a0
-; CHECK-NEXT: vl1r.v v14, (a5)
-; CHECK-NEXT: vsetvli a6, zero, e8, m2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a4, a1, 1
+; CHECK-NEXT: add a3, a0, a4
+; CHECK-NEXT: vl1r.v v8, (a3)
+; CHECK-NEXT: add a5, a4, a1
+; CHECK-NEXT: add a3, a0, a5
+; CHECK-NEXT: vl1r.v v9, (a3)
+; CHECK-NEXT: vl1r.v v10, (a0)
+; CHECK-NEXT: add a6, a0, a1
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: vl1r.v v11, (a6)
+; CHECK-NEXT: add a6, a3, a4
+; CHECK-NEXT: add a7, a0, a6
+; CHECK-NEXT: slli t0, a1, 3
+; CHECK-NEXT: vl1r.v v12, (a7)
+; CHECK-NEXT: sub a7, t0, a1
+; CHECK-NEXT: add t0, a0, a7
+; CHECK-NEXT: vl1r.v v13, (t0)
+; CHECK-NEXT: add a4, a2, a4
+; CHECK-NEXT: vl1r.v v14, (a4)
+; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v16, v8, 0
-; CHECK-NEXT: add a5, a5, a0
+; CHECK-NEXT: add a5, a2, a5
; CHECK-NEXT: vl1r.v v15, (a5)
; CHECK-NEXT: vmsne.vi v8, v10, 0
; CHECK-NEXT: vl1r.v v10, (a2)
-; CHECK-NEXT: add a5, a5, a0
-; CHECK-NEXT: vl1r.v v11, (a3)
+; CHECK-NEXT: add a4, a2, a1
+; CHECK-NEXT: vl1r.v v11, (a4)
; CHECK-NEXT: vmsne.vi v9, v12, 0
-; CHECK-NEXT: add a2, a5, a0
-; CHECK-NEXT: add a3, a2, a0
-; CHECK-NEXT: vl1r.v v12, (a3)
+; CHECK-NEXT: add a6, a2, a6
+; CHECK-NEXT: vl1r.v v12, (a6)
; CHECK-NEXT: vmsne.vi v17, v14, 0
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v13, (a3)
+; CHECK-NEXT: add a7, a2, a7
+; CHECK-NEXT: vl1r.v v13, (a7)
+; CHECK-NEXT: add a4, a2, a3
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vl1r.v v10, (a5)
+; CHECK-NEXT: vl1r.v v10, (a4)
+; CHECK-NEXT: add a4, a3, a1
+; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: vl1r.v v11, (a2)
; CHECK-NEXT: vmsne.vi v14, v12, 0
-; CHECK-NEXT: vl1r.v v12, (a4)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vl1r.v v12, (a3)
+; CHECK-NEXT: add a0, a0, a4
; CHECK-NEXT: vmsne.vi v15, v10, 0
-; CHECK-NEXT: vl1r.v v13, (a1)
+; CHECK-NEXT: vl1r.v v13, (a0)
; CHECK-NEXT: vmsne.vi v10, v12, 0
-; CHECK-NEXT: srli a1, a0, 2
+; CHECK-NEXT: srli a0, a1, 2
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v15, v14, a1
-; CHECK-NEXT: vslideup.vx v0, v17, a1
-; CHECK-NEXT: vslideup.vx v10, v9, a1
-; CHECK-NEXT: vslideup.vx v8, v16, a1
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v15, a0
-; CHECK-NEXT: vslideup.vx v8, v10, a0
+; CHECK-NEXT: vslideup.vx v15, v14, a0
+; CHECK-NEXT: vslideup.vx v0, v17, a0
+; CHECK-NEXT: vslideup.vx v10, v9, a0
+; CHECK-NEXT: vslideup.vx v8, v16, a0
+; CHECK-NEXT: srli a1, a1, 1
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v0, v15, a1
+; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
@@ -5573,68 +5825,75 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: vmv1r.v v6, v11
; ZVBB-NEXT: vmv1r.v v7, v23
; ZVBB-NEXT: vmv1r.v v8, v13
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
-; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg8e8.v v1, (a1)
+; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vsseg8e8.v v1, (a0)
; ZVBB-NEXT: vmv1r.v v17, v24
; ZVBB-NEXT: vmv1r.v v19, v28
; ZVBB-NEXT: vmv1r.v v21, v10
; ZVBB-NEXT: vmv1r.v v23, v12
-; ZVBB-NEXT: addi a2, sp, 16
+; ZVBB-NEXT: csrr a2, vlenb
+; ZVBB-NEXT: slli a2, a2, 3
+; ZVBB-NEXT: add a2, sp, a2
+; ZVBB-NEXT: addi a2, a2, 16
; ZVBB-NEXT: vsseg8e8.v v16, (a2)
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: add a3, a1, a0
-; ZVBB-NEXT: add a4, a3, a0
-; ZVBB-NEXT: vl1r.v v8, (a4)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vl1r.v v9, (a4)
-; ZVBB-NEXT: vl1r.v v10, (a1)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vl1r.v v11, (a3)
-; ZVBB-NEXT: add a1, a4, a0
-; ZVBB-NEXT: add a3, a1, a0
-; ZVBB-NEXT: vl1r.v v12, (a3)
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v13, (a3)
-; ZVBB-NEXT: add a3, a2, a0
-; ZVBB-NEXT: add a5, a3, a0
-; ZVBB-NEXT: vl1r.v v14, (a5)
-; ZVBB-NEXT: vsetvli a6, zero, e8, m2, ta, ma
+; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: slli a4, a1, 1
+; ZVBB-NEXT: add a3, a0, a4
+; ZVBB-NEXT: vl1r.v v8, (a3)
+; ZVBB-NEXT: add a5, a4, a1
+; ZVBB-NEXT: add a3, a0, a5
+; ZVBB-NEXT: vl1r.v v9, (a3)
+; ZVBB-NEXT: vl1r.v v10, (a0)
+; ZVBB-NEXT: add a6, a0, a1
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: vl1r.v v11, (a6)
+; ZVBB-NEXT: add a6, a3, a4
+; ZVBB-NEXT: add a7, a0, a6
+; ZVBB-NEXT: slli t0, a1, 3
+; ZVBB-NEXT: vl1r.v v12, (a7)
+; ZVBB-NEXT: sub a7, t0, a1
+; ZVBB-NEXT: add t0, a0, a7
+; ZVBB-NEXT: vl1r.v v13, (t0)
+; ZVBB-NEXT: add a4, a2, a4
+; ZVBB-NEXT: vl1r.v v14, (a4)
+; ZVBB-NEXT: vsetvli a4, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v16, v8, 0
-; ZVBB-NEXT: add a5, a5, a0
+; ZVBB-NEXT: add a5, a2, a5
; ZVBB-NEXT: vl1r.v v15, (a5)
; ZVBB-NEXT: vmsne.vi v8, v10, 0
; ZVBB-NEXT: vl1r.v v10, (a2)
-; ZVBB-NEXT: add a5, a5, a0
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a4, a2, a1
+; ZVBB-NEXT: vl1r.v v11, (a4)
; ZVBB-NEXT: vmsne.vi v9, v12, 0
-; ZVBB-NEXT: add a2, a5, a0
-; ZVBB-NEXT: add a3, a2, a0
-; ZVBB-NEXT: vl1r.v v12, (a3)
+; ZVBB-NEXT: add a6, a2, a6
+; ZVBB-NEXT: vl1r.v v12, (a6)
; ZVBB-NEXT: vmsne.vi v17, v14, 0
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v13, (a3)
+; ZVBB-NEXT: add a7, a2, a7
+; ZVBB-NEXT: vl1r.v v13, (a7)
+; ZVBB-NEXT: add a4, a2, a3
; ZVBB-NEXT: vmsne.vi v0, v10, 0
-; ZVBB-NEXT: vl1r.v v10, (a5)
+; ZVBB-NEXT: vl1r.v v10, (a4)
+; ZVBB-NEXT: add a4, a3, a1
+; ZVBB-NEXT: add a2, a2, a4
; ZVBB-NEXT: vl1r.v v11, (a2)
; ZVBB-NEXT: vmsne.vi v14, v12, 0
-; ZVBB-NEXT: vl1r.v v12, (a4)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1r.v v12, (a3)
+; ZVBB-NEXT: add a0, a0, a4
; ZVBB-NEXT: vmsne.vi v15, v10, 0
-; ZVBB-NEXT: vl1r.v v13, (a1)
+; ZVBB-NEXT: vl1r.v v13, (a0)
; ZVBB-NEXT: vmsne.vi v10, v12, 0
-; ZVBB-NEXT: srli a1, a0, 2
+; ZVBB-NEXT: srli a0, a1, 2
; ZVBB-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vx v15, v14, a1
-; ZVBB-NEXT: vslideup.vx v0, v17, a1
-; ZVBB-NEXT: vslideup.vx v10, v9, a1
-; ZVBB-NEXT: vslideup.vx v8, v16, a1
-; ZVBB-NEXT: srli a0, a0, 1
-; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v0, v15, a0
-; ZVBB-NEXT: vslideup.vx v8, v10, a0
+; ZVBB-NEXT: vslideup.vx v15, v14, a0
+; ZVBB-NEXT: vslideup.vx v0, v17, a0
+; ZVBB-NEXT: vslideup.vx v10, v9, a0
+; ZVBB-NEXT: vslideup.vx v8, v16, a0
+; ZVBB-NEXT: srli a1, a1, 1
+; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v0, v15, a1
+; ZVBB-NEXT: vslideup.vx v8, v10, a1
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -5666,48 +5925,55 @@ define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv16i8(<vscale x 16 x i8
; CHECK-NEXT: vmv1r.v v6, v19
; CHECK-NEXT: vmv1r.v v7, v31
; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vsseg8e8.v v1, (a1)
; CHECK-NEXT: vmv1r.v v25, v10
; CHECK-NEXT: vmv1r.v v27, v14
; CHECK-NEXT: vmv1r.v v29, v18
; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsseg8e8.v v24, (a0)
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1r.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1r.v v23, (t0)
-; CHECK-NEXT: vl1r.v v20, (a6)
-; CHECK-NEXT: vl1r.v v21, (a7)
+; CHECK-NEXT: slli a3, a2, 1
+; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl1r.v v18, (a4)
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a5, a1, a4
; CHECK-NEXT: vl1r.v v19, (a5)
; CHECK-NEXT: vl1r.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1r.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1r.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1r.v v15, (a2)
-; CHECK-NEXT: vl1r.v v12, (a3)
-; CHECK-NEXT: vl1r.v v13, (a6)
-; CHECK-NEXT: vl1r.v v10, (a4)
-; CHECK-NEXT: vl1r.v v11, (a5)
+; CHECK-NEXT: add a5, a1, a2
+; CHECK-NEXT: vl1r.v v17, (a5)
+; CHECK-NEXT: slli a5, a2, 2
+; CHECK-NEXT: add a6, a5, a3
+; CHECK-NEXT: add a7, a1, a6
+; CHECK-NEXT: vl1r.v v22, (a7)
+; CHECK-NEXT: slli a7, a2, 3
+; CHECK-NEXT: sub a7, a7, a2
+; CHECK-NEXT: add t0, a1, a7
+; CHECK-NEXT: vl1r.v v23, (t0)
+; CHECK-NEXT: add t0, a1, a5
+; CHECK-NEXT: vl1r.v v20, (t0)
+; CHECK-NEXT: add t0, a5, a2
+; CHECK-NEXT: add a1, a1, t0
+; CHECK-NEXT: vl1r.v v21, (a1)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vl1r.v v10, (a3)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1r.v v11, (a4)
; CHECK-NEXT: vl1r.v v8, (a0)
-; CHECK-NEXT: vl1r.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl1r.v v9, (a2)
+; CHECK-NEXT: add a6, a0, a6
+; CHECK-NEXT: vl1r.v v14, (a6)
+; CHECK-NEXT: add a7, a0, a7
+; CHECK-NEXT: vl1r.v v15, (a7)
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vl1r.v v12, (a5)
+; CHECK-NEXT: add a0, a0, t0
+; CHECK-NEXT: vl1r.v v13, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
@@ -5733,48 +5999,55 @@ define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv16i8(<vscale x 16 x i8
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e8.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e8.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1r.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1r.v v23, (t0)
-; ZVBB-NEXT: vl1r.v v20, (a6)
-; ZVBB-NEXT: vl1r.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1r.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1r.v v19, (a5)
; ZVBB-NEXT: vl1r.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1r.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1r.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1r.v v15, (a2)
-; ZVBB-NEXT: vl1r.v v12, (a3)
-; ZVBB-NEXT: vl1r.v v13, (a6)
-; ZVBB-NEXT: vl1r.v v10, (a4)
-; ZVBB-NEXT: vl1r.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1r.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1r.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1r.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1r.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1r.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1r.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1r.v v11, (a4)
; ZVBB-NEXT: vl1r.v v8, (a0)
-; ZVBB-NEXT: vl1r.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1r.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1r.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1r.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1r.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1r.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -5806,48 +6079,55 @@ define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv8i16(<vscale x 8 x i16
; CHECK-NEXT: vmv1r.v v6, v19
; CHECK-NEXT: vmv1r.v v7, v31
; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vsseg8e16.v v1, (a1)
; CHECK-NEXT: vmv1r.v v25, v10
; CHECK-NEXT: vmv1r.v v27, v14
; CHECK-NEXT: vmv1r.v v29, v18
; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsseg8e16.v v24, (a0)
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re16.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re16.v v23, (t0)
-; CHECK-NEXT: vl1re16.v v20, (a6)
-; CHECK-NEXT: vl1re16.v v21, (a7)
+; CHECK-NEXT: slli a3, a2, 1
+; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl1re16.v v18, (a4)
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a5, a1, a4
; CHECK-NEXT: vl1re16.v v19, (a5)
; CHECK-NEXT: vl1re16.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re16.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re16.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re16.v v15, (a2)
-; CHECK-NEXT: vl1re16.v v12, (a3)
-; CHECK-NEXT: vl1re16.v v13, (a6)
-; CHECK-NEXT: vl1re16.v v10, (a4)
-; CHECK-NEXT: vl1re16.v v11, (a5)
+; CHECK-NEXT: add a5, a1, a2
+; CHECK-NEXT: vl1re16.v v17, (a5)
+; CHECK-NEXT: slli a5, a2, 2
+; CHECK-NEXT: add a6, a5, a3
+; CHECK-NEXT: add a7, a1, a6
+; CHECK-NEXT: vl1re16.v v22, (a7)
+; CHECK-NEXT: slli a7, a2, 3
+; CHECK-NEXT: sub a7, a7, a2
+; CHECK-NEXT: add t0, a1, a7
+; CHECK-NEXT: vl1re16.v v23, (t0)
+; CHECK-NEXT: add t0, a1, a5
+; CHECK-NEXT: vl1re16.v v20, (t0)
+; CHECK-NEXT: add t0, a5, a2
+; CHECK-NEXT: add a1, a1, t0
+; CHECK-NEXT: vl1re16.v v21, (a1)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vl1re16.v v10, (a3)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1re16.v v11, (a4)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl1re16.v v9, (a2)
+; CHECK-NEXT: add a6, a0, a6
+; CHECK-NEXT: vl1re16.v v14, (a6)
+; CHECK-NEXT: add a7, a0, a7
+; CHECK-NEXT: vl1re16.v v15, (a7)
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vl1re16.v v12, (a5)
+; CHECK-NEXT: add a0, a0, t0
+; CHECK-NEXT: vl1re16.v v13, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
@@ -5873,48 +6153,55 @@ define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv8i16(<vscale x 8 x i16
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e16.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e16.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re16.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re16.v v23, (t0)
-; ZVBB-NEXT: vl1re16.v v20, (a6)
-; ZVBB-NEXT: vl1re16.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re16.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re16.v v19, (a5)
; ZVBB-NEXT: vl1re16.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re16.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re16.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re16.v v15, (a2)
-; ZVBB-NEXT: vl1re16.v v12, (a3)
-; ZVBB-NEXT: vl1re16.v v13, (a6)
-; ZVBB-NEXT: vl1re16.v v10, (a4)
-; ZVBB-NEXT: vl1re16.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re16.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re16.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re16.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re16.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re16.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re16.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re16.v v11, (a4)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re16.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re16.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re16.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re16.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -5946,48 +6233,55 @@ define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv4i32(<vscale x 4 x i32
; CHECK-NEXT: vmv1r.v v6, v19
; CHECK-NEXT: vmv1r.v v7, v31
; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vsseg8e32.v v1, (a1)
; CHECK-NEXT: vmv1r.v v25, v10
; CHECK-NEXT: vmv1r.v v27, v14
; CHECK-NEXT: vmv1r.v v29, v18
; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsseg8e32.v v24, (a0)
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re32.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re32.v v23, (t0)
-; CHECK-NEXT: vl1re32.v v20, (a6)
-; CHECK-NEXT: vl1re32.v v21, (a7)
+; CHECK-NEXT: slli a3, a2, 1
+; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl1re32.v v18, (a4)
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a5, a1, a4
; CHECK-NEXT: vl1re32.v v19, (a5)
; CHECK-NEXT: vl1re32.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re32.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re32.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re32.v v15, (a2)
-; CHECK-NEXT: vl1re32.v v12, (a3)
-; CHECK-NEXT: vl1re32.v v13, (a6)
-; CHECK-NEXT: vl1re32.v v10, (a4)
-; CHECK-NEXT: vl1re32.v v11, (a5)
+; CHECK-NEXT: add a5, a1, a2
+; CHECK-NEXT: vl1re32.v v17, (a5)
+; CHECK-NEXT: slli a5, a2, 2
+; CHECK-NEXT: add a6, a5, a3
+; CHECK-NEXT: add a7, a1, a6
+; CHECK-NEXT: vl1re32.v v22, (a7)
+; CHECK-NEXT: slli a7, a2, 3
+; CHECK-NEXT: sub a7, a7, a2
+; CHECK-NEXT: add t0, a1, a7
+; CHECK-NEXT: vl1re32.v v23, (t0)
+; CHECK-NEXT: add t0, a1, a5
+; CHECK-NEXT: vl1re32.v v20, (t0)
+; CHECK-NEXT: add t0, a5, a2
+; CHECK-NEXT: add a1, a1, t0
+; CHECK-NEXT: vl1re32.v v21, (a1)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vl1re32.v v10, (a3)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1re32.v v11, (a4)
; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl1re32.v v9, (a2)
+; CHECK-NEXT: add a6, a0, a6
+; CHECK-NEXT: vl1re32.v v14, (a6)
+; CHECK-NEXT: add a7, a0, a7
+; CHECK-NEXT: vl1re32.v v15, (a7)
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vl1re32.v v12, (a5)
+; CHECK-NEXT: add a0, a0, t0
+; CHECK-NEXT: vl1re32.v v13, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
@@ -6013,48 +6307,55 @@ define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv4i32(<vscale x 4 x i32
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e32.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e32.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re32.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re32.v v23, (t0)
-; ZVBB-NEXT: vl1re32.v v20, (a6)
-; ZVBB-NEXT: vl1re32.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re32.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re32.v v19, (a5)
; ZVBB-NEXT: vl1re32.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re32.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re32.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re32.v v15, (a2)
-; ZVBB-NEXT: vl1re32.v v12, (a3)
-; ZVBB-NEXT: vl1re32.v v13, (a6)
-; ZVBB-NEXT: vl1re32.v v10, (a4)
-; ZVBB-NEXT: vl1re32.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re32.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re32.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re32.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re32.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re32.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re32.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re32.v v11, (a4)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re32.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re32.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re32.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re32.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re32.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -6085,48 +6386,55 @@ define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv2i64(<vscale x 2 x i64
; CHECK-NEXT: vmv1r.v v6, v19
; CHECK-NEXT: vmv1r.v v7, v31
; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vsseg8e64.v v1, (a1)
; CHECK-NEXT: vmv1r.v v25, v10
; CHECK-NEXT: vmv1r.v v27, v14
; CHECK-NEXT: vmv1r.v v29, v18
; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsseg8e64.v v24, (a0)
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re64.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re64.v v23, (t0)
-; CHECK-NEXT: vl1re64.v v20, (a6)
-; CHECK-NEXT: vl1re64.v v21, (a7)
+; CHECK-NEXT: slli a3, a2, 1
+; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl1re64.v v18, (a4)
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a5, a1, a4
; CHECK-NEXT: vl1re64.v v19, (a5)
; CHECK-NEXT: vl1re64.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re64.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re64.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re64.v v15, (a2)
-; CHECK-NEXT: vl1re64.v v12, (a3)
-; CHECK-NEXT: vl1re64.v v13, (a6)
-; CHECK-NEXT: vl1re64.v v10, (a4)
-; CHECK-NEXT: vl1re64.v v11, (a5)
+; CHECK-NEXT: add a5, a1, a2
+; CHECK-NEXT: vl1re64.v v17, (a5)
+; CHECK-NEXT: slli a5, a2, 2
+; CHECK-NEXT: add a6, a5, a3
+; CHECK-NEXT: add a7, a1, a6
+; CHECK-NEXT: vl1re64.v v22, (a7)
+; CHECK-NEXT: slli a7, a2, 3
+; CHECK-NEXT: sub a7, a7, a2
+; CHECK-NEXT: add t0, a1, a7
+; CHECK-NEXT: vl1re64.v v23, (t0)
+; CHECK-NEXT: add t0, a1, a5
+; CHECK-NEXT: vl1re64.v v20, (t0)
+; CHECK-NEXT: add t0, a5, a2
+; CHECK-NEXT: add a1, a1, t0
+; CHECK-NEXT: vl1re64.v v21, (a1)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vl1re64.v v10, (a3)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1re64.v v11, (a4)
; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl1re64.v v9, (a2)
+; CHECK-NEXT: add a6, a0, a6
+; CHECK-NEXT: vl1re64.v v14, (a6)
+; CHECK-NEXT: add a7, a0, a7
+; CHECK-NEXT: vl1re64.v v15, (a7)
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vl1re64.v v12, (a5)
+; CHECK-NEXT: add a0, a0, t0
+; CHECK-NEXT: vl1re64.v v13, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
@@ -6150,50 +6458,57 @@ define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv2i64(<vscale x 2 x i64
; ZVBB-NEXT: vmv1r.v v4, v15
; ZVBB-NEXT: vmv1r.v v5, v29
; ZVBB-NEXT: vmv1r.v v6, v19
-; ZVBB-NEXT: vmv1r.v v7, v31
-; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: vmv1r.v v7, v31
+; ZVBB-NEXT: vmv1r.v v8, v23
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e64.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e64.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re64.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re64.v v23, (t0)
-; ZVBB-NEXT: vl1re64.v v20, (a6)
-; ZVBB-NEXT: vl1re64.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re64.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re64.v v19, (a5)
; ZVBB-NEXT: vl1re64.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re64.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re64.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re64.v v15, (a2)
-; ZVBB-NEXT: vl1re64.v v12, (a3)
-; ZVBB-NEXT: vl1re64.v v13, (a6)
-; ZVBB-NEXT: vl1re64.v v10, (a4)
-; ZVBB-NEXT: vl1re64.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re64.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re64.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re64.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re64.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re64.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re64.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re64.v v11, (a4)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re64.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re64.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re64.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re64.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re64.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -6213,9 +6528,11 @@ define <vscale x 4 x bfloat> @vector_interleave_nxv4bf16_nxv2bf16(<vscale x 2 x
; V-NEXT: li a0, -1
; V-NEXT: vwmaccu.vx v10, a0, v9
; V-NEXT: csrr a0, vlenb
+; V-NEXT: srli a1, a0, 3
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; V-NEXT: vslidedown.vx v8, v10, a1
; V-NEXT: srli a0, a0, 2
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; V-NEXT: vslidedown.vx v8, v10, a0
; V-NEXT: vslideup.vx v10, v8, a0
; V-NEXT: vmv.v.v v8, v10
; V-NEXT: ret
@@ -6226,9 +6543,11 @@ define <vscale x 4 x bfloat> @vector_interleave_nxv4bf16_nxv2bf16(<vscale x 2 x
; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: srli a1, a0, 3
+; ZVBB-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslidedown.vx v8, v10, a1
; ZVBB-NEXT: srli a0, a0, 2
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslidedown.vx v8, v10, a0
; ZVBB-NEXT: vslideup.vx v10, v8, a0
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
@@ -6287,9 +6606,11 @@ define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half
; V-NEXT: li a0, -1
; V-NEXT: vwmaccu.vx v10, a0, v9
; V-NEXT: csrr a0, vlenb
+; V-NEXT: srli a1, a0, 3
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; V-NEXT: vslidedown.vx v8, v10, a1
; V-NEXT: srli a0, a0, 2
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; V-NEXT: vslidedown.vx v8, v10, a0
; V-NEXT: vslideup.vx v10, v8, a0
; V-NEXT: vmv.v.v v8, v10
; V-NEXT: ret
@@ -6300,9 +6621,11 @@ define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half
; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: srli a1, a0, 3
+; ZVBB-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslidedown.vx v8, v10, a1
; ZVBB-NEXT: srli a0, a0, 2
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslidedown.vx v8, v10, a0
; ZVBB-NEXT: vslideup.vx v10, v8, a0
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
@@ -6699,15 +7022,15 @@ define <vscale x 6 x half> @vector_interleave_nxv6f16_nxv2f16(<vscale x 2 x half
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: vle16.v v9, (a3)
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v9, a1
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: vle16.v v9, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
@@ -6725,15 +7048,15 @@ define <vscale x 6 x half> @vector_interleave_nxv6f16_nxv2f16(<vscale x 2 x half
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: vle16.v v9, (a3)
-; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v9, a1
-; ZVBB-NEXT: add a2, a3, a2
-; ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: add a2, a0, a2
; ZVBB-NEXT: vle16.v v9, (a2)
+; ZVBB-NEXT: vle16.v v8, (a0)
+; ZVBB-NEXT: srli a2, a1, 2
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v9, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v9, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
@@ -6756,8 +7079,9 @@ define <vscale x 12 x half> @vector_interleave_nxv12f16_nxv4f16(<vscale x 4 x ha
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: vl1re16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl1re16.v v9, (a0)
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vl1re16.v v9, (a2)
+; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl1re16.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -6779,8 +7103,9 @@ define <vscale x 12 x half> @vector_interleave_nxv12f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: vl1re16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl1re16.v v9, (a0)
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl1re16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -6806,9 +7131,10 @@ define <vscale x 24 x half> @vector_interleave_nxv24f16_nxv8f16(<vscale x 8 x ha
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: vl2re16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re16.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re16.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re16.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -6830,9 +7156,10 @@ define <vscale x 24 x half> @vector_interleave_nxv24f16_nxv8f16(<vscale x 8 x ha
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: vl2re16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re16.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re16.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re16.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -6857,15 +7184,15 @@ define <vscale x 6 x bfloat> @vector_interleave_nxv6bf16_nxv2bf16(<vscale x 2 x
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: vle16.v v9, (a3)
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v9, a1
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: vle16.v v9, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
@@ -6883,15 +7210,15 @@ define <vscale x 6 x bfloat> @vector_interleave_nxv6bf16_nxv2bf16(<vscale x 2 x
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: vle16.v v9, (a3)
-; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v9, a1
-; ZVBB-NEXT: add a2, a3, a2
-; ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: add a2, a0, a2
; ZVBB-NEXT: vle16.v v9, (a2)
+; ZVBB-NEXT: vle16.v v8, (a0)
+; ZVBB-NEXT: srli a2, a1, 2
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v9, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v9, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
@@ -6914,8 +7241,9 @@ define <vscale x 12 x bfloat> @vector_interleave_nxv12bf16_nxv4bf16(<vscale x 4
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: vl1re16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl1re16.v v9, (a0)
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vl1re16.v v9, (a2)
+; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl1re16.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -6937,8 +7265,9 @@ define <vscale x 12 x bfloat> @vector_interleave_nxv12bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: vl1re16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl1re16.v v9, (a0)
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl1re16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -6964,9 +7293,10 @@ define <vscale x 24 x bfloat> @vector_interleave_nxv24bf16_nxv8bf16(<vscale x 8
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: vl2re16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re16.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re16.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re16.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -6988,9 +7318,10 @@ define <vscale x 24 x bfloat> @vector_interleave_nxv24bf16_nxv8bf16(<vscale x 8
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: vl2re16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re16.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re16.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re16.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7015,15 +7346,15 @@ define <vscale x 3 x float> @vector_interleave_nxv3f32_nxv1f32(<vscale x 1 x flo
; CHECK-NEXT: vsseg3e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: vle32.v v9, (a3)
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: srli a1, a1, 3
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v9, a1
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: vle32.v v9, (a2)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: srli a2, a1, 3
+; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
@@ -7041,15 +7372,15 @@ define <vscale x 3 x float> @vector_interleave_nxv3f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: vle32.v v9, (a3)
-; ZVBB-NEXT: vle32.v v8, (a0)
-; ZVBB-NEXT: srli a1, a1, 3
-; ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v9, a1
-; ZVBB-NEXT: add a2, a3, a2
-; ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: add a2, a0, a2
; ZVBB-NEXT: vle32.v v9, (a2)
+; ZVBB-NEXT: vle32.v v8, (a0)
+; ZVBB-NEXT: srli a2, a1, 3
+; ZVBB-NEXT: vsetvli a3, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v9, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v9, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
@@ -7072,8 +7403,9 @@ define <vscale x 6 x float> @vector_interleave_nxv6f32_nxv2f32(<vscale x 2 x flo
; CHECK-NEXT: vsseg3e32.v v8, (a0)
; CHECK-NEXT: vl1re32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl1re32.v v9, (a0)
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vl1re32.v v9, (a2)
+; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl1re32.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7095,8 +7427,9 @@ define <vscale x 6 x float> @vector_interleave_nxv6f32_nxv2f32(<vscale x 2 x flo
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
; ZVBB-NEXT: vl1re32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl1re32.v v9, (a0)
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: vl1re32.v v9, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl1re32.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7122,9 +7455,10 @@ define <vscale x 12 x float> @vector_interleave_nxv12f32_nxv4f32(<vscale x 4 x f
; CHECK-NEXT: vsseg3e32.v v8, (a0)
; CHECK-NEXT: vl2re32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re32.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re32.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re32.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7146,9 +7480,10 @@ define <vscale x 12 x float> @vector_interleave_nxv12f32_nxv4f32(<vscale x 4 x f
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
; ZVBB-NEXT: vl2re32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re32.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re32.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re32.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7174,8 +7509,9 @@ define <vscale x 3 x double> @vector_interleave_nxv3f64_nxv1f64(<vscale x 1 x do
; CHECK-NEXT: vsseg3e64.v v8, (a0)
; CHECK-NEXT: vl1re64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl1re64.v v9, (a0)
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vl1re64.v v9, (a2)
+; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl1re64.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7197,8 +7533,9 @@ define <vscale x 3 x double> @vector_interleave_nxv3f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsseg3e64.v v8, (a0)
; ZVBB-NEXT: vl1re64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl1re64.v v9, (a0)
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: vl1re64.v v9, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl1re64.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7224,9 +7561,10 @@ define <vscale x 6 x double> @vector_interleave_nxv6f64_nxv2f64(<vscale x 2 x do
; CHECK-NEXT: vsseg3e64.v v8, (a0)
; CHECK-NEXT: vl2re64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re64.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re64.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re64.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7248,9 +7586,10 @@ define <vscale x 6 x double> @vector_interleave_nxv6f64_nxv2f64(<vscale x 2 x do
; ZVBB-NEXT: vsseg3e64.v v8, (a0)
; ZVBB-NEXT: vl2re64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re64.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re64.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re64.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7275,12 +7614,12 @@ define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv2f16(<vscale x 2 x half
; CHECK-NEXT: vsseg4e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: add a3, a0, a1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a2, a4, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v10, (a3)
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: vle16.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v10, (a2)
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v8, a1
@@ -7305,12 +7644,12 @@ define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv2f16(<vscale x 2 x half
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a2, a4, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v10, (a2)
; ZVBB-NEXT: srli a1, a1, 2
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
@@ -7338,13 +7677,14 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv4f16(<vscale x 4 x ha
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg4e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a1)
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: add a2, a1, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
+; CHECK-NEXT: vl1re16.v v9, (a1)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add sp, sp, a0
@@ -7361,13 +7701,14 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a1)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: vl1re16.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -7388,14 +7729,16 @@ define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv8f16(<vscale x 8 x ha
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vsseg4e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 2
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl2re16.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re16.v v14, (a1)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re16.v v14, (a2)
; CHECK-NEXT: vl2re16.v v8, (a0)
-; CHECK-NEXT: vl2re16.v v10, (a2)
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl2re16.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -7412,14 +7755,16 @@ define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv8f16(<vscale x 8 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re16.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re16.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re16.v v14, (a2)
; ZVBB-NEXT: vl2re16.v v8, (a0)
-; ZVBB-NEXT: vl2re16.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -7441,12 +7786,12 @@ define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv2bf16(<vscale x 2 x
; CHECK-NEXT: vsseg4e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: add a3, a0, a1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a2, a4, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v10, (a3)
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: vle16.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v10, (a2)
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v8, a1
@@ -7471,12 +7816,12 @@ define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv2bf16(<vscale x 2 x
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a2, a4, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v10, (a2)
; ZVBB-NEXT: srli a1, a1, 2
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
@@ -7504,13 +7849,14 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv4bf16(<vscale x 4
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg4e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a1)
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: add a2, a1, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
+; CHECK-NEXT: vl1re16.v v9, (a1)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add sp, sp, a0
@@ -7527,13 +7873,14 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a1)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: vl1re16.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -7554,14 +7901,16 @@ define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv8bf16(<vscale x 8
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vsseg4e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 2
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl2re16.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re16.v v14, (a1)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re16.v v14, (a2)
; CHECK-NEXT: vl2re16.v v8, (a0)
-; CHECK-NEXT: vl2re16.v v10, (a2)
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl2re16.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -7578,14 +7927,16 @@ define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv8bf16(<vscale x 8
; ZVBB-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re16.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re16.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re16.v v14, (a2)
; ZVBB-NEXT: vl2re16.v v8, (a0)
-; ZVBB-NEXT: vl2re16.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -7607,12 +7958,12 @@ define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv1f32(<vscale x 1 x flo
; CHECK-NEXT: vsseg4e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: add a3, a0, a1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a2, a4, a2
-; CHECK-NEXT: vle32.v v8, (a2)
-; CHECK-NEXT: vle32.v v9, (a4)
-; CHECK-NEXT: vle32.v v10, (a3)
+; CHECK-NEXT: vle32.v v8, (a4)
+; CHECK-NEXT: vle32.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle32.v v10, (a2)
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v8, a1
@@ -7637,12 +7988,12 @@ define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a2, a4, a2
-; ZVBB-NEXT: vle32.v v8, (a2)
-; ZVBB-NEXT: vle32.v v9, (a4)
-; ZVBB-NEXT: vle32.v v10, (a3)
+; ZVBB-NEXT: vle32.v v8, (a4)
+; ZVBB-NEXT: vle32.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle32.v v10, (a2)
; ZVBB-NEXT: srli a1, a1, 3
; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
@@ -7670,13 +8021,14 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv2f32(<vscale x 2 x flo
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vsseg4e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re32.v v10, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re32.v v11, (a1)
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: add a2, a1, a2
+; CHECK-NEXT: vl1re32.v v11, (a2)
; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a2)
+; CHECK-NEXT: vl1re32.v v9, (a1)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add sp, sp, a0
@@ -7693,13 +8045,14 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv2f32(<vscale x 2 x flo
; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re32.v v10, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re32.v v11, (a1)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re32.v v11, (a2)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a2)
+; ZVBB-NEXT: vl1re32.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -7720,14 +8073,16 @@ define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv4f32(<vscale x 4 x f
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT: vsseg4e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 2
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl2re32.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re32.v v14, (a1)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re32.v v14, (a2)
; CHECK-NEXT: vl2re32.v v8, (a0)
-; CHECK-NEXT: vl2re32.v v10, (a2)
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl2re32.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -7744,14 +8099,16 @@ define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv4f32(<vscale x 4 x f
; ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re32.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re32.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re32.v v14, (a2)
; ZVBB-NEXT: vl2re32.v v8, (a0)
-; ZVBB-NEXT: vl2re32.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re32.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -7772,13 +8129,14 @@ define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv1f64(<vscale x 1 x do
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vsseg4e64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re64.v v10, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re64.v v11, (a1)
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: add a2, a1, a2
+; CHECK-NEXT: vl1re64.v v11, (a2)
; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a2)
+; CHECK-NEXT: vl1re64.v v9, (a1)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add sp, sp, a0
@@ -7795,13 +8153,14 @@ define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; ZVBB-NEXT: vsseg4e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re64.v v10, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re64.v v11, (a1)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re64.v v11, (a2)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a2)
+; ZVBB-NEXT: vl1re64.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -7822,14 +8181,16 @@ define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv2f64(<vscale x 2 x do
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-NEXT: vsseg4e64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 2
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl2re64.v v12, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl2re64.v v14, (a1)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re64.v v14, (a2)
; CHECK-NEXT: vl2re64.v v8, (a0)
-; CHECK-NEXT: vl2re64.v v10, (a2)
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl2re64.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -7846,14 +8207,16 @@ define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv2f64(<vscale x 2 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; ZVBB-NEXT: vsseg4e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re64.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re64.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re64.v v14, (a2)
; ZVBB-NEXT: vl2re64.v v8, (a0)
-; ZVBB-NEXT: vl2re64.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re64.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -7876,22 +8239,23 @@ define <vscale x 10 x half> @vector_interleave_nxv10f16_nxv2f16(<vscale x 2 x ha
; CHECK-NEXT: vsseg5e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: add a3, a0, a1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v10, (a3)
-; CHECK-NEXT: srli a1, a1, 2
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: vle16.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a2
; CHECK-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v10, a1
-; CHECK-NEXT: add a2, a5, a2
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a0, a1, a0
@@ -7911,22 +8275,23 @@ define <vscale x 10 x half> @vector_interleave_nxv10f16_nxv2f16(<vscale x 2 x ha
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v10, (a3)
-; ZVBB-NEXT: srli a1, a1, 2
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v10, (a2)
+; ZVBB-NEXT: srli a2, a1, 2
; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
+; ZVBB-NEXT: vslideup.vx v9, v8, a2
; ZVBB-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v10, a1
-; ZVBB-NEXT: add a2, a5, a2
-; ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v10, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 1
; ZVBB-NEXT: add a0, a1, a0
@@ -7949,15 +8314,17 @@ define <vscale x 20 x half> @vector_interleave_nxv20f16_nxv4f16(<vscale x 4 x ha
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg5e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a1)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
; CHECK-NEXT: add a0, a1, a0
@@ -7976,15 +8343,17 @@ define <vscale x 20 x half> @vector_interleave_nxv20f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a1)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
; ZVBB-NEXT: add a0, a1, a0
@@ -8016,35 +8385,38 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e16.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e16.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re16.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re16.v v11, (a5)
; RV32-NEXT: vl1re16.v v8, (a0)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re16.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re16.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re16.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re16.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re16.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re16.v v12, (a0)
; RV32-NEXT: vl1re16.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re16.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re16.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -8082,35 +8454,38 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e16.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e16.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re16.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re16.v v11, (a5)
; RV64-NEXT: vl1re16.v v8, (a0)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re16.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re16.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re16.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re16.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re16.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re16.v v12, (a0)
; RV64-NEXT: vl1re16.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re16.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re16.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -8148,35 +8523,38 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e16.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e16.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re16.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re16.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re16.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -8214,35 +8592,38 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e16.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e16.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re16.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re16.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re16.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -8280,35 +8661,38 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e16.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e16.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re16.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
; ZVZIP-NEXT: vl1re16.v v8, (a0)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re16.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re16.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re16.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re16.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re16.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re16.v v12, (a0)
; ZVZIP-NEXT: vl1re16.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re16.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re16.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -8342,22 +8726,23 @@ define <vscale x 10 x bfloat> @vector_interleave_nxv10bf16_nxv2bf16(<vscale x 2
; CHECK-NEXT: vsseg5e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: add a3, a0, a1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v10, (a3)
-; CHECK-NEXT: srli a1, a1, 2
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: vle16.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a2
; CHECK-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v10, a1
-; CHECK-NEXT: add a2, a5, a2
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a0, a1, a0
@@ -8377,22 +8762,23 @@ define <vscale x 10 x bfloat> @vector_interleave_nxv10bf16_nxv2bf16(<vscale x 2
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v10, (a3)
-; ZVBB-NEXT: srli a1, a1, 2
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v10, (a2)
+; ZVBB-NEXT: srli a2, a1, 2
; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
+; ZVBB-NEXT: vslideup.vx v9, v8, a2
; ZVBB-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v10, a1
-; ZVBB-NEXT: add a2, a5, a2
-; ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v10, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 1
; ZVBB-NEXT: add a0, a1, a0
@@ -8415,15 +8801,17 @@ define <vscale x 20 x bfloat> @vector_interleave_nxv20bf16_nxv4bf16(<vscale x 4
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg5e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a1)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
; CHECK-NEXT: add a0, a1, a0
@@ -8442,15 +8830,17 @@ define <vscale x 20 x bfloat> @vector_interleave_nxv20bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a1)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
; ZVBB-NEXT: add a0, a1, a0
@@ -8482,35 +8872,38 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e16.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e16.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re16.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re16.v v11, (a5)
; RV32-NEXT: vl1re16.v v8, (a0)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re16.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re16.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re16.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re16.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re16.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re16.v v12, (a0)
; RV32-NEXT: vl1re16.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re16.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re16.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -8548,35 +8941,38 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e16.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e16.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re16.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re16.v v11, (a5)
; RV64-NEXT: vl1re16.v v8, (a0)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re16.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re16.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re16.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re16.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re16.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re16.v v12, (a0)
; RV64-NEXT: vl1re16.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re16.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re16.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -8614,35 +9010,38 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e16.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e16.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re16.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re16.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re16.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -8680,35 +9079,38 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e16.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e16.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re16.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re16.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re16.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -8746,35 +9148,38 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e16.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e16.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re16.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
; ZVZIP-NEXT: vl1re16.v v8, (a0)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re16.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re16.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re16.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re16.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re16.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re16.v v12, (a0)
; ZVZIP-NEXT: vl1re16.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re16.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re16.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -8808,22 +9213,23 @@ define <vscale x 5 x float> @vector_interleave_nxv5f32_nxv1f32(<vscale x 1 x flo
; CHECK-NEXT: vsseg5e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: add a3, a0, a1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vle32.v v8, (a5)
-; CHECK-NEXT: vle32.v v9, (a4)
-; CHECK-NEXT: vle32.v v10, (a3)
-; CHECK-NEXT: srli a1, a1, 3
+; CHECK-NEXT: vle32.v v8, (a4)
+; CHECK-NEXT: vle32.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle32.v v10, (a2)
+; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a2
; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v10, a1
-; CHECK-NEXT: add a2, a5, a2
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a0, a1, a0
@@ -8843,22 +9249,23 @@ define <vscale x 5 x float> @vector_interleave_nxv5f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg5e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vle32.v v8, (a5)
-; ZVBB-NEXT: vle32.v v9, (a4)
-; ZVBB-NEXT: vle32.v v10, (a3)
-; ZVBB-NEXT: srli a1, a1, 3
+; ZVBB-NEXT: vle32.v v8, (a4)
+; ZVBB-NEXT: vle32.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle32.v v10, (a2)
+; ZVBB-NEXT: srli a2, a1, 3
; ZVBB-NEXT: vsetvli a3, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
+; ZVBB-NEXT: vslideup.vx v9, v8, a2
; ZVBB-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; ZVBB-NEXT: vle32.v v8, (a0)
-; ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v10, a1
-; ZVBB-NEXT: add a2, a5, a2
-; ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: vsetvli a3, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v10, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 1
; ZVBB-NEXT: add a0, a1, a0
@@ -8881,15 +9288,17 @@ define <vscale x 10 x float> @vector_interleave_nxv10f32_nxv2f32(<vscale x 2 x f
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vsseg5e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re32.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re32.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re32.v v11, (a2)
; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a2)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re32.v v12, (a1)
+; CHECK-NEXT: vl1re32.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re32.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
; CHECK-NEXT: add a0, a1, a0
@@ -8908,15 +9317,17 @@ define <vscale x 10 x float> @vector_interleave_nxv10f32_nxv2f32(<vscale x 2 x f
; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVBB-NEXT: vsseg5e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re32.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re32.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re32.v v11, (a2)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a2)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re32.v v12, (a1)
+; ZVBB-NEXT: vl1re32.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re32.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
; ZVBB-NEXT: add a0, a1, a0
@@ -8948,35 +9359,38 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e32.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e32.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re32.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re32.v v11, (a5)
; RV32-NEXT: vl1re32.v v8, (a0)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re32.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re32.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re32.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re32.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re32.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re32.v v12, (a0)
; RV32-NEXT: vl1re32.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re32.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re32.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -9014,35 +9428,38 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e32.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e32.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re32.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re32.v v11, (a5)
; RV64-NEXT: vl1re32.v v8, (a0)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re32.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re32.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re32.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re32.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re32.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re32.v v12, (a0)
; RV64-NEXT: vl1re32.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re32.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re32.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -9080,35 +9497,38 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e32.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e32.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re32.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re32.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re32.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -9146,35 +9566,38 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e32.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e32.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re32.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re32.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re32.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -9212,35 +9635,38 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e32.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e32.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re32.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re32.v v11, (a5)
; ZVZIP-NEXT: vl1re32.v v8, (a0)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re32.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re32.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re32.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re32.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re32.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re32.v v12, (a0)
; ZVZIP-NEXT: vl1re32.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re32.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re32.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -9273,15 +9699,17 @@ define <vscale x 5 x double> @vector_interleave_nxv5f64_nxv1f64(<vscale x 1 x do
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vsseg5e64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re64.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re64.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re64.v v11, (a2)
; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a2)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re64.v v12, (a1)
+; CHECK-NEXT: vl1re64.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re64.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
; CHECK-NEXT: add a0, a1, a0
@@ -9300,15 +9728,17 @@ define <vscale x 5 x double> @vector_interleave_nxv5f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; ZVBB-NEXT: vsseg5e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re64.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re64.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re64.v v11, (a2)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a2)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re64.v v12, (a1)
+; ZVBB-NEXT: vl1re64.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re64.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
; ZVBB-NEXT: add a0, a1, a0
@@ -9340,35 +9770,38 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e64.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e64.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re64.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re64.v v11, (a5)
; RV32-NEXT: vl1re64.v v8, (a0)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re64.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re64.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re64.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re64.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re64.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re64.v v12, (a0)
; RV32-NEXT: vl1re64.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re64.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re64.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -9406,35 +9839,38 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e64.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e64.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re64.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re64.v v11, (a5)
; RV64-NEXT: vl1re64.v v8, (a0)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re64.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re64.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re64.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re64.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re64.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re64.v v12, (a0)
; RV64-NEXT: vl1re64.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re64.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re64.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -9472,35 +9908,38 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e64.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e64.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re64.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re64.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re64.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -9538,35 +9977,38 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e64.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e64.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re64.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re64.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re64.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -9604,35 +10046,38 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e64.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e64.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re64.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re64.v v11, (a5)
; ZVZIP-NEXT: vl1re64.v v8, (a0)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re64.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re64.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re64.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re64.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re64.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re64.v v12, (a0)
; ZVZIP-NEXT: vl1re64.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re64.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re64.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -9666,20 +10111,22 @@ define <vscale x 12 x half> @vector_interleave_nxv12f16_nxv2f16(<vscale x 2 x ha
; CHECK-NEXT: vsseg6e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a2, a6, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: vle16.v v11, (a5)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vle16.v v10, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vle16.v v11, (a4)
; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a4, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
+; CHECK-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v12, (a2)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v11, a1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -9705,20 +10152,22 @@ define <vscale x 12 x half> @vector_interleave_nxv12f16_nxv2f16(<vscale x 2 x ha
; ZVBB-NEXT: vsseg6e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a2, a6, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: vle16.v v11, (a5)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vle16.v v11, (a4)
; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vsetvli a4, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
+; ZVBB-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v11, a1
; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -9747,15 +10196,17 @@ define <vscale x 24 x half> @vector_interleave_nxv24f16_nxv4f16(<vscale x 4 x ha
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg6e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a3)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a0)
; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: vl1re16.v v13, (a1)
; CHECK-NEXT: csrr a0, vlenb
@@ -9776,15 +10227,17 @@ define <vscale x 24 x half> @vector_interleave_nxv24f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg6e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a3)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a0)
; ZVBB-NEXT: add a1, a3, a1
; ZVBB-NEXT: vl1re16.v v13, (a1)
; ZVBB-NEXT: csrr a0, vlenb
@@ -9816,52 +10269,56 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e16.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e16.v v20, (a1)
-; RV32-NEXT: vl1re16.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re16.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re16.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re16.v v13, (a6)
-; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: vl1re16.v v11, (a5)
-; RV32-NEXT: vl1re16.v v8, (a1)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e16.v v20, (a2)
+; RV32-NEXT: vl1re16.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re16.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re16.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re16.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re16.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re16.v v11, (a7)
+; RV32-NEXT: vl1re16.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re16.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re16.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re16.v v19, (a3)
-; RV32-NEXT: vl1re16.v v16, (a0)
-; RV32-NEXT: vl1re16.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re16.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re16.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re16.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re16.v v16, (a2)
+; RV32-NEXT: vl8re16.v v16, (a1)
; RV32-NEXT: vl8re16.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -9887,52 +10344,56 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e16.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e16.v v20, (a1)
-; RV64-NEXT: vl1re16.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re16.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re16.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re16.v v13, (a6)
-; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: vl1re16.v v11, (a5)
-; RV64-NEXT: vl1re16.v v8, (a1)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e16.v v20, (a2)
+; RV64-NEXT: vl1re16.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re16.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re16.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re16.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re16.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re16.v v11, (a7)
+; RV64-NEXT: vl1re16.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re16.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re16.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re16.v v19, (a3)
-; RV64-NEXT: vl1re16.v v16, (a0)
-; RV64-NEXT: vl1re16.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re16.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re16.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re16.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re16.v v16, (a2)
+; RV64-NEXT: vl8re16.v v16, (a1)
; RV64-NEXT: vl8re16.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -9958,52 +10419,56 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e16.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e16.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re16.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e16.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re16.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re16.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re16.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re16.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re16.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re16.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re16.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re16.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -10029,52 +10494,56 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e16.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e16.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re16.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e16.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re16.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re16.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re16.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re16.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re16.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re16.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re16.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re16.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -10100,52 +10569,56 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e16.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e16.v v20, (a1)
-; ZVZIP-NEXT: vl1re16.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re16.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re16.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re16.v v13, (a6)
-; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: vl1re16.v v11, (a5)
-; ZVZIP-NEXT: vl1re16.v v8, (a1)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e16.v v20, (a2)
+; ZVZIP-NEXT: vl1re16.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re16.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re16.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re16.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re16.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re16.v v11, (a7)
+; ZVZIP-NEXT: vl1re16.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re16.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re16.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re16.v v19, (a3)
-; ZVZIP-NEXT: vl1re16.v v16, (a0)
-; ZVZIP-NEXT: vl1re16.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re16.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re16.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re16.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re16.v v16, (a2)
+; ZVZIP-NEXT: vl8re16.v v16, (a1)
; ZVZIP-NEXT: vl8re16.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -10169,20 +10642,22 @@ define <vscale x 12 x bfloat> @vector_interleave_nxv12bf16_nxv2bf16(<vscale x 2
; CHECK-NEXT: vsseg6e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a2, a6, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: vle16.v v11, (a5)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vle16.v v10, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vle16.v v11, (a4)
; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a4, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
+; CHECK-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v12, (a2)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v11, a1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -10208,20 +10683,22 @@ define <vscale x 12 x bfloat> @vector_interleave_nxv12bf16_nxv2bf16(<vscale x 2
; ZVBB-NEXT: vsseg6e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a2, a6, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: vle16.v v11, (a5)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vle16.v v11, (a4)
; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vsetvli a4, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
+; ZVBB-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v11, a1
; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -10250,15 +10727,17 @@ define <vscale x 24 x bfloat> @vector_interleave_nxv24bf16_nxv4bf16(<vscale x 4
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg6e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a3)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a0)
; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: vl1re16.v v13, (a1)
; CHECK-NEXT: csrr a0, vlenb
@@ -10279,15 +10758,17 @@ define <vscale x 24 x bfloat> @vector_interleave_nxv24bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg6e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a3)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a0)
; ZVBB-NEXT: add a1, a3, a1
; ZVBB-NEXT: vl1re16.v v13, (a1)
; ZVBB-NEXT: csrr a0, vlenb
@@ -10319,52 +10800,56 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e16.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e16.v v20, (a1)
-; RV32-NEXT: vl1re16.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re16.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re16.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re16.v v13, (a6)
-; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: vl1re16.v v11, (a5)
-; RV32-NEXT: vl1re16.v v8, (a1)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e16.v v20, (a2)
+; RV32-NEXT: vl1re16.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re16.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re16.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re16.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re16.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re16.v v11, (a7)
+; RV32-NEXT: vl1re16.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re16.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re16.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re16.v v19, (a3)
-; RV32-NEXT: vl1re16.v v16, (a0)
-; RV32-NEXT: vl1re16.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re16.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re16.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re16.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re16.v v16, (a2)
+; RV32-NEXT: vl8re16.v v16, (a1)
; RV32-NEXT: vl8re16.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -10390,52 +10875,56 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e16.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e16.v v20, (a1)
-; RV64-NEXT: vl1re16.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re16.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re16.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re16.v v13, (a6)
-; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: vl1re16.v v11, (a5)
-; RV64-NEXT: vl1re16.v v8, (a1)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e16.v v20, (a2)
+; RV64-NEXT: vl1re16.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re16.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re16.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re16.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re16.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re16.v v11, (a7)
+; RV64-NEXT: vl1re16.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re16.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re16.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re16.v v19, (a3)
-; RV64-NEXT: vl1re16.v v16, (a0)
-; RV64-NEXT: vl1re16.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re16.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re16.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re16.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re16.v v16, (a2)
+; RV64-NEXT: vl8re16.v v16, (a1)
; RV64-NEXT: vl8re16.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -10457,56 +10946,60 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; ZVBB-RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v23, v13
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v25, v17
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: vmv1r.v v23, v13
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v25, v17
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e16.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e16.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re16.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e16.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re16.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re16.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re16.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re16.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re16.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re16.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re16.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re16.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -10532,52 +11025,56 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e16.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e16.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re16.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e16.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re16.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re16.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re16.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re16.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re16.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re16.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re16.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re16.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -10603,52 +11100,56 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e16.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e16.v v20, (a1)
-; ZVZIP-NEXT: vl1re16.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re16.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re16.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re16.v v13, (a6)
-; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: vl1re16.v v11, (a5)
-; ZVZIP-NEXT: vl1re16.v v8, (a1)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e16.v v20, (a2)
+; ZVZIP-NEXT: vl1re16.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re16.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re16.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re16.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re16.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re16.v v11, (a7)
+; ZVZIP-NEXT: vl1re16.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re16.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re16.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re16.v v19, (a3)
-; ZVZIP-NEXT: vl1re16.v v16, (a0)
-; ZVZIP-NEXT: vl1re16.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re16.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re16.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re16.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re16.v v16, (a2)
+; ZVZIP-NEXT: vl8re16.v v16, (a1)
; ZVZIP-NEXT: vl8re16.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -10672,20 +11173,22 @@ define <vscale x 6 x float> @vector_interleave_nxv6f32_nxv1f32(<vscale x 1 x flo
; CHECK-NEXT: vsseg6e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a2, a6, a2
-; CHECK-NEXT: vle32.v v8, (a2)
-; CHECK-NEXT: vle32.v v10, (a6)
-; CHECK-NEXT: vle32.v v11, (a5)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle32.v v8, (a4)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vle32.v v10, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vle32.v v11, (a4)
; CHECK-NEXT: srli a1, a1, 3
-; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a4, zero, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v9, (a4)
-; CHECK-NEXT: vle32.v v12, (a3)
+; CHECK-NEXT: vsetvli a4, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle32.v v12, (a2)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v11, a1
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
@@ -10711,20 +11214,22 @@ define <vscale x 6 x float> @vector_interleave_nxv6f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg6e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a2, a6, a2
-; ZVBB-NEXT: vle32.v v8, (a2)
-; ZVBB-NEXT: vle32.v v10, (a6)
-; ZVBB-NEXT: vle32.v v11, (a5)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle32.v v8, (a4)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle32.v v10, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vle32.v v11, (a4)
; ZVBB-NEXT: srli a1, a1, 3
-; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vsetvli a4, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v9, (a4)
-; ZVBB-NEXT: vle32.v v12, (a3)
+; ZVBB-NEXT: vsetvli a4, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle32.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v11, a1
; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
@@ -10753,15 +11258,17 @@ define <vscale x 12 x float> @vector_interleave_nxv12f32_nxv2f32(<vscale x 2 x f
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vsseg6e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re32.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re32.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re32.v v11, (a2)
; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re32.v v12, (a3)
+; CHECK-NEXT: vl1re32.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re32.v v12, (a0)
; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: vl1re32.v v13, (a1)
; CHECK-NEXT: csrr a0, vlenb
@@ -10782,15 +11289,17 @@ define <vscale x 12 x float> @vector_interleave_nxv12f32_nxv2f32(<vscale x 2 x f
; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVBB-NEXT: vsseg6e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re32.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re32.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re32.v v11, (a2)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re32.v v12, (a3)
+; ZVBB-NEXT: vl1re32.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re32.v v12, (a0)
; ZVBB-NEXT: add a1, a3, a1
; ZVBB-NEXT: vl1re32.v v13, (a1)
; ZVBB-NEXT: csrr a0, vlenb
@@ -10822,52 +11331,56 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e32.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e32.v v20, (a1)
-; RV32-NEXT: vl1re32.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re32.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re32.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re32.v v13, (a6)
-; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: vl1re32.v v11, (a5)
-; RV32-NEXT: vl1re32.v v8, (a1)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e32.v v20, (a2)
+; RV32-NEXT: vl1re32.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re32.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re32.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re32.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re32.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re32.v v11, (a7)
+; RV32-NEXT: vl1re32.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re32.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re32.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re32.v v19, (a3)
-; RV32-NEXT: vl1re32.v v16, (a0)
-; RV32-NEXT: vl1re32.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re32.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re32.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re32.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re32.v v16, (a2)
+; RV32-NEXT: vl8re32.v v16, (a1)
; RV32-NEXT: vl8re32.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -10893,52 +11406,56 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e32.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e32.v v20, (a1)
-; RV64-NEXT: vl1re32.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re32.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re32.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re32.v v13, (a6)
-; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: vl1re32.v v11, (a5)
-; RV64-NEXT: vl1re32.v v8, (a1)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e32.v v20, (a2)
+; RV64-NEXT: vl1re32.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re32.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re32.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re32.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re32.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re32.v v11, (a7)
+; RV64-NEXT: vl1re32.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re32.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re32.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re32.v v19, (a3)
-; RV64-NEXT: vl1re32.v v16, (a0)
-; RV64-NEXT: vl1re32.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re32.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re32.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re32.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re32.v v16, (a2)
+; RV64-NEXT: vl8re32.v v16, (a1)
; RV64-NEXT: vl8re32.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -10964,52 +11481,56 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e32.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e32.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re32.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e32.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re32.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re32.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re32.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re32.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re32.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re32.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re32.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re32.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -11035,52 +11556,56 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e32.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e32.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re32.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e32.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re32.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re32.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re32.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re32.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re32.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re32.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re32.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re32.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11106,52 +11631,56 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e32.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e32.v v20, (a1)
-; ZVZIP-NEXT: vl1re32.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re32.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re32.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re32.v v13, (a6)
-; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: vl1re32.v v11, (a5)
-; ZVZIP-NEXT: vl1re32.v v8, (a1)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e32.v v20, (a2)
+; ZVZIP-NEXT: vl1re32.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re32.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re32.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re32.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re32.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re32.v v11, (a7)
+; ZVZIP-NEXT: vl1re32.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re32.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re32.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re32.v v19, (a3)
-; ZVZIP-NEXT: vl1re32.v v16, (a0)
-; ZVZIP-NEXT: vl1re32.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re32.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re32.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re32.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re32.v v16, (a2)
+; ZVZIP-NEXT: vl8re32.v v16, (a1)
; ZVZIP-NEXT: vl8re32.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11174,15 +11703,17 @@ define <vscale x 6 x double> @vector_interleave_nxv6f64_nxv1f64(<vscale x 1 x do
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vsseg6e64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re64.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re64.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re64.v v11, (a2)
; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re64.v v12, (a3)
+; CHECK-NEXT: vl1re64.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re64.v v12, (a0)
; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: vl1re64.v v13, (a1)
; CHECK-NEXT: csrr a0, vlenb
@@ -11203,15 +11734,17 @@ define <vscale x 6 x double> @vector_interleave_nxv6f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; ZVBB-NEXT: vsseg6e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re64.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re64.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re64.v v11, (a2)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re64.v v12, (a3)
+; ZVBB-NEXT: vl1re64.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re64.v v12, (a0)
; ZVBB-NEXT: add a1, a3, a1
; ZVBB-NEXT: vl1re64.v v13, (a1)
; ZVBB-NEXT: csrr a0, vlenb
@@ -11243,52 +11776,56 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e64.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e64.v v20, (a1)
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e64.v v20, (a2)
; RV32-NEXT: vl1re64.v v14, (a0)
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re64.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re64.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re64.v v13, (a6)
-; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: vl1re64.v v11, (a5)
-; RV32-NEXT: vl1re64.v v8, (a1)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re64.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re64.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re64.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re64.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re64.v v11, (a7)
+; RV32-NEXT: vl1re64.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re64.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re64.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re64.v v19, (a3)
-; RV32-NEXT: vl1re64.v v16, (a0)
-; RV32-NEXT: vl1re64.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re64.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re64.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re64.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re64.v v16, (a2)
+; RV32-NEXT: vl8re64.v v16, (a1)
; RV32-NEXT: vl8re64.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -11314,52 +11851,56 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e64.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e64.v v20, (a1)
-; RV64-NEXT: vl1re64.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re64.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re64.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re64.v v13, (a6)
-; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: vl1re64.v v11, (a5)
-; RV64-NEXT: vl1re64.v v8, (a1)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e64.v v20, (a2)
+; RV64-NEXT: vl1re64.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re64.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re64.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re64.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re64.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re64.v v11, (a7)
+; RV64-NEXT: vl1re64.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re64.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re64.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re64.v v19, (a3)
-; RV64-NEXT: vl1re64.v v16, (a0)
-; RV64-NEXT: vl1re64.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re64.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re64.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re64.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re64.v v16, (a2)
+; RV64-NEXT: vl8re64.v v16, (a1)
; RV64-NEXT: vl8re64.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11385,52 +11926,56 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e64.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e64.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re64.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e64.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re64.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re64.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re64.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re64.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re64.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re64.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re64.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re64.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -11456,52 +12001,56 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e64.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e64.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re64.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e64.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re64.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re64.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re64.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re64.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re64.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re64.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re64.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re64.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11527,52 +12076,56 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e64.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e64.v v20, (a1)
-; ZVZIP-NEXT: vl1re64.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re64.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re64.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re64.v v13, (a6)
-; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: vl1re64.v v11, (a5)
-; ZVZIP-NEXT: vl1re64.v v8, (a1)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e64.v v20, (a2)
+; ZVZIP-NEXT: vl1re64.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re64.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re64.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re64.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re64.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re64.v v11, (a7)
+; ZVZIP-NEXT: vl1re64.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re64.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re64.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re64.v v19, (a3)
-; ZVZIP-NEXT: vl1re64.v v16, (a0)
-; ZVZIP-NEXT: vl1re64.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re64.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re64.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re64.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re64.v v16, (a2)
+; ZVZIP-NEXT: vl8re64.v v16, (a1)
; ZVZIP-NEXT: vl8re64.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11595,28 +12148,30 @@ define <vscale x 14 x half> @vector_interleave_nxv14f16_nxv2f16(<vscale x 2 x ha
; CHECK-NEXT: vsseg7e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vle16.v v8, (a7)
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a6, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vsetvli a6, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v11, (a2)
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: add a4, a0, a3
+; CHECK-NEXT: vle16.v v10, (a4)
+; CHECK-NEXT: srli a4, a1, 2
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: vsetvli a5, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v10, v8, a4
+; CHECK-NEXT: add a3, a1, a3
+; CHECK-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v11, (a3)
+; CHECK-NEXT: add a3, a1, a2
+; CHECK-NEXT: vle16.v v8, (a3)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v12, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v8, a4
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add sp, sp, a0
@@ -11634,28 +12189,30 @@ define <vscale x 14 x half> @vector_interleave_nxv14f16_nxv2f16(<vscale x 2 x ha
; ZVBB-NEXT: vsseg7e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vle16.v v8, (a7)
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a6, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vsetvli a6, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v11, (a2)
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vle16.v v10, (a4)
+; ZVBB-NEXT: srli a4, a1, 2
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: vsetvli a5, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v10, v8, a4
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v11, (a3)
+; ZVBB-NEXT: add a3, a1, a2
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: vle16.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
+; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v9, v8, a4
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v12, a1
+; ZVBB-NEXT: vslideup.vx v8, v12, a4
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -11677,19 +12234,22 @@ define <vscale x 28 x half> @vector_interleave_nxv28f16_nxv4f16(<vscale x 4 x ha
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg7e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a4)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a3)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a4)
; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: vl1re16.v v13, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v14, (a1)
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v14, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 3
; CHECK-NEXT: sub a0, a1, a0
@@ -11708,19 +12268,22 @@ define <vscale x 28 x half> @vector_interleave_nxv28f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg7e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a4)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a3)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a4)
; ZVBB-NEXT: add a3, a3, a1
; ZVBB-NEXT: vl1re16.v v13, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v14, (a1)
+; ZVBB-NEXT: add a1, a1, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v14, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 3
; ZVBB-NEXT: sub a0, a1, a0
@@ -11754,59 +12317,63 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e16.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e16.v v21, (a2)
+; RV32-NEXT: vsseg7e16.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e16.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v11, (a4)
-; RV32-NEXT: vl1re16.v v8, (a1)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v14, (a4)
-; RV32-NEXT: vl1re16.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re16.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re16.v v11, (a5)
+; RV32-NEXT: vl1re16.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re16.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re16.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re16.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re16.v v14, (a2)
+; RV32-NEXT: vl1re16.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re16.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re16.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re16.v v16, (a2)
-; RV32-NEXT: vl1re16.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re16.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re16.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re16.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re16.v v16, (a0)
-; RV32-NEXT: vl8re16.v v8, (a2)
+; RV32-NEXT: vl8re16.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -11835,59 +12402,63 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e16.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e16.v v21, (a2)
+; RV64-NEXT: vsseg7e16.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e16.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v11, (a4)
-; RV64-NEXT: vl1re16.v v8, (a1)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v14, (a4)
-; RV64-NEXT: vl1re16.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re16.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re16.v v11, (a5)
+; RV64-NEXT: vl1re16.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re16.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re16.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re16.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re16.v v14, (a2)
+; RV64-NEXT: vl1re16.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re16.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re16.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re16.v v16, (a2)
-; RV64-NEXT: vl1re16.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re16.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re16.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re16.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re16.v v16, (a0)
-; RV64-NEXT: vl8re16.v v8, (a2)
+; RV64-NEXT: vl8re16.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -11916,59 +12487,63 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -11997,59 +12572,63 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -12076,61 +12655,65 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVZIP-NEXT: vmv1r.v v5, v24
; ZVZIP-NEXT: vmv1r.v v7, v26
; ZVZIP-NEXT: vmv1r.v v2, v10
-; ZVZIP-NEXT: vmv1r.v v4, v14
-; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e16.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: vmv1r.v v4, v14
+; ZVZIP-NEXT: vmv1r.v v6, v18
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e16.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e16.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e16.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v11, (a4)
-; ZVZIP-NEXT: vl1re16.v v8, (a1)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v14, (a4)
-; ZVZIP-NEXT: vl1re16.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re16.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
+; ZVZIP-NEXT: vl1re16.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re16.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re16.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re16.v v14, (a2)
+; ZVZIP-NEXT: vl1re16.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re16.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re16.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re16.v v16, (a2)
-; ZVZIP-NEXT: vl1re16.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re16.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re16.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re16.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re16.v v16, (a0)
-; ZVZIP-NEXT: vl8re16.v v8, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -12152,28 +12735,30 @@ define <vscale x 14 x bfloat> @vector_interleave_nxv14bf16_nxv2bf16(<vscale x 2
; CHECK-NEXT: vsseg7e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vle16.v v8, (a7)
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a6, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vsetvli a6, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v11, (a2)
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: add a4, a0, a3
+; CHECK-NEXT: vle16.v v10, (a4)
+; CHECK-NEXT: srli a4, a1, 2
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: vsetvli a5, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v10, v8, a4
+; CHECK-NEXT: add a3, a1, a3
+; CHECK-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v11, (a3)
+; CHECK-NEXT: add a3, a1, a2
+; CHECK-NEXT: vle16.v v8, (a3)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v12, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v8, a4
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add sp, sp, a0
@@ -12191,28 +12776,30 @@ define <vscale x 14 x bfloat> @vector_interleave_nxv14bf16_nxv2bf16(<vscale x 2
; ZVBB-NEXT: vsseg7e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vle16.v v8, (a7)
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a6, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vsetvli a6, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v11, (a2)
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vle16.v v10, (a4)
+; ZVBB-NEXT: srli a4, a1, 2
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: vsetvli a5, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v10, v8, a4
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v11, (a3)
+; ZVBB-NEXT: add a3, a1, a2
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: vle16.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
+; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v9, v8, a4
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v12, a1
+; ZVBB-NEXT: vslideup.vx v8, v12, a4
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -12234,19 +12821,22 @@ define <vscale x 28 x bfloat> @vector_interleave_nxv28bf16_nxv4bf16(<vscale x 4
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg7e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a4)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a3)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a4)
; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: vl1re16.v v13, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v14, (a1)
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v14, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 3
; CHECK-NEXT: sub a0, a1, a0
@@ -12265,19 +12855,22 @@ define <vscale x 28 x bfloat> @vector_interleave_nxv28bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg7e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a4)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a3)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a4)
; ZVBB-NEXT: add a3, a3, a1
; ZVBB-NEXT: vl1re16.v v13, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v14, (a1)
+; ZVBB-NEXT: add a1, a1, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v14, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 3
; ZVBB-NEXT: sub a0, a1, a0
@@ -12311,59 +12904,63 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e16.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e16.v v21, (a2)
+; RV32-NEXT: vsseg7e16.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e16.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v11, (a4)
-; RV32-NEXT: vl1re16.v v8, (a1)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v14, (a4)
-; RV32-NEXT: vl1re16.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re16.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re16.v v11, (a5)
+; RV32-NEXT: vl1re16.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re16.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re16.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re16.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re16.v v14, (a2)
+; RV32-NEXT: vl1re16.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re16.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re16.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re16.v v16, (a2)
-; RV32-NEXT: vl1re16.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re16.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re16.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re16.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re16.v v16, (a0)
-; RV32-NEXT: vl8re16.v v8, (a2)
+; RV32-NEXT: vl8re16.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -12392,59 +12989,63 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e16.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e16.v v21, (a2)
+; RV64-NEXT: vsseg7e16.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e16.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v11, (a4)
-; RV64-NEXT: vl1re16.v v8, (a1)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v14, (a4)
-; RV64-NEXT: vl1re16.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re16.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re16.v v11, (a5)
+; RV64-NEXT: vl1re16.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re16.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re16.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re16.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re16.v v14, (a2)
+; RV64-NEXT: vl1re16.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re16.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re16.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re16.v v16, (a2)
-; RV64-NEXT: vl1re16.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re16.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re16.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re16.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re16.v v16, (a0)
-; RV64-NEXT: vl8re16.v v8, (a2)
+; RV64-NEXT: vl8re16.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -12473,59 +13074,63 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -12554,59 +13159,63 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -12635,59 +13244,63 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e16.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e16.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e16.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e16.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v11, (a4)
-; ZVZIP-NEXT: vl1re16.v v8, (a1)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v14, (a4)
-; ZVZIP-NEXT: vl1re16.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re16.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
+; ZVZIP-NEXT: vl1re16.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re16.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re16.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re16.v v14, (a2)
+; ZVZIP-NEXT: vl1re16.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re16.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re16.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re16.v v16, (a2)
-; ZVZIP-NEXT: vl1re16.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re16.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re16.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re16.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re16.v v16, (a0)
-; ZVZIP-NEXT: vl8re16.v v8, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -12709,28 +13322,30 @@ define <vscale x 7 x float> @vector_interleave_nxv7f32_nxv1f32(<vscale x 1 x flo
; CHECK-NEXT: vsseg7e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vle32.v v8, (a7)
-; CHECK-NEXT: vle32.v v10, (a6)
-; CHECK-NEXT: srli a1, a1, 3
-; CHECK-NEXT: vsetvli a6, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vsetvli a6, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v11, (a2)
-; CHECK-NEXT: vle32.v v8, (a5)
-; CHECK-NEXT: vle32.v v9, (a4)
-; CHECK-NEXT: vle32.v v12, (a3)
-; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle32.v v8, (a4)
+; CHECK-NEXT: add a4, a0, a3
+; CHECK-NEXT: vle32.v v10, (a4)
+; CHECK-NEXT: srli a4, a1, 3
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: vsetvli a5, zero, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v10, v8, a4
+; CHECK-NEXT: add a3, a1, a3
+; CHECK-NEXT: vsetvli a5, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v11, (a3)
+; CHECK-NEXT: add a3, a1, a2
+; CHECK-NEXT: vle32.v v8, (a3)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle32.v v12, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v8, a4
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add sp, sp, a0
@@ -12748,28 +13363,30 @@ define <vscale x 7 x float> @vector_interleave_nxv7f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg7e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vle32.v v8, (a7)
-; ZVBB-NEXT: vle32.v v10, (a6)
-; ZVBB-NEXT: srli a1, a1, 3
-; ZVBB-NEXT: vsetvli a6, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vsetvli a6, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v11, (a2)
-; ZVBB-NEXT: vle32.v v8, (a5)
-; ZVBB-NEXT: vle32.v v9, (a4)
-; ZVBB-NEXT: vle32.v v12, (a3)
-; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle32.v v8, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vle32.v v10, (a4)
+; ZVBB-NEXT: srli a4, a1, 3
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: vsetvli a5, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v10, v8, a4
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vsetvli a5, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v11, (a3)
+; ZVBB-NEXT: add a3, a1, a2
+; ZVBB-NEXT: vle32.v v8, (a3)
+; ZVBB-NEXT: vle32.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle32.v v12, (a2)
+; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v9, v8, a4
+; ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; ZVBB-NEXT: vle32.v v8, (a0)
; ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v12, a1
+; ZVBB-NEXT: vslideup.vx v8, v12, a4
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -12791,19 +13408,22 @@ define <vscale x 14 x float> @vector_interleave_nxv14f32_nxv2f32(<vscale x 2 x f
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vsseg7e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re32.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re32.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vl1re32.v v11, (a4)
; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re32.v v12, (a3)
+; CHECK-NEXT: vl1re32.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: vl1re32.v v12, (a4)
; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: vl1re32.v v13, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re32.v v14, (a1)
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re32.v v14, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 3
; CHECK-NEXT: sub a0, a1, a0
@@ -12822,19 +13442,22 @@ define <vscale x 14 x float> @vector_interleave_nxv14f32_nxv2f32(<vscale x 2 x f
; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVBB-NEXT: vsseg7e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re32.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re32.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vl1re32.v v11, (a4)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re32.v v12, (a3)
+; ZVBB-NEXT: vl1re32.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: vl1re32.v v12, (a4)
; ZVBB-NEXT: add a3, a3, a1
; ZVBB-NEXT: vl1re32.v v13, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re32.v v14, (a1)
+; ZVBB-NEXT: add a1, a1, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re32.v v14, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 3
; ZVBB-NEXT: sub a0, a1, a0
@@ -12868,59 +13491,63 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e32.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e32.v v21, (a2)
+; RV32-NEXT: vsseg7e32.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e32.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v11, (a4)
-; RV32-NEXT: vl1re32.v v8, (a1)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v14, (a4)
-; RV32-NEXT: vl1re32.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re32.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re32.v v11, (a5)
+; RV32-NEXT: vl1re32.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re32.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re32.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re32.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re32.v v14, (a2)
+; RV32-NEXT: vl1re32.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re32.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re32.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re32.v v16, (a2)
-; RV32-NEXT: vl1re32.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re32.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re32.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re32.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re32.v v16, (a0)
-; RV32-NEXT: vl8re32.v v8, (a2)
+; RV32-NEXT: vl8re32.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -12949,59 +13576,63 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e32.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e32.v v21, (a2)
+; RV64-NEXT: vsseg7e32.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e32.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v11, (a4)
-; RV64-NEXT: vl1re32.v v8, (a1)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v14, (a4)
-; RV64-NEXT: vl1re32.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re32.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re32.v v11, (a5)
+; RV64-NEXT: vl1re32.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re32.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re32.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re32.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re32.v v14, (a2)
+; RV64-NEXT: vl1re32.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re32.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re32.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re32.v v16, (a2)
-; RV64-NEXT: vl1re32.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re32.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re32.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re32.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re32.v v16, (a0)
-; RV64-NEXT: vl8re32.v v8, (a2)
+; RV64-NEXT: vl8re32.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13030,59 +13661,63 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e32.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e32.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e32.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e32.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re32.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re32.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re32.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re32.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re32.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re32.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re32.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re32.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re32.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -13111,59 +13746,63 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e32.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e32.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e32.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e32.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re32.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re32.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re32.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re32.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re32.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re32.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re32.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re32.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re32.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13192,59 +13831,63 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e32.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e32.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e32.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e32.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v11, (a4)
-; ZVZIP-NEXT: vl1re32.v v8, (a1)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v14, (a4)
-; ZVZIP-NEXT: vl1re32.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re32.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re32.v v11, (a5)
+; ZVZIP-NEXT: vl1re32.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re32.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re32.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re32.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re32.v v14, (a2)
+; ZVZIP-NEXT: vl1re32.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re32.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re32.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re32.v v16, (a2)
-; ZVZIP-NEXT: vl1re32.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re32.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re32.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re32.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re32.v v16, (a0)
-; ZVZIP-NEXT: vl8re32.v v8, (a2)
+; ZVZIP-NEXT: vl8re32.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13266,19 +13909,22 @@ define <vscale x 7 x double> @vector_interleave_nxv7f64_nxv1f64(<vscale x 1 x do
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vsseg7e64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re64.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re64.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vl1re64.v v11, (a4)
; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re64.v v12, (a3)
+; CHECK-NEXT: vl1re64.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: vl1re64.v v12, (a4)
; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: vl1re64.v v13, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re64.v v14, (a1)
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re64.v v14, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 3
; CHECK-NEXT: sub a0, a1, a0
@@ -13297,19 +13943,22 @@ define <vscale x 7 x double> @vector_interleave_nxv7f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; ZVBB-NEXT: vsseg7e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re64.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re64.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vl1re64.v v11, (a4)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re64.v v12, (a3)
+; ZVBB-NEXT: vl1re64.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: vl1re64.v v12, (a4)
; ZVBB-NEXT: add a3, a3, a1
; ZVBB-NEXT: vl1re64.v v13, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re64.v v14, (a1)
+; ZVBB-NEXT: add a1, a1, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re64.v v14, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 3
; ZVBB-NEXT: sub a0, a1, a0
@@ -13343,59 +13992,63 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e64.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e64.v v21, (a2)
+; RV32-NEXT: vsseg7e64.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e64.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v11, (a4)
-; RV32-NEXT: vl1re64.v v8, (a1)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v14, (a4)
-; RV32-NEXT: vl1re64.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re64.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re64.v v11, (a5)
+; RV32-NEXT: vl1re64.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re64.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re64.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re64.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re64.v v14, (a2)
+; RV32-NEXT: vl1re64.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re64.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re64.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re64.v v16, (a2)
-; RV32-NEXT: vl1re64.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re64.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re64.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re64.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re64.v v16, (a0)
-; RV32-NEXT: vl8re64.v v8, (a2)
+; RV32-NEXT: vl8re64.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -13424,59 +14077,63 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e64.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e64.v v21, (a2)
+; RV64-NEXT: vsseg7e64.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e64.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v11, (a4)
-; RV64-NEXT: vl1re64.v v8, (a1)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v14, (a4)
-; RV64-NEXT: vl1re64.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re64.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re64.v v11, (a5)
+; RV64-NEXT: vl1re64.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re64.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re64.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re64.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re64.v v14, (a2)
+; RV64-NEXT: vl1re64.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re64.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re64.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re64.v v16, (a2)
-; RV64-NEXT: vl1re64.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re64.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re64.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re64.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re64.v v16, (a0)
-; RV64-NEXT: vl8re64.v v8, (a2)
+; RV64-NEXT: vl8re64.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13505,59 +14162,63 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e64.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e64.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e64.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e64.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re64.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re64.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re64.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re64.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re64.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re64.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re64.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re64.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re64.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -13586,59 +14247,63 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e64.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e64.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e64.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e64.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re64.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re64.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re64.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re64.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re64.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re64.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re64.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re64.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re64.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13667,59 +14332,63 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e64.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e64.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e64.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e64.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v11, (a4)
-; ZVZIP-NEXT: vl1re64.v v8, (a1)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v14, (a4)
-; ZVZIP-NEXT: vl1re64.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re64.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re64.v v11, (a5)
+; ZVZIP-NEXT: vl1re64.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re64.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re64.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re64.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re64.v v14, (a2)
+; ZVZIP-NEXT: vl1re64.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re64.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re64.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re64.v v16, (a2)
-; ZVZIP-NEXT: vl1re64.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re64.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re64.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re64.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re64.v v16, (a0)
-; ZVZIP-NEXT: vl8re64.v v8, (a2)
+; ZVZIP-NEXT: vl8re64.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13741,27 +14410,31 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv2f16(<vscale x 2 x ha
; CHECK-NEXT: vsseg8e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: add a2, t0, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v11, (t0)
-; CHECK-NEXT: vle16.v v9, (a7)
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: sub a3, a3, a2
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vle16.v v8, (a3)
+; CHECK-NEXT: slli a3, a1, 1
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: add a5, a4, a3
+; CHECK-NEXT: vle16.v v11, (a5)
+; CHECK-NEXT: add a5, a3, a2
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vle16.v v9, (a5)
; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a5, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v11, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v10, (a3)
+; CHECK-NEXT: add a3, a4, a2
+; CHECK-NEXT: vle16.v v8, (a3)
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v10, v9, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v12, (a2)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v8, a1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -13785,27 +14458,31 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv2f16(<vscale x 2 x ha
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: add a2, t0, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v11, (t0)
-; ZVBB-NEXT: vle16.v v9, (a7)
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: sub a3, a3, a2
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: slli a3, a1, 1
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: add a5, a4, a3
+; ZVBB-NEXT: vle16.v v11, (a5)
+; ZVBB-NEXT: add a5, a3, a2
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vle16.v v9, (a5)
; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vsetvli a5, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v11, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: add a3, a4, a2
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v9, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -13832,21 +14509,26 @@ define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv4f16(<vscale x 4 x ha
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg8e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: add a4, a3, a1
-; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: add a6, a5, a1
-; CHECK-NEXT: add a7, a6, a1
-; CHECK-NEXT: vl1re16.v v14, (a7)
-; CHECK-NEXT: add a1, a7, a1
-; CHECK-NEXT: vl1re16.v v15, (a1)
-; CHECK-NEXT: vl1re16.v v12, (a5)
-; CHECK-NEXT: vl1re16.v v13, (a6)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1re16.v v14, (a4)
+; CHECK-NEXT: slli a4, a1, 3
+; CHECK-NEXT: sub a5, a0, a1
+; CHECK-NEXT: add a4, a5, a4
+; CHECK-NEXT: vl1re16.v v15, (a4)
+; CHECK-NEXT: add a4, a0, a3
+; CHECK-NEXT: vl1re16.v v12, (a4)
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: add a3, a1, a3
+; CHECK-NEXT: vl1re16.v v13, (a3)
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: vl1re16.v v11, (a4)
+; CHECK-NEXT: add a2, a1, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
+; CHECK-NEXT: vl1re16.v v9, (a1)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -13863,21 +14545,26 @@ define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: add a4, a3, a1
-; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: add a6, a5, a1
-; ZVBB-NEXT: add a7, a6, a1
-; ZVBB-NEXT: vl1re16.v v14, (a7)
-; ZVBB-NEXT: add a1, a7, a1
-; ZVBB-NEXT: vl1re16.v v15, (a1)
-; ZVBB-NEXT: vl1re16.v v12, (a5)
-; ZVBB-NEXT: vl1re16.v v13, (a6)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re16.v v14, (a4)
+; ZVBB-NEXT: slli a4, a1, 3
+; ZVBB-NEXT: sub a5, a0, a1
+; ZVBB-NEXT: add a4, a5, a4
+; ZVBB-NEXT: vl1re16.v v15, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vl1re16.v v12, (a4)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vl1re16.v v13, (a3)
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: vl1re16.v v11, (a4)
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: vl1re16.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -13907,48 +14594,55 @@ define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv8f16(<vscale x 8 x ha
; CHECK-NEXT: vmv1r.v v6, v19
; CHECK-NEXT: vmv1r.v v7, v31
; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vsseg8e16.v v1, (a1)
; CHECK-NEXT: vmv1r.v v25, v10
; CHECK-NEXT: vmv1r.v v27, v14
; CHECK-NEXT: vmv1r.v v29, v18
; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsseg8e16.v v24, (a0)
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re16.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re16.v v23, (t0)
-; CHECK-NEXT: vl1re16.v v20, (a6)
-; CHECK-NEXT: vl1re16.v v21, (a7)
+; CHECK-NEXT: slli a3, a2, 1
+; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl1re16.v v18, (a4)
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a5, a1, a4
; CHECK-NEXT: vl1re16.v v19, (a5)
; CHECK-NEXT: vl1re16.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re16.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re16.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re16.v v15, (a2)
-; CHECK-NEXT: vl1re16.v v12, (a3)
-; CHECK-NEXT: vl1re16.v v13, (a6)
-; CHECK-NEXT: vl1re16.v v10, (a4)
-; CHECK-NEXT: vl1re16.v v11, (a5)
+; CHECK-NEXT: add a5, a1, a2
+; CHECK-NEXT: vl1re16.v v17, (a5)
+; CHECK-NEXT: slli a5, a2, 2
+; CHECK-NEXT: add a6, a5, a3
+; CHECK-NEXT: add a7, a1, a6
+; CHECK-NEXT: vl1re16.v v22, (a7)
+; CHECK-NEXT: slli a7, a2, 3
+; CHECK-NEXT: sub a7, a7, a2
+; CHECK-NEXT: add t0, a1, a7
+; CHECK-NEXT: vl1re16.v v23, (t0)
+; CHECK-NEXT: add t0, a1, a5
+; CHECK-NEXT: vl1re16.v v20, (t0)
+; CHECK-NEXT: add t0, a5, a2
+; CHECK-NEXT: add a1, a1, t0
+; CHECK-NEXT: vl1re16.v v21, (a1)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vl1re16.v v10, (a3)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1re16.v v11, (a4)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl1re16.v v9, (a2)
+; CHECK-NEXT: add a6, a0, a6
+; CHECK-NEXT: vl1re16.v v14, (a6)
+; CHECK-NEXT: add a7, a0, a7
+; CHECK-NEXT: vl1re16.v v15, (a7)
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vl1re16.v v12, (a5)
+; CHECK-NEXT: add a0, a0, t0
+; CHECK-NEXT: vl1re16.v v13, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
@@ -13974,48 +14668,55 @@ define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv8f16(<vscale x 8 x ha
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e16.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e16.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re16.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re16.v v23, (t0)
-; ZVBB-NEXT: vl1re16.v v20, (a6)
-; ZVBB-NEXT: vl1re16.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re16.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re16.v v19, (a5)
; ZVBB-NEXT: vl1re16.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re16.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re16.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re16.v v15, (a2)
-; ZVBB-NEXT: vl1re16.v v12, (a3)
-; ZVBB-NEXT: vl1re16.v v13, (a6)
-; ZVBB-NEXT: vl1re16.v v10, (a4)
-; ZVBB-NEXT: vl1re16.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re16.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re16.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re16.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re16.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re16.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re16.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re16.v v11, (a4)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re16.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re16.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re16.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re16.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -14037,27 +14738,31 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv2bf16(<vscale x 2
; CHECK-NEXT: vsseg8e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: add a2, t0, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v11, (t0)
-; CHECK-NEXT: vle16.v v9, (a7)
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: sub a3, a3, a2
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vle16.v v8, (a3)
+; CHECK-NEXT: slli a3, a1, 1
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: add a5, a4, a3
+; CHECK-NEXT: vle16.v v11, (a5)
+; CHECK-NEXT: add a5, a3, a2
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vle16.v v9, (a5)
; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a5, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v11, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v10, (a3)
+; CHECK-NEXT: add a3, a4, a2
+; CHECK-NEXT: vle16.v v8, (a3)
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v10, v9, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v12, (a2)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v8, a1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -14081,27 +14786,31 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv2bf16(<vscale x 2
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: add a2, t0, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v11, (t0)
-; ZVBB-NEXT: vle16.v v9, (a7)
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: sub a3, a3, a2
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: slli a3, a1, 1
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: add a5, a4, a3
+; ZVBB-NEXT: vle16.v v11, (a5)
+; ZVBB-NEXT: add a5, a3, a2
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vle16.v v9, (a5)
; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vsetvli a5, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v11, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: add a3, a4, a2
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v9, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -14128,21 +14837,26 @@ define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv4bf16(<vscale x 4
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg8e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: add a4, a3, a1
-; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: add a6, a5, a1
-; CHECK-NEXT: add a7, a6, a1
-; CHECK-NEXT: vl1re16.v v14, (a7)
-; CHECK-NEXT: add a1, a7, a1
-; CHECK-NEXT: vl1re16.v v15, (a1)
-; CHECK-NEXT: vl1re16.v v12, (a5)
-; CHECK-NEXT: vl1re16.v v13, (a6)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1re16.v v14, (a4)
+; CHECK-NEXT: slli a4, a1, 3
+; CHECK-NEXT: sub a5, a0, a1
+; CHECK-NEXT: add a4, a5, a4
+; CHECK-NEXT: vl1re16.v v15, (a4)
+; CHECK-NEXT: add a4, a0, a3
+; CHECK-NEXT: vl1re16.v v12, (a4)
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: add a3, a1, a3
+; CHECK-NEXT: vl1re16.v v13, (a3)
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: vl1re16.v v11, (a4)
+; CHECK-NEXT: add a2, a1, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
+; CHECK-NEXT: vl1re16.v v9, (a1)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -14159,21 +14873,26 @@ define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: add a4, a3, a1
-; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: add a6, a5, a1
-; ZVBB-NEXT: add a7, a6, a1
-; ZVBB-NEXT: vl1re16.v v14, (a7)
-; ZVBB-NEXT: add a1, a7, a1
-; ZVBB-NEXT: vl1re16.v v15, (a1)
-; ZVBB-NEXT: vl1re16.v v12, (a5)
-; ZVBB-NEXT: vl1re16.v v13, (a6)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re16.v v14, (a4)
+; ZVBB-NEXT: slli a4, a1, 3
+; ZVBB-NEXT: sub a5, a0, a1
+; ZVBB-NEXT: add a4, a5, a4
+; ZVBB-NEXT: vl1re16.v v15, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vl1re16.v v12, (a4)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vl1re16.v v13, (a3)
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: vl1re16.v v11, (a4)
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: vl1re16.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -14203,48 +14922,55 @@ define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv8bf16(<vscale x 8
; CHECK-NEXT: vmv1r.v v6, v19
; CHECK-NEXT: vmv1r.v v7, v31
; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vsseg8e16.v v1, (a1)
; CHECK-NEXT: vmv1r.v v25, v10
; CHECK-NEXT: vmv1r.v v27, v14
; CHECK-NEXT: vmv1r.v v29, v18
; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsseg8e16.v v24, (a0)
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re16.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re16.v v23, (t0)
-; CHECK-NEXT: vl1re16.v v20, (a6)
-; CHECK-NEXT: vl1re16.v v21, (a7)
+; CHECK-NEXT: slli a3, a2, 1
+; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl1re16.v v18, (a4)
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a5, a1, a4
; CHECK-NEXT: vl1re16.v v19, (a5)
; CHECK-NEXT: vl1re16.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re16.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re16.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re16.v v15, (a2)
-; CHECK-NEXT: vl1re16.v v12, (a3)
-; CHECK-NEXT: vl1re16.v v13, (a6)
-; CHECK-NEXT: vl1re16.v v10, (a4)
-; CHECK-NEXT: vl1re16.v v11, (a5)
+; CHECK-NEXT: add a5, a1, a2
+; CHECK-NEXT: vl1re16.v v17, (a5)
+; CHECK-NEXT: slli a5, a2, 2
+; CHECK-NEXT: add a6, a5, a3
+; CHECK-NEXT: add a7, a1, a6
+; CHECK-NEXT: vl1re16.v v22, (a7)
+; CHECK-NEXT: slli a7, a2, 3
+; CHECK-NEXT: sub a7, a7, a2
+; CHECK-NEXT: add t0, a1, a7
+; CHECK-NEXT: vl1re16.v v23, (t0)
+; CHECK-NEXT: add t0, a1, a5
+; CHECK-NEXT: vl1re16.v v20, (t0)
+; CHECK-NEXT: add t0, a5, a2
+; CHECK-NEXT: add a1, a1, t0
+; CHECK-NEXT: vl1re16.v v21, (a1)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vl1re16.v v10, (a3)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1re16.v v11, (a4)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl1re16.v v9, (a2)
+; CHECK-NEXT: add a6, a0, a6
+; CHECK-NEXT: vl1re16.v v14, (a6)
+; CHECK-NEXT: add a7, a0, a7
+; CHECK-NEXT: vl1re16.v v15, (a7)
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vl1re16.v v12, (a5)
+; CHECK-NEXT: add a0, a0, t0
+; CHECK-NEXT: vl1re16.v v13, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
@@ -14270,48 +14996,55 @@ define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv8bf16(<vscale x 8
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e16.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e16.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re16.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re16.v v23, (t0)
-; ZVBB-NEXT: vl1re16.v v20, (a6)
-; ZVBB-NEXT: vl1re16.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re16.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re16.v v19, (a5)
; ZVBB-NEXT: vl1re16.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re16.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re16.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re16.v v15, (a2)
-; ZVBB-NEXT: vl1re16.v v12, (a3)
-; ZVBB-NEXT: vl1re16.v v13, (a6)
-; ZVBB-NEXT: vl1re16.v v10, (a4)
-; ZVBB-NEXT: vl1re16.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re16.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re16.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re16.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re16.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re16.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re16.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re16.v v11, (a4)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re16.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re16.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re16.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re16.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -14333,27 +15066,31 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv1f32(<vscale x 1 x flo
; CHECK-NEXT: vsseg8e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: add a2, t0, a2
-; CHECK-NEXT: vle32.v v8, (a2)
-; CHECK-NEXT: vle32.v v11, (t0)
-; CHECK-NEXT: vle32.v v9, (a7)
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: sub a3, a3, a2
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vle32.v v8, (a3)
+; CHECK-NEXT: slli a3, a1, 1
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: add a5, a4, a3
+; CHECK-NEXT: vle32.v v11, (a5)
+; CHECK-NEXT: add a5, a3, a2
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vle32.v v9, (a5)
; CHECK-NEXT: srli a1, a1, 3
-; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a5, zero, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vx v11, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a6)
-; CHECK-NEXT: vle32.v v8, (a5)
-; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vsetvli a5, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v10, (a3)
+; CHECK-NEXT: add a3, a4, a2
+; CHECK-NEXT: vle32.v v8, (a3)
+; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vx v10, v9, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v9, (a4)
-; CHECK-NEXT: vle32.v v12, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle32.v v12, (a2)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v8, a1
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
@@ -14377,27 +15114,31 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg8e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: add a2, t0, a2
-; ZVBB-NEXT: vle32.v v8, (a2)
-; ZVBB-NEXT: vle32.v v11, (t0)
-; ZVBB-NEXT: vle32.v v9, (a7)
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: sub a3, a3, a2
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle32.v v8, (a3)
+; ZVBB-NEXT: slli a3, a1, 1
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: add a5, a4, a3
+; ZVBB-NEXT: vle32.v v11, (a5)
+; ZVBB-NEXT: add a5, a3, a2
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vle32.v v9, (a5)
; ZVBB-NEXT: srli a1, a1, 3
-; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vsetvli a5, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v11, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a6)
-; ZVBB-NEXT: vle32.v v8, (a5)
-; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vsetvli a5, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v10, (a3)
+; ZVBB-NEXT: add a3, a4, a2
+; ZVBB-NEXT: vle32.v v8, (a3)
+; ZVBB-NEXT: vsetvli a3, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v9, a1
-; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; ZVBB-NEXT: vle32.v v9, (a4)
-; ZVBB-NEXT: vle32.v v12, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle32.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
@@ -14424,21 +15165,26 @@ define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv2f32(<vscale x 2 x f
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vsseg8e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: add a4, a3, a1
-; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: add a6, a5, a1
-; CHECK-NEXT: add a7, a6, a1
-; CHECK-NEXT: vl1re32.v v14, (a7)
-; CHECK-NEXT: add a1, a7, a1
-; CHECK-NEXT: vl1re32.v v15, (a1)
-; CHECK-NEXT: vl1re32.v v12, (a5)
-; CHECK-NEXT: vl1re32.v v13, (a6)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1re32.v v14, (a4)
+; CHECK-NEXT: slli a4, a1, 3
+; CHECK-NEXT: sub a5, a0, a1
+; CHECK-NEXT: add a4, a5, a4
+; CHECK-NEXT: vl1re32.v v15, (a4)
+; CHECK-NEXT: add a4, a0, a3
+; CHECK-NEXT: vl1re32.v v12, (a4)
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: add a3, a1, a3
+; CHECK-NEXT: vl1re32.v v13, (a3)
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re32.v v10, (a3)
-; CHECK-NEXT: vl1re32.v v11, (a4)
+; CHECK-NEXT: add a2, a1, a2
+; CHECK-NEXT: vl1re32.v v11, (a2)
; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a2)
+; CHECK-NEXT: vl1re32.v v9, (a1)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -14455,21 +15201,26 @@ define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv2f32(<vscale x 2 x f
; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVBB-NEXT: vsseg8e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: add a4, a3, a1
-; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: add a6, a5, a1
-; ZVBB-NEXT: add a7, a6, a1
-; ZVBB-NEXT: vl1re32.v v14, (a7)
-; ZVBB-NEXT: add a1, a7, a1
-; ZVBB-NEXT: vl1re32.v v15, (a1)
-; ZVBB-NEXT: vl1re32.v v12, (a5)
-; ZVBB-NEXT: vl1re32.v v13, (a6)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re32.v v14, (a4)
+; ZVBB-NEXT: slli a4, a1, 3
+; ZVBB-NEXT: sub a5, a0, a1
+; ZVBB-NEXT: add a4, a5, a4
+; ZVBB-NEXT: vl1re32.v v15, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vl1re32.v v12, (a4)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vl1re32.v v13, (a3)
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re32.v v10, (a3)
-; ZVBB-NEXT: vl1re32.v v11, (a4)
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re32.v v11, (a2)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a2)
+; ZVBB-NEXT: vl1re32.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -14499,48 +15250,55 @@ define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv4f32(<vscale x 4 x f
; CHECK-NEXT: vmv1r.v v6, v19
; CHECK-NEXT: vmv1r.v v7, v31
; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vsseg8e32.v v1, (a1)
; CHECK-NEXT: vmv1r.v v25, v10
; CHECK-NEXT: vmv1r.v v27, v14
; CHECK-NEXT: vmv1r.v v29, v18
; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsseg8e32.v v24, (a0)
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re32.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re32.v v23, (t0)
-; CHECK-NEXT: vl1re32.v v20, (a6)
-; CHECK-NEXT: vl1re32.v v21, (a7)
+; CHECK-NEXT: slli a3, a2, 1
+; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl1re32.v v18, (a4)
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a5, a1, a4
; CHECK-NEXT: vl1re32.v v19, (a5)
; CHECK-NEXT: vl1re32.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re32.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re32.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re32.v v15, (a2)
-; CHECK-NEXT: vl1re32.v v12, (a3)
-; CHECK-NEXT: vl1re32.v v13, (a6)
-; CHECK-NEXT: vl1re32.v v10, (a4)
-; CHECK-NEXT: vl1re32.v v11, (a5)
+; CHECK-NEXT: add a5, a1, a2
+; CHECK-NEXT: vl1re32.v v17, (a5)
+; CHECK-NEXT: slli a5, a2, 2
+; CHECK-NEXT: add a6, a5, a3
+; CHECK-NEXT: add a7, a1, a6
+; CHECK-NEXT: vl1re32.v v22, (a7)
+; CHECK-NEXT: slli a7, a2, 3
+; CHECK-NEXT: sub a7, a7, a2
+; CHECK-NEXT: add t0, a1, a7
+; CHECK-NEXT: vl1re32.v v23, (t0)
+; CHECK-NEXT: add t0, a1, a5
+; CHECK-NEXT: vl1re32.v v20, (t0)
+; CHECK-NEXT: add t0, a5, a2
+; CHECK-NEXT: add a1, a1, t0
+; CHECK-NEXT: vl1re32.v v21, (a1)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vl1re32.v v10, (a3)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1re32.v v11, (a4)
; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl1re32.v v9, (a2)
+; CHECK-NEXT: add a6, a0, a6
+; CHECK-NEXT: vl1re32.v v14, (a6)
+; CHECK-NEXT: add a7, a0, a7
+; CHECK-NEXT: vl1re32.v v15, (a7)
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vl1re32.v v12, (a5)
+; CHECK-NEXT: add a0, a0, t0
+; CHECK-NEXT: vl1re32.v v13, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
@@ -14566,48 +15324,55 @@ define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv4f32(<vscale x 4 x f
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e32.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e32.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re32.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re32.v v23, (t0)
-; ZVBB-NEXT: vl1re32.v v20, (a6)
-; ZVBB-NEXT: vl1re32.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re32.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re32.v v19, (a5)
; ZVBB-NEXT: vl1re32.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re32.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re32.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re32.v v15, (a2)
-; ZVBB-NEXT: vl1re32.v v12, (a3)
-; ZVBB-NEXT: vl1re32.v v13, (a6)
-; ZVBB-NEXT: vl1re32.v v10, (a4)
-; ZVBB-NEXT: vl1re32.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re32.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re32.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re32.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re32.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re32.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re32.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re32.v v11, (a4)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re32.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re32.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re32.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re32.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re32.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -14628,21 +15393,26 @@ define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv1f64(<vscale x 1 x do
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vsseg8e64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: add a4, a3, a1
-; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: add a6, a5, a1
-; CHECK-NEXT: add a7, a6, a1
-; CHECK-NEXT: vl1re64.v v14, (a7)
-; CHECK-NEXT: add a1, a7, a1
-; CHECK-NEXT: vl1re64.v v15, (a1)
-; CHECK-NEXT: vl1re64.v v12, (a5)
-; CHECK-NEXT: vl1re64.v v13, (a6)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1re64.v v14, (a4)
+; CHECK-NEXT: slli a4, a1, 3
+; CHECK-NEXT: sub a5, a0, a1
+; CHECK-NEXT: add a4, a5, a4
+; CHECK-NEXT: vl1re64.v v15, (a4)
+; CHECK-NEXT: add a4, a0, a3
+; CHECK-NEXT: vl1re64.v v12, (a4)
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: add a3, a1, a3
+; CHECK-NEXT: vl1re64.v v13, (a3)
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re64.v v10, (a3)
-; CHECK-NEXT: vl1re64.v v11, (a4)
+; CHECK-NEXT: add a2, a1, a2
+; CHECK-NEXT: vl1re64.v v11, (a2)
; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a2)
+; CHECK-NEXT: vl1re64.v v9, (a1)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -14659,21 +15429,26 @@ define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; ZVBB-NEXT: vsseg8e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: add a4, a3, a1
-; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: add a6, a5, a1
-; ZVBB-NEXT: add a7, a6, a1
-; ZVBB-NEXT: vl1re64.v v14, (a7)
-; ZVBB-NEXT: add a1, a7, a1
-; ZVBB-NEXT: vl1re64.v v15, (a1)
-; ZVBB-NEXT: vl1re64.v v12, (a5)
-; ZVBB-NEXT: vl1re64.v v13, (a6)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re64.v v14, (a4)
+; ZVBB-NEXT: slli a4, a1, 3
+; ZVBB-NEXT: sub a5, a0, a1
+; ZVBB-NEXT: add a4, a5, a4
+; ZVBB-NEXT: vl1re64.v v15, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vl1re64.v v12, (a4)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vl1re64.v v13, (a3)
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re64.v v10, (a3)
-; ZVBB-NEXT: vl1re64.v v11, (a4)
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re64.v v11, (a2)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a2)
+; ZVBB-NEXT: vl1re64.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -14703,48 +15478,55 @@ define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv2f64(<vscale x 2 x
; CHECK-NEXT: vmv1r.v v6, v19
; CHECK-NEXT: vmv1r.v v7, v31
; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vsseg8e64.v v1, (a1)
; CHECK-NEXT: vmv1r.v v25, v10
; CHECK-NEXT: vmv1r.v v27, v14
; CHECK-NEXT: vmv1r.v v29, v18
; CHECK-NEXT: vmv1r.v v31, v22
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsseg8e64.v v24, (a0)
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: add t0, a7, a2
-; CHECK-NEXT: vl1re64.v v22, (t0)
-; CHECK-NEXT: add t0, t0, a2
-; CHECK-NEXT: vl1re64.v v23, (t0)
-; CHECK-NEXT: vl1re64.v v20, (a6)
-; CHECK-NEXT: vl1re64.v v21, (a7)
+; CHECK-NEXT: slli a3, a2, 1
+; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl1re64.v v18, (a4)
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a5, a1, a4
; CHECK-NEXT: vl1re64.v v19, (a5)
; CHECK-NEXT: vl1re64.v v16, (a1)
-; CHECK-NEXT: add a1, a0, a2
-; CHECK-NEXT: add a4, a1, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vl1re64.v v17, (a3)
-; CHECK-NEXT: add a3, a5, a2
-; CHECK-NEXT: add a6, a3, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vl1re64.v v14, (a7)
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vl1re64.v v15, (a2)
-; CHECK-NEXT: vl1re64.v v12, (a3)
-; CHECK-NEXT: vl1re64.v v13, (a6)
-; CHECK-NEXT: vl1re64.v v10, (a4)
-; CHECK-NEXT: vl1re64.v v11, (a5)
+; CHECK-NEXT: add a5, a1, a2
+; CHECK-NEXT: vl1re64.v v17, (a5)
+; CHECK-NEXT: slli a5, a2, 2
+; CHECK-NEXT: add a6, a5, a3
+; CHECK-NEXT: add a7, a1, a6
+; CHECK-NEXT: vl1re64.v v22, (a7)
+; CHECK-NEXT: slli a7, a2, 3
+; CHECK-NEXT: sub a7, a7, a2
+; CHECK-NEXT: add t0, a1, a7
+; CHECK-NEXT: vl1re64.v v23, (t0)
+; CHECK-NEXT: add t0, a1, a5
+; CHECK-NEXT: vl1re64.v v20, (t0)
+; CHECK-NEXT: add t0, a5, a2
+; CHECK-NEXT: add a1, a1, t0
+; CHECK-NEXT: vl1re64.v v21, (a1)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vl1re64.v v10, (a3)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1re64.v v11, (a4)
; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl1re64.v v9, (a2)
+; CHECK-NEXT: add a6, a0, a6
+; CHECK-NEXT: vl1re64.v v14, (a6)
+; CHECK-NEXT: add a7, a0, a7
+; CHECK-NEXT: vl1re64.v v15, (a7)
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vl1re64.v v12, (a5)
+; CHECK-NEXT: add a0, a0, t0
+; CHECK-NEXT: vl1re64.v v13, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
@@ -14770,48 +15552,55 @@ define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv2f64(<vscale x 2 x
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e64.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e64.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re64.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re64.v v23, (t0)
-; ZVBB-NEXT: vl1re64.v v20, (a6)
-; ZVBB-NEXT: vl1re64.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re64.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re64.v v19, (a5)
; ZVBB-NEXT: vl1re64.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re64.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re64.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re64.v v15, (a2)
-; ZVBB-NEXT: vl1re64.v v12, (a3)
-; ZVBB-NEXT: vl1re64.v v13, (a6)
-; ZVBB-NEXT: vl1re64.v v10, (a4)
-; ZVBB-NEXT: vl1re64.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re64.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re64.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re64.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re64.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re64.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re64.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re64.v v11, (a4)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re64.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re64.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re64.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re64.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re64.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -14847,9 +15636,11 @@ define <vscale x 4 x i16> @interleave2_diff_const_splat_nxv4i16() {
; V-NEXT: vmv.v.i v9, -1
; V-NEXT: vwmaccu.vx v8, a0, v9
; V-NEXT: csrr a0, vlenb
+; V-NEXT: srli a1, a0, 3
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; V-NEXT: vslidedown.vx v9, v8, a1
; V-NEXT: srli a0, a0, 2
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; V-NEXT: vslidedown.vx v9, v8, a0
; V-NEXT: vslideup.vx v8, v9, a0
; V-NEXT: ret
;
@@ -14861,9 +15652,11 @@ define <vscale x 4 x i16> @interleave2_diff_const_splat_nxv4i16() {
; ZVBB-NEXT: li a0, 3
; ZVBB-NEXT: vwaddu.wx v8, v9, a0
; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: srli a1, a0, 3
+; ZVBB-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslidedown.vx v9, v8, a1
; ZVBB-NEXT: srli a0, a0, 2
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslidedown.vx v9, v8, a0
; ZVBB-NEXT: vslideup.vx v8, v9, a0
; ZVBB-NEXT: ret
;
@@ -14873,11 +15666,6 @@ define <vscale x 4 x i16> @interleave2_diff_const_splat_nxv4i16() {
; ZVZIP-NEXT: vmv.v.i v9, 4
; ZVZIP-NEXT: vmv.v.i v10, 3
; ZVZIP-NEXT: vzip.vv v8, v10, v9
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: srli a0, a0, 2
-; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v9, v8, a0
-; ZVZIP-NEXT: vslideup.vx v8, v9, a0
; ZVZIP-NEXT: ret
%retval = call <vscale x 4 x i16> @llvm.vector.interleave2.v4i16(<vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 4))
ret <vscale x 4 x i16> %retval
@@ -14910,9 +15698,11 @@ define <vscale x 4 x i16> @interleave2_diff_nonconst_splat_nxv4i16(i16 %a, i16 %
; V-NEXT: vmv.v.i v9, -1
; V-NEXT: vwmaccu.vx v8, a1, v9
; V-NEXT: csrr a0, vlenb
+; V-NEXT: srli a1, a0, 3
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; V-NEXT: vslidedown.vx v9, v8, a1
; V-NEXT: srli a0, a0, 2
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; V-NEXT: vslidedown.vx v9, v8, a0
; V-NEXT: vslideup.vx v8, v9, a0
; V-NEXT: ret
;
@@ -14923,9 +15713,11 @@ define <vscale x 4 x i16> @interleave2_diff_nonconst_splat_nxv4i16(i16 %a, i16 %
; ZVBB-NEXT: vwsll.vi v9, v8, 16
; ZVBB-NEXT: vwaddu.wx v8, v9, a0
; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: srli a1, a0, 3
+; ZVBB-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslidedown.vx v9, v8, a1
; ZVBB-NEXT: srli a0, a0, 2
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslidedown.vx v9, v8, a0
; ZVBB-NEXT: vslideup.vx v8, v9, a0
; ZVBB-NEXT: ret
;
@@ -14935,11 +15727,6 @@ define <vscale x 4 x i16> @interleave2_diff_nonconst_splat_nxv4i16(i16 %a, i16 %
; ZVZIP-NEXT: vmv.v.x v9, a0
; ZVZIP-NEXT: vmv.v.x v10, a1
; ZVZIP-NEXT: vzip.vv v8, v9, v10
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: srli a0, a0, 2
-; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v9, v8, a0
-; ZVZIP-NEXT: vslideup.vx v8, v9, a0
; ZVZIP-NEXT: ret
%ins1 = insertelement <vscale x 2 x i16> poison, i16 %a, i32 0
%splat1 = shufflevector <vscale x 2 x i16> %ins1, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
index fd46b99bd98e3..a788376bd26ed 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
@@ -370,12 +370,15 @@ define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %
; RV32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: srli a2, a2, 2
-; RV32-NEXT: vslidedown.vx v11, v11, a2
+; RV32-NEXT: srli a3, a2, 3
+; RV32-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; RV32-NEXT: vslidedown.vx v11, v11, a3
+; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v11, 0
; RV32-NEXT: vmerge.vim v9, v9, 1, v0
+; RV32-NEXT: srli a2, a2, 2
; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vx v10, v9, a2
; RV32-NEXT: slli a2, a1, 1
@@ -405,12 +408,15 @@ define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %
; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: srli a2, a2, 2
-; RV64-NEXT: vslidedown.vx v11, v11, a2
+; RV64-NEXT: srli a3, a2, 3
+; RV64-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; RV64-NEXT: vslidedown.vx v11, v11, a3
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV64-NEXT: vmsne.vi v0, v11, 0
; RV64-NEXT: vmerge.vim v9, v9, 1, v0
+; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vslideup.vx v10, v9, a2
; RV64-NEXT: slli a2, a1, 33
@@ -591,12 +597,15 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: srli a2, a2, 2
-; RV32-NEXT: vslidedown.vx v9, v11, a2
+; RV32-NEXT: srli a3, a2, 3
+; RV32-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; RV32-NEXT: vslidedown.vx v9, v11, a3
+; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v9, 0
; RV32-NEXT: vmerge.vim v9, v10, 1, v0
+; RV32-NEXT: srli a2, a2, 2
; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vx v8, v9, a2
; RV32-NEXT: slli a1, a1, 1
@@ -625,12 +634,15 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: srli a2, a2, 2
-; RV64-NEXT: vslidedown.vx v9, v11, a2
+; RV64-NEXT: srli a3, a2, 3
+; RV64-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; RV64-NEXT: vslidedown.vx v9, v11, a3
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV64-NEXT: vmsne.vi v0, v9, 0
; RV64-NEXT: vmerge.vim v9, v10, 1, v0
+; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vslideup.vx v8, v9, a2
; RV64-NEXT: slli a1, a1, 33
diff --git a/llvm/test/CodeGen/X86/vector-deinterleave-intrinsics.ll b/llvm/test/CodeGen/X86/vector-deinterleave-intrinsics.ll
new file mode 100644
index 0000000000000..ad94331638afd
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-deinterleave-intrinsics.ll
@@ -0,0 +1,386 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define void @deinterleave2(ptr %src, ptr %dst0, ptr %dst1) {
+; CHECK-LABEL: deinterleave2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps (%rdi), %xmm0
+; CHECK-NEXT: movaps 16(%rdi), %xmm1
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm1[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movaps %xmm2, (%rdx)
+; CHECK-NEXT: retq
+ %wide = load <8 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32> } %result, 1
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ ret void
+}
+
+define void @deinterleave3(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2) {
+; CHECK-LABEL: deinterleave3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa (%rdi), %xmm0
+; CHECK-NEXT: movdqa 16(%rdi), %xmm1
+; CHECK-NEXT: movdqa 32(%rdi), %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm1[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm0[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm2[0,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[0,1]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movdqa %xmm3, (%rdx)
+; CHECK-NEXT: movaps %xmm5, (%rcx)
+; CHECK-NEXT: retq
+ %wide = load <12 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave3.v12i32(<12 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ ret void
+}
+
+define void @deinterleave4(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3) {
+; CHECK-LABEL: deinterleave4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps (%rdi), %xmm0
+; CHECK-NEXT: movaps 16(%rdi), %xmm1
+; CHECK-NEXT: movaps 32(%rdi), %xmm2
+; CHECK-NEXT: movaps 48(%rdi), %xmm3
+; CHECK-NEXT: movaps %xmm2, %xmm4
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,3],xmm3[1,3]
+; CHECK-NEXT: movaps %xmm0, %xmm5
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,3],xmm1[1,3]
+; CHECK-NEXT: movaps %xmm5, %xmm6
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,3],xmm4[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
+; CHECK-NEXT: movaps %xmm0, %xmm1
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm4[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movaps %xmm5, (%rdx)
+; CHECK-NEXT: movaps %xmm1, (%rcx)
+; CHECK-NEXT: movaps %xmm6, (%r8)
+; CHECK-NEXT: retq
+ %wide = load <16 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave4.v16i32(<16 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ ret void
+}
+
+define void @deinterleave5(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4) {
+; CHECK-LABEL: deinterleave5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa 64(%rdi), %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm1[3,3,3,3]
+; CHECK-NEXT: movdqa (%rdi), %xmm0
+; CHECK-NEXT: movdqa 16(%rdi), %xmm4
+; CHECK-NEXT: movdqa 32(%rdi), %xmm2
+; CHECK-NEXT: movdqa 48(%rdi), %xmm3
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm3[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm4[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm4[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm4[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm1[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm1[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm3[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm6[0],xmm3[1],xmm6[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm0[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm3[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm8[0],xmm1[1],xmm8[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm10[0],xmm2[1],xmm10[1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm9[0],xmm0[1],xmm9[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT: movdqa %xmm0, (%rsi)
+; CHECK-NEXT: movdqa %xmm1, (%rdx)
+; CHECK-NEXT: movdqa %xmm6, (%rcx)
+; CHECK-NEXT: movdqa %xmm5, (%r8)
+; CHECK-NEXT: movdqa %xmm4, (%r9)
+; CHECK-NEXT: retq
+ %wide = load <20 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave5.v20i32(<20 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ ret void
+}
+
+define void @deinterleave6(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4, ptr %dst5) {
+; CHECK-LABEL: deinterleave6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movdqa 80(%rdi), %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
+; CHECK-NEXT: movdqa 64(%rdi), %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm5[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1]
+; CHECK-NEXT: movdqa (%rdi), %xmm0
+; CHECK-NEXT: movdqa 16(%rdi), %xmm3
+; CHECK-NEXT: movdqa 32(%rdi), %xmm6
+; CHECK-NEXT: movdqa 48(%rdi), %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm1[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm5[0],xmm8[1],xmm5[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm4[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm6[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm3[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm4[0],xmm7[1],xmm4[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm7[0]
+; CHECK-NEXT: movdqa %xmm4, %xmm7
+; CHECK-NEXT: shufps {{.*#+}} xmm7 = xmm7[1,3],xmm8[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2],xmm8[0,2]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm5[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm1[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm8[0],xmm9[1],xmm8[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,1],xmm2[0,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm3[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm0[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm8[0],xmm10[1],xmm8[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm10 = xmm10[0,1],xmm6[0,3]
+; CHECK-NEXT: movaps %xmm10, %xmm8
+; CHECK-NEXT: shufps {{.*#+}} xmm8 = xmm8[1,3],xmm9[1,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,3],xmm5[0,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm6[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm3[0,1]
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm1[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm10 = xmm10[0,2],xmm9[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movaps %xmm4, (%rdx)
+; CHECK-NEXT: movaps %xmm10, (%rcx)
+; CHECK-NEXT: movaps %xmm2, (%r8)
+; CHECK-NEXT: movaps %xmm7, (%r9)
+; CHECK-NEXT: movaps %xmm8, (%rax)
+; CHECK-NEXT: retq
+ %wide = load <24 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave6.v24i32(<24 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ %v5 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 5
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ store <4 x i32> %v5, ptr %dst5
+ ret void
+}
+
+define void @deinterleave7(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4, ptr %dst5, ptr %dst6) {
+; CHECK-LABEL: deinterleave7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa 80(%rdi), %xmm6
+; CHECK-NEXT: movdqa 96(%rdi), %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm6[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm6[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[1]
+; CHECK-NEXT: movdqa (%rdi), %xmm2
+; CHECK-NEXT: movdqa 16(%rdi), %xmm9
+; CHECK-NEXT: movdqa 32(%rdi), %xmm8
+; CHECK-NEXT: movdqa 48(%rdi), %xmm7
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm7[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm9[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm10[0],xmm1[1],xmm10[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm6[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm0[2,3,2,3]
+; CHECK-NEXT: movdqa 64(%rdi), %xmm10
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm10[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm11 = xmm11[0],xmm6[0],xmm11[1],xmm6[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm9[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm11[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm0[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm12 = xmm10[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm12 = xmm12[0],xmm11[0],xmm12[1],xmm11[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm8[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm13 = xmm9[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm11[0],xmm9[1],xmm11[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm12[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm10[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm11 = xmm11[0],xmm0[0],xmm11[1],xmm0[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm8[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm12 = xmm2[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm12 = xmm12[0],xmm0[0],xmm12[1],xmm0[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm12 = xmm12[0],xmm11[0]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm3[0],xmm10[1],xmm3[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm8[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm10[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm7[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm8[0],xmm4[1],xmm8[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm0[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm7[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm13[0],xmm2[1],xmm13[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; CHECK-NEXT: movdqa %xmm2, (%rsi)
+; CHECK-NEXT: movdqa %xmm4, (%rdx)
+; CHECK-NEXT: movdqa %xmm3, (%rcx)
+; CHECK-NEXT: movdqa %xmm12, (%r8)
+; CHECK-NEXT: movdqa %xmm9, (%r9)
+; CHECK-NEXT: movdqa %xmm6, (%rdi)
+; CHECK-NEXT: movdqa %xmm1, (%rax)
+; CHECK-NEXT: retq
+ %wide = load <28 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave7.v28i32(<28 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ %v5 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 5
+ %v6 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 6
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ store <4 x i32> %v5, ptr %dst5
+ store <4 x i32> %v6, ptr %dst6
+ ret void
+}
+
+define void @deinterleave8(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4, ptr %dst5, ptr %dst6, ptr %dst7) {
+; CHECK-LABEL: deinterleave8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: movaps 112(%rdi), %xmm10
+; CHECK-NEXT: movaps 96(%rdi), %xmm4
+; CHECK-NEXT: movaps %xmm4, %xmm8
+; CHECK-NEXT: shufps {{.*#+}} xmm8 = xmm8[1,3],xmm10[1,3]
+; CHECK-NEXT: movaps 80(%rdi), %xmm11
+; CHECK-NEXT: movaps 64(%rdi), %xmm0
+; CHECK-NEXT: movaps %xmm0, %xmm1
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm11[1,3]
+; CHECK-NEXT: movaps %xmm1, %xmm5
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,3],xmm8[1,3]
+; CHECK-NEXT: movaps (%rdi), %xmm2
+; CHECK-NEXT: movaps 16(%rdi), %xmm12
+; CHECK-NEXT: movaps 32(%rdi), %xmm9
+; CHECK-NEXT: movaps 48(%rdi), %xmm13
+; CHECK-NEXT: movaps %xmm9, %xmm14
+; CHECK-NEXT: shufps {{.*#+}} xmm14 = xmm14[1,3],xmm13[1,3]
+; CHECK-NEXT: movaps %xmm2, %xmm6
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,3],xmm12[1,3]
+; CHECK-NEXT: movaps %xmm6, %xmm7
+; CHECK-NEXT: shufps {{.*#+}} xmm7 = xmm7[1,3],xmm14[1,3]
+; CHECK-NEXT: movaps %xmm7, %xmm3
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,3],xmm5[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2],xmm10[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm11[0,2]
+; CHECK-NEXT: movaps %xmm0, %xmm10
+; CHECK-NEXT: shufps {{.*#+}} xmm10 = xmm10[1,3],xmm4[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,2],xmm13[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm12[0,2]
+; CHECK-NEXT: movaps %xmm2, %xmm11
+; CHECK-NEXT: shufps {{.*#+}} xmm11 = xmm11[1,3],xmm9[1,3]
+; CHECK-NEXT: movaps %xmm11, %xmm12
+; CHECK-NEXT: shufps {{.*#+}} xmm12 = xmm12[1,3],xmm10[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm8[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2],xmm14[0,2]
+; CHECK-NEXT: movaps %xmm6, %xmm8
+; CHECK-NEXT: shufps {{.*#+}} xmm8 = xmm8[1,3],xmm1[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm4[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm9[0,2]
+; CHECK-NEXT: movaps %xmm2, %xmm4
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,3],xmm0[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,2],xmm5[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm11 = xmm11[0,2],xmm10[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2],xmm1[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[0,2]
+; CHECK-NEXT: movaps %xmm2, (%rsi)
+; CHECK-NEXT: movaps %xmm6, (%rdx)
+; CHECK-NEXT: movaps %xmm11, (%rcx)
+; CHECK-NEXT: movaps %xmm7, (%r8)
+; CHECK-NEXT: movaps %xmm4, (%r9)
+; CHECK-NEXT: movaps %xmm8, (%r11)
+; CHECK-NEXT: movaps %xmm12, (%r10)
+; CHECK-NEXT: movaps %xmm3, (%rax)
+; CHECK-NEXT: retq
+ %wide = load <32 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave8.v32i32(<32 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ %v5 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 5
+ %v6 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 6
+ %v7 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 7
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ store <4 x i32> %v5, ptr %dst5
+ store <4 x i32> %v6, ptr %dst6
+ store <4 x i32> %v7, ptr %dst7
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll b/llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll
new file mode 100644
index 0000000000000..328886432d07d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll
@@ -0,0 +1,274 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define void @interleave2(ptr %dst, <4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: interleave2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm0, 16(%rdi)
+; CHECK-NEXT: movaps %xmm2, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %v0, <4 x i32> %v1)
+ store <8 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave3(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: interleave3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm2[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm2[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; CHECK-NEXT: movdqa %xmm0, %xmm3
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm4[0],xmm6[1],xmm4[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm0[0]
+; CHECK-NEXT: movdqa %xmm6, 32(%rdi)
+; CHECK-NEXT: movdqa %xmm2, 16(%rdi)
+; CHECK-NEXT: movdqa %xmm3, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <12 x i32> @llvm.vector.interleave3.v12i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2)
+ store <12 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave4(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
+; CHECK-LABEL: interleave4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm1, %xmm4
+; CHECK-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
+; CHECK-NEXT: movaps %xmm0, %xmm5
+; CHECK-NEXT: unpcklps {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
+; CHECK-NEXT: movaps %xmm5, %xmm6
+; CHECK-NEXT: unpcklps {{.*#+}} xmm6 = xmm6[0],xmm4[0],xmm6[1],xmm4[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm5 = xmm5[2],xmm4[2],xmm5[3],xmm4[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm1 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm0, 48(%rdi)
+; CHECK-NEXT: movaps %xmm2, 32(%rdi)
+; CHECK-NEXT: movaps %xmm5, 16(%rdi)
+; CHECK-NEXT: movaps %xmm6, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <16 x i32> @llvm.vector.interleave4.v16i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3)
+ store <16 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave5(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4) {
+; CHECK-LABEL: interleave5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm1[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm0[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm4[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm4[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm4[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm6[0]
+; CHECK-NEXT: movdqa %xmm0, %xmm5
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm5 = xmm5[2],xmm1[2],xmm5[3],xmm1[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm5[0]
+; CHECK-NEXT: movdqa %xmm2, %xmm5
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm5 = xmm5[2],xmm3[2],xmm5[3],xmm3[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm8[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm3[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm9[0],xmm7[1],xmm9[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm2[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm1[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm8[0],xmm9[1],xmm8[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm7[0]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT: movdqa %xmm0, (%rdi)
+; CHECK-NEXT: movdqa %xmm9, 64(%rdi)
+; CHECK-NEXT: movdqa %xmm5, 48(%rdi)
+; CHECK-NEXT: movdqa %xmm6, 32(%rdi)
+; CHECK-NEXT: movdqa %xmm4, 16(%rdi)
+; CHECK-NEXT: retq
+ %result = call <20 x i32> @llvm.vector.interleave5.v20i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4)
+ store <20 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave6(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5) {
+; CHECK-LABEL: interleave6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa %xmm4, %xmm6
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm1[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm0[1,1,1,1]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm8 = xmm8[2],xmm7[2],xmm8[3],xmm7[3]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm8[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm5[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm4[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm3[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm2[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm9[0],xmm7[1],xmm9[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm8[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm4[3,3,3,3]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm5[2],xmm4[3],xmm5[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm1[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm10 = xmm10[2],xmm9[2],xmm10[3],xmm9[3]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm10[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm5[0],xmm8[1],xmm5[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm3[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm2[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm5[0],xmm9[1],xmm5[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm8[0]
+; CHECK-NEXT: movdqa %xmm2, %xmm5
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1]
+; CHECK-NEXT: movdqa %xmm0, %xmm8
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm1[0],xmm8[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm5[0]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT: movdqa %xmm0, 48(%rdi)
+; CHECK-NEXT: movdqa %xmm8, (%rdi)
+; CHECK-NEXT: movdqa %xmm9, 80(%rdi)
+; CHECK-NEXT: movdqa %xmm4, 64(%rdi)
+; CHECK-NEXT: movdqa %xmm7, 32(%rdi)
+; CHECK-NEXT: movdqa %xmm6, 16(%rdi)
+; CHECK-NEXT: retq
+ %result = call <24 x i32> @llvm.vector.interleave6.v24i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5)
+ store <24 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave7(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6) {
+; CHECK-LABEL: interleave7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa %xmm4, %xmm7
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm0[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm6[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm6[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm6[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm9[0],xmm6[1],xmm9[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm6[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm3[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm6[0],xmm9[1],xmm6[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm12 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm1[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm12[0],xmm6[1],xmm12[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm9[0]
+; CHECK-NEXT: movdqa %xmm0, %xmm12
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm12 = xmm12[2],xmm1[2],xmm12[3],xmm1[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm5[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm10[0],xmm9[1],xmm10[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm12[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm2[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm12 = xmm1[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm12 = xmm12[0],xmm10[0],xmm12[1],xmm10[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm10[0],xmm8[1],xmm10[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm12[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm5[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm11[0],xmm10[1],xmm11[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm4[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm12 = xmm3[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm12 = xmm12[0],xmm11[0],xmm12[1],xmm11[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm12 = xmm12[0],xmm10[0]
+; CHECK-NEXT: movdqa %xmm2, %xmm10
+; CHECK-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm3[0],xmm10[1],xmm3[1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm10[0]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm5[2],xmm4[3],xmm5[3]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
+; CHECK-NEXT: movdqa %xmm2, 64(%rdi)
+; CHECK-NEXT: movdqa %xmm0, (%rdi)
+; CHECK-NEXT: movdqa %xmm12, 96(%rdi)
+; CHECK-NEXT: movdqa %xmm8, 80(%rdi)
+; CHECK-NEXT: movdqa %xmm9, 48(%rdi)
+; CHECK-NEXT: movdqa %xmm6, 32(%rdi)
+; CHECK-NEXT: movdqa %xmm7, 16(%rdi)
+; CHECK-NEXT: retq
+ %result = call <28 x i32> @llvm.vector.interleave7.v28i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6)
+ store <28 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave8(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7) {
+; CHECK-LABEL: interleave8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm3, %xmm11
+; CHECK-NEXT: unpcklps {{.*#+}} xmm11 = xmm11[0],xmm7[0],xmm11[1],xmm7[1]
+; CHECK-NEXT: movaps %xmm1, %xmm12
+; CHECK-NEXT: unpcklps {{.*#+}} xmm12 = xmm12[0],xmm5[0],xmm12[1],xmm5[1]
+; CHECK-NEXT: movaps %xmm12, %xmm13
+; CHECK-NEXT: unpcklps {{.*#+}} xmm13 = xmm13[0],xmm11[0],xmm13[1],xmm11[1]
+; CHECK-NEXT: movaps %xmm2, %xmm14
+; CHECK-NEXT: unpcklps {{.*#+}} xmm14 = xmm14[0],xmm6[0],xmm14[1],xmm6[1]
+; CHECK-NEXT: movaps %xmm0, %xmm9
+; CHECK-NEXT: unpcklps {{.*#+}} xmm9 = xmm9[0],xmm4[0],xmm9[1],xmm4[1]
+; CHECK-NEXT: movaps %xmm9, %xmm8
+; CHECK-NEXT: unpcklps {{.*#+}} xmm8 = xmm8[0],xmm14[0],xmm8[1],xmm14[1]
+; CHECK-NEXT: movaps %xmm8, %xmm10
+; CHECK-NEXT: unpcklps {{.*#+}} xmm10 = xmm10[0],xmm13[0],xmm10[1],xmm13[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm8 = xmm8[2],xmm13[2],xmm8[3],xmm13[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm12 = xmm12[2],xmm11[2],xmm12[3],xmm11[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm9 = xmm9[2],xmm14[2],xmm9[3],xmm14[3]
+; CHECK-NEXT: movaps %xmm9, %xmm11
+; CHECK-NEXT: unpcklps {{.*#+}} xmm11 = xmm11[0],xmm12[0],xmm11[1],xmm12[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm9 = xmm9[2],xmm12[2],xmm9[3],xmm12[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm3 = xmm3[2],xmm7[2],xmm3[3],xmm7[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm1 = xmm1[2],xmm5[2],xmm1[3],xmm5[3]
+; CHECK-NEXT: movaps %xmm1, %xmm5
+; CHECK-NEXT: unpcklps {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm2 = xmm2[2],xmm6[2],xmm2[3],xmm6[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm4[2],xmm0[3],xmm4[3]
+; CHECK-NEXT: movaps %xmm0, %xmm4
+; CHECK-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
+; CHECK-NEXT: movaps %xmm4, %xmm6
+; CHECK-NEXT: unpcklps {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm4 = xmm4[2],xmm5[2],xmm4[3],xmm5[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm1 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm0, 112(%rdi)
+; CHECK-NEXT: movaps %xmm2, 96(%rdi)
+; CHECK-NEXT: movaps %xmm4, 80(%rdi)
+; CHECK-NEXT: movaps %xmm6, 64(%rdi)
+; CHECK-NEXT: movaps %xmm9, 48(%rdi)
+; CHECK-NEXT: movaps %xmm11, 32(%rdi)
+; CHECK-NEXT: movaps %xmm8, 16(%rdi)
+; CHECK-NEXT: movaps %xmm10, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <32 x i32> @llvm.vector.interleave8.v32i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7)
+ store <32 x i32> %result, ptr %dst
+ ret void
+}
>From 8ee6f6a23b86ba4b915f404aaacd06ebe1b9d4c9 Mon Sep 17 00:00:00 2001
From: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: Mon, 7 Sep 2026 12:15:52 +0000
Subject: [PATCH 2/2] Fix riscv interleave regressions
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 27 +
.../rvv/fixed-vectors-interleave-store.ll | 59 +-
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 35 +-
.../RISCV/rvv/vector-interleave-fixed.ll | 653 +++++-------------
4 files changed, 222 insertions(+), 552 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d49991e65b162..66482e5c527f5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -22895,6 +22895,33 @@ static SDValue performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG,
if (!TLI.isTypeLegal(VT))
return SDValue();
+ // If inputs of concat_vectors are output of 2 way interleave
+ // transform it to wider shuffle for fixed length vector.
+ // i.e.
+ // concat_vectors((vector_interleave X, Y):0,
+ // (vector_interleave X, Y):1)
+ // --> vector_shuffle(concat_vectors(X, Y), undef,
+ // <0, N, 1, N + 1, ...>)
+ if (N->getNumOperands() == 2) {
+ SDValue Lo = N->getOperand(0);
+ SDValue Hi = N->getOperand(1);
+ SDNode *Interleave = Lo.getNode();
+ EVT PartVT = Lo.getValueType();
+ if (PartVT.isFixedLengthVector() &&
+ Lo.getOpcode() == ISD::VECTOR_INTERLEAVE &&
+ Hi.getNode() == Interleave && Interleave->getNumOperands() == 2 &&
+ Lo.hasOneUse() && Hi.hasOneUse() &&
+ TLI.getVectorInterleaveAction(ISD::VECTOR_INTERLEAVE, 2, PartVT) ==
+ TargetLowering::Expand) {
+ unsigned NumElts = PartVT.getVectorNumElements();
+ SDValue Concat =
+ DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Interleave->getOperand(0),
+ Interleave->getOperand(1));
+ return DAG.getVectorShuffle(VT, DL, Concat, DAG.getUNDEF(VT),
+ createInterleaveMask(NumElts, 2));
+ }
+ }
+
// TODO: Potentially extend this to scalable vectors
if (VT.isScalableVector())
return SDValue();
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
index 34f57538deb41..a5971fb1f0310 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
@@ -9,39 +9,21 @@
define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr %p) {
; CHECK-LABEL: vector_interleave_store_v32i1_v16i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: lui a1, 11
-; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
-; CHECK-NEXT: addi a1, a1, -1366
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a1
-; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 8
-; CHECK-NEXT: vslidedown.vi v11, v9, 8
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v10
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v10, v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v9, v11
-; CHECK-NEXT: vsll.vi v11, v12, 8
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v10, a1, v8
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
-; CHECK-NEXT: vmsne.vi v9, v10, 0
-; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vslideup.vi v9, v8, 2
+; CHECK-NEXT: vslideup.vi v0, v8, 2
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vsm.v v9, (a0)
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 16
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vwaddu.vv v12, v8, v10
+; CHECK-NEXT: li a2, -1
+; CHECK-NEXT: vwmaccu.vx v12, a2, v10
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vmsne.vi v8, v12, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
store <32 x i1> %res, ptr %p
@@ -52,25 +34,10 @@ define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr
define void @vector_interleave_store_v16i16_v8i16_align1(<8 x i16> %a, <8 x i16> %b, ptr %p) {
; CHECK-LABEL: vector_interleave_store_v16i16_v8i16_align1:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 170
-; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a1
-; CHECK-NEXT: vslidedown.vi v10, v8, 4
-; CHECK-NEXT: vslidedown.vi v11, v9, 4
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v10
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsll.vi v8, v13, 16
; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a1, v9
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v8, 8
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vse8.v v10, (a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index 5de1c9f539891..688bb0cf7462b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -3799,47 +3799,18 @@ define <16 x float> @deinterleave_interleave2(<16 x float> %arg) {
; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; V-NEXT: vnsrl.wx v12, v8, a0
; V-NEXT: vnsrl.wi v14, v8, 0
-; V-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; V-NEXT: vslidedown.vi v8, v12, 4
-; V-NEXT: vslidedown.vi v10, v14, 4
-; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; V-NEXT: vzext.vf2 v16, v8
-; V-NEXT: vsll.vx v16, v16, a0
-; V-NEXT: li a0, 170
-; V-NEXT: vmv.s.x v0, a0
-; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; V-NEXT: vwaddu.vv v8, v14, v12
-; V-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; V-NEXT: vzext.vf2 v14, v10
; V-NEXT: li a0, -1
-; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; V-NEXT: vwmaccu.vx v8, a0, v12
-; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; V-NEXT: vmerge.vvm v12, v14, v16, v0
-; V-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; V-NEXT: vslideup.vi v8, v12, 8
; V-NEXT: ret
;
; ZVZIP-LABEL: deinterleave_interleave2:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: li a0, 32
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vnsrl.wx v14, v8, a0
-; ZVZIP-NEXT: vnsrl.wi v16, v8, 0
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v8, v14, 4
-; ZVZIP-NEXT: vslidedown.vi v10, v16, 4
-; ZVZIP-NEXT: li a0, 170
-; ZVZIP-NEXT: vmv.s.x v0, a0
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v12, v9, v8
-; ZVZIP-NEXT: vzip.vv v8, v10, v11
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vmerge.vvm v12, v8, v12, v0
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v16, v14
-; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 8
+; ZVZIP-NEXT: vnsrl.wx v12, v8, a0
+; ZVZIP-NEXT: vnsrl.wi v14, v8, 0
+; ZVZIP-NEXT: vzip.vv v8, v14, v12
; ZVZIP-NEXT: ret
entry:
%0 = call { <8 x float>, <8 x float> } @llvm.vector.deinterleave2.v16f32(<16 x float> %arg)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index d20c4b7fb661c..97c980714f7b1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -11,92 +11,53 @@
define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; CHECK-LABEL: vector_interleave_v32i1_v16i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: lui a0, 11
-; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
-; CHECK-NEXT: addi a0, a0, -1366
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 8
-; CHECK-NEXT: vslidedown.vi v11, v9, 8
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v10
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v10, v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v9, v11
-; CHECK-NEXT: vsll.vi v11, v12, 8
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v10, a0, v8
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v8, 2
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 16
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vwaddu.vv v12, v8, v10
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vwmaccu.vx v12, a1, v10
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v32i1_v16i1:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVBB-NEXT: vmv.v.i v9, 0
-; ZVBB-NEXT: vmerge.vim v10, v9, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: lui a0, 11
-; ZVBB-NEXT: vmerge.vim v8, v9, 1, v0
-; ZVBB-NEXT: addi a0, a0, -1366
-; ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVBB-NEXT: vmv.s.x v0, a0
-; ZVBB-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; ZVBB-NEXT: vslidedown.vi v9, v10, 8
-; ZVBB-NEXT: vslidedown.vi v11, v8, 8
-; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v9
-; ZVBB-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vi v9, v8, 8
-; ZVBB-NEXT: vwaddu.wv v9, v9, v10
-; ZVBB-NEXT: vwsll.vi v8, v11, 8
-; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v8, v12, v8, v0
-; ZVBB-NEXT: vmsne.vi v0, v9, 0
-; ZVBB-NEXT: vmsne.vi v8, v8, 0
; ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVBB-NEXT: vslideup.vi v0, v8, 2
+; ZVBB-NEXT: li a0, 32
+; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVBB-NEXT: vmv.v.i v8, 0
+; ZVBB-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVBB-NEXT: vsetivli zero, 16, e8, m2, ta, ma
+; ZVBB-NEXT: vslidedown.vi v10, v8, 16
+; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVBB-NEXT: vwsll.vi v12, v10, 8
+; ZVBB-NEXT: vwaddu.wv v12, v12, v8
+; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVBB-NEXT: vmsne.vi v0, v12, 0
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v32i1_v16i1:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v9, v0
-; ZVZIP-NEXT: vmv.v.i v10, 0
-; ZVZIP-NEXT: vmv1r.v v0, v8
-; ZVZIP-NEXT: vmerge.vim v8, v10, 1, v0
-; ZVZIP-NEXT: vmv1r.v v0, v9
-; ZVZIP-NEXT: lui a0, 11
-; ZVZIP-NEXT: vmerge.vim v9, v10, 1, v0
-; ZVZIP-NEXT: addi a0, a0, -1366
-; ZVZIP-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVZIP-NEXT: vmv.s.x v0, a0
-; ZVZIP-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v10, v8, 8
-; ZVZIP-NEXT: vslidedown.vi v11, v9, 8
-; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v13, v12, v10
-; ZVZIP-NEXT: vzip.vv v12, v11, v10
-; ZVZIP-NEXT: vzip.vv v10, v9, v8
-; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVZIP-NEXT: vmerge.vvm v8, v12, v13, v0
-; ZVZIP-NEXT: vmsne.vi v0, v10, 0
-; ZVZIP-NEXT: vmsne.vi v8, v8, 0
; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVZIP-NEXT: vslideup.vi v0, v8, 2
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-NEXT: vmv.v.i v8, 0
+; ZVZIP-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 16
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-NEXT: vmsne.vi v0, v12, 0
; ZVZIP-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
ret <32 x i1> %res
@@ -105,64 +66,29 @@ define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: vector_interleave_v16i16_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vslidedown.vi v8, v8, 4
-; CHECK-NEXT: vslidedown.vi v11, v9, 4
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsll.vi v10, v13, 16
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v8, a0, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v8
+; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16i16_v8i16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v8
-; ZVBB-NEXT: li a0, 170
-; ZVBB-NEXT: vmv.s.x v0, a0
-; ZVBB-NEXT: vslidedown.vi v8, v8, 4
-; ZVBB-NEXT: vslidedown.vi v11, v9, 4
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v8
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vi v8, v9, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v10
-; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
-; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 8
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: vwsll.vi v8, v10, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16i16_v8i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: li a0, 170
-; ZVZIP-NEXT: vmv.s.x v0, a0
-; ZVZIP-NEXT: vslidedown.vi v8, v9, 4
-; ZVZIP-NEXT: vslidedown.vi v11, v10, 4
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v13, v12, v8
-; ZVZIP-NEXT: vzip.vv v12, v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v10, v9
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vmerge.vvm v10, v12, v13, v0
-; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 8
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
%res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)
ret <16 x i16> %res
@@ -171,63 +97,30 @@ define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: vector_interleave_v8i32_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-NEXT: vslidedown.vi v11, v10, 2
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vmv.v.i v0, 10
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT: vsll.vx v10, v12, a0
-; CHECK-NEXT: vzext.vf2 v12, v11
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v8, a0, v9
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v8
+; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8i32_v4i32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v8
-; ZVBB-NEXT: vslidedown.vi v8, v8, 2
-; ZVBB-NEXT: vmv.v.i v0, 10
-; ZVBB-NEXT: vslidedown.vi v11, v9, 2
-; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v8
-; ZVBB-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vx v8, v9, a0
-; ZVBB-NEXT: vwaddu.wv v8, v8, v10
-; ZVBB-NEXT: vwsll.vx v9, v11, a0
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
-; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: li a0, 32
+; ZVBB-NEXT: vwsll.vx v8, v10, a0
+; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8i32_v4i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslidedown.vi v8, v9, 2
-; ZVZIP-NEXT: vslidedown.vi v11, v10, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v13, v12, v8
-; ZVZIP-NEXT: vzip.vv v12, v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v10, v9
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vmerge.vvm v10, v12, v13, v0
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)
ret <8 x i32> %res
@@ -236,33 +129,40 @@ define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: vector_interleave_v4i64_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v0, 1
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: lui a0, 12304
+; CHECK-NEXT: addi a0, a0, 512
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsext.vf2 v12, v10
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
+; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4i64_v2i64:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; ZVBB-NEXT: vmv.v.i v0, 1
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; ZVBB-NEXT: vslideup.vi v8, v9, 1
; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v9
; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: lui a0, 12304
+; ZVBB-NEXT: addi a0, a0, 512
+; ZVBB-NEXT: vmv.s.x v10, a0
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vsext.vf2 v12, v10
+; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
+; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4i64_v2i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVZIP-NEXT: vpairo.vv v10, v8, v9
-; ZVZIP-NEXT: vslideup.vi v8, v9, 1
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
%res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
ret <4 x i64> %res
@@ -699,34 +599,25 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: vector_interleave_v4f16_v2f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v0, 1
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v10, a0, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f16_v2f16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; ZVBB-NEXT: vmv.v.i v0, 1
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; ZVBB-NEXT: vslideup.vi v8, v9, 1
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v10, v9, 16
+; ZVBB-NEXT: vwaddu.wv v10, v10, v8
+; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f16_v2f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vpairo.vv v11, v8, v9
-; ZVZIP-NEXT: vslideup.vi v10, v9, 1
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 2
+; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
%res = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b)
@@ -736,34 +627,25 @@ define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v4bf16_v2bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v0, 1
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v10, a0, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; ZVBB-NEXT: vmv.v.i v0, 1
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; ZVBB-NEXT: vslideup.vi v8, v9, 1
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v10, v9, 16
+; ZVBB-NEXT: vwaddu.wv v10, v10, v8
+; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vpairo.vv v11, v8, v9
-; ZVZIP-NEXT: vslideup.vi v10, v9, 1
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 2
+; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
%res = call <4 x bfloat> @llvm.vector.interleave2.v4bf16(<2 x bfloat> %a, <2 x bfloat> %b)
@@ -773,62 +655,26 @@ define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloa
define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
; CHECK-LABEL: vector_interleave_v8f16_v4f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v0, 10
-; CHECK-NEXT: vslidedown.vi v10, v9, 2
-; CHECK-NEXT: vslidedown.vi v11, v8, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v10
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsll.vi v11, v12, 16
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v13, v11, v0
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v8, 4
-; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8f16_v4f16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVBB-NEXT: vmv.v.i v0, 10
-; ZVBB-NEXT: vslidedown.vi v10, v8, 2
-; ZVBB-NEXT: vslidedown.vi v11, v9, 2
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v10
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVBB-NEXT: vwsll.vi v13, v11, 16
-; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vmerge.vvm v9, v12, v13, v0
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 4
-; ZVBB-NEXT: vmv.v.v v8, v10
+; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8f16_v4f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslidedown.vi v10, v9, 2
-; ZVZIP-NEXT: vslidedown.vi v11, v8, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-NEXT: vzip.vv v13, v12, v10
-; ZVZIP-NEXT: vzip.vv v12, v11, v10
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vmerge.vvm v11, v12, v13, v0
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 4
-; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)
ret <8 x half> %res
@@ -837,62 +683,26 @@ define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v8bf16_v4bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v0, 10
-; CHECK-NEXT: vslidedown.vi v10, v9, 2
-; CHECK-NEXT: vslidedown.vi v11, v8, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v10
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsll.vi v11, v12, 16
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v13, v11, v0
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v8, 4
-; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVBB-NEXT: vmv.v.i v0, 10
-; ZVBB-NEXT: vslidedown.vi v10, v8, 2
-; ZVBB-NEXT: vslidedown.vi v11, v9, 2
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v10
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVBB-NEXT: vwsll.vi v13, v11, 16
-; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vmerge.vvm v9, v12, v13, v0
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 4
-; ZVBB-NEXT: vmv.v.v v8, v10
+; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslidedown.vi v10, v9, 2
-; ZVZIP-NEXT: vslidedown.vi v11, v8, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-NEXT: vzip.vv v13, v12, v10
-; ZVZIP-NEXT: vzip.vv v12, v11, v10
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vmerge.vvm v11, v12, v13, v0
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 4
-; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
%res = call <8 x bfloat> @llvm.vector.interleave2.v8bf16(<4 x bfloat> %a, <4 x bfloat> %b)
ret <8 x bfloat> %res
@@ -901,35 +711,27 @@ define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloa
define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: vector_interleave_v4f32_v2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v0, 1
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v10, a0, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f32_v2f32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; ZVBB-NEXT: vmv.v.i v0, 1
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; ZVBB-NEXT: vslideup.vi v8, v9, 1
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: li a0, 32
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vx v10, v9, a0
+; ZVBB-NEXT: vwaddu.wv v10, v10, v8
+; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f32_v2f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vpairo.vv v11, v8, v9
-; ZVZIP-NEXT: vslideup.vi v10, v9, 1
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 2
-; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
%res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)
ret <4 x float> %res
@@ -938,64 +740,29 @@ define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b
define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: vector_interleave_v16f16_v8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vslidedown.vi v8, v8, 4
-; CHECK-NEXT: vslidedown.vi v11, v9, 4
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsll.vi v10, v13, 16
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v8, a0, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v8
+; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16f16_v8f16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v8
-; ZVBB-NEXT: li a0, 170
-; ZVBB-NEXT: vmv.s.x v0, a0
-; ZVBB-NEXT: vslidedown.vi v8, v8, 4
-; ZVBB-NEXT: vslidedown.vi v11, v9, 4
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v8
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vi v8, v9, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v10
-; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
-; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 8
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: vwsll.vi v8, v10, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16f16_v8f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: li a0, 170
-; ZVZIP-NEXT: vmv.s.x v0, a0
-; ZVZIP-NEXT: vslidedown.vi v8, v9, 4
-; ZVZIP-NEXT: vslidedown.vi v11, v10, 4
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v13, v12, v8
-; ZVZIP-NEXT: vzip.vv v12, v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v10, v9
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vmerge.vvm v10, v12, v13, v0
-; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 8
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
%res = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b)
ret <16 x half> %res
@@ -1004,64 +771,29 @@ define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b)
define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v16bf16_v8bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vslidedown.vi v8, v8, 4
-; CHECK-NEXT: vslidedown.vi v11, v9, 4
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsll.vi v10, v13, 16
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v8, a0, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v8
+; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v8
-; ZVBB-NEXT: li a0, 170
-; ZVBB-NEXT: vmv.s.x v0, a0
-; ZVBB-NEXT: vslidedown.vi v8, v8, 4
-; ZVBB-NEXT: vslidedown.vi v11, v9, 4
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v8
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vi v8, v9, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v10
-; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
-; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 8
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: vwsll.vi v8, v10, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: li a0, 170
-; ZVZIP-NEXT: vmv.s.x v0, a0
-; ZVZIP-NEXT: vslidedown.vi v8, v9, 4
-; ZVZIP-NEXT: vslidedown.vi v11, v10, 4
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v13, v12, v8
-; ZVZIP-NEXT: vzip.vv v12, v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v10, v9
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vmerge.vvm v10, v12, v13, v0
-; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 8
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
%res = call <16 x bfloat> @llvm.vector.interleave2.v16bf16(<8 x bfloat> %a, <8 x bfloat> %b)
ret <16 x bfloat> %res
@@ -1070,63 +802,30 @@ define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfl
define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: vector_interleave_v8f32_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-NEXT: vslidedown.vi v11, v10, 2
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vmv.v.i v0, 10
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT: vsll.vx v10, v12, a0
-; CHECK-NEXT: vzext.vf2 v12, v11
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v8, a0, v9
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v8
+; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8f32_v4f32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v8
-; ZVBB-NEXT: vslidedown.vi v8, v8, 2
-; ZVBB-NEXT: vmv.v.i v0, 10
-; ZVBB-NEXT: vslidedown.vi v11, v9, 2
-; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v8
-; ZVBB-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vx v8, v9, a0
-; ZVBB-NEXT: vwaddu.wv v8, v8, v10
-; ZVBB-NEXT: vwsll.vx v9, v11, a0
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
-; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: li a0, 32
+; ZVBB-NEXT: vwsll.vx v8, v10, a0
+; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8f32_v4f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslidedown.vi v8, v9, 2
-; ZVZIP-NEXT: vslidedown.vi v11, v10, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v13, v12, v8
-; ZVZIP-NEXT: vzip.vv v12, v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v10, v9
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vmerge.vvm v10, v12, v13, v0
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)
ret <8 x float> %res
@@ -1135,34 +834,40 @@ define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b
define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: vector_interleave_v4f64_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v0, 1
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: lui a0, 12304
+; CHECK-NEXT: addi a0, a0, 512
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsext.vf2 v12, v10
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
+; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f64_v2f64:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; ZVBB-NEXT: vmv.v.i v0, 1
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; ZVBB-NEXT: vslideup.vi v8, v9, 1
; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v9
; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: lui a0, 12304
+; ZVBB-NEXT: addi a0, a0, 512
+; ZVBB-NEXT: vmv.s.x v10, a0
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vsext.vf2 v12, v10
+; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
+; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f64_v2f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vslideup.vi v8, v9, 1
-; ZVZIP-NEXT: vpairo.vv v12, v10, v9
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 2
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
%res = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)
ret <4 x double> %res
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