[llvm] [RISCV] Enable shouldMaximizeVectorBandwidth (PR #216005)

[Florian Hahn via llvm-commits]

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@@ -1379,6 +1409,11 @@ class TargetTransformInfo {
   LLVM_ABI bool
   shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const;
 
+  /// Return the register-usage model VPlan should use for conservative
+  /// register-pressure decisions involving registers of kind \p K. This mode
+  /// is not intended for estimating spill costs.
+  LLVM_ABI VPRegisterUsageMode getVPlanRegisterUsageMode(RegisterKind K) const;
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fhahn wrote:

I am not sure about leaking an implementation details (VPlan) to TTI. Do we really need this?

https://github.com/llvm/llvm-project/pull/216005