[llvm] CodeGen: Drop inert -fp-contract flags from tests (PR #221710)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 7 04:32:08 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/221710
-fp-contract is nearly dead, but referenced in tests. These have
no output change with or without the flag now.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
>From deed172fb37901acfc36ffc6a63bb5ff20ae5f3f Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Mon, 7 Sep 2026 13:30:34 +0200
Subject: [PATCH] CodeGen: Drop inert -fp-contract flags from tests
-fp-contract is nearly dead, but referenced in tests. These have
no output change with or without the flag now.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
---
.../Analysis/CostModel/AMDGPU/fused_costs.ll | 12 +--
llvm/test/CodeGen/AArch64/PBQP-chain.ll | 4 +-
.../CodeGen/AArch64/PBQP-coalesce-benefit.ll | 2 +-
llvm/test/CodeGen/AArch64/PBQP-csr.ll | 2 +-
llvm/test/CodeGen/AArch64/arithmetic_fence.ll | 4 +-
.../AArch64/arm64-2013-01-13-ffast-fcmp.ll | 5 -
.../AArch64/arm64-extract-insert-varidx.ll | 4 +-
.../CodeGen/AArch64/arm64-fml-combines.ll | 1 -
.../CodeGen/AArch64/arm64-neon-2velem-high.ll | 4 +-
.../AArch64/arm64-neon-scalar-by-elem-mul.ll | 2 +-
.../CodeGen/AArch64/arm64-neon-select_cc.ll | 2 +-
.../AArch64/arm64-neon-vector-list-spill.ll | 2 +-
llvm/test/CodeGen/AArch64/fnmul.ll | 1 -
llvm/test/CodeGen/AArch64/fp16-fmla.ll | 2 +-
.../test/CodeGen/AArch64/neon-fpextend_f16.ll | 2 +-
.../test/CodeGen/AArch64/neon-fpround_f128.ll | 2 +-
.../AArch64/neon-scalar-by-elem-fma.ll | 2 +-
.../GlobalISel/combine-fma-add-ext-fma.ll | 92 +------------------
.../GlobalISel/combine-fma-add-fma-mul.ll | 8 +-
llvm/test/CodeGen/AMDGPU/fdot2.ll | 4 +-
.../CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll | 4 +-
llvm/test/CodeGen/Hexagon/swp-epilog-reuse.ll | 2 +-
.../test/CodeGen/Hexagon/swp-epilog-reuse2.ll | 2 +-
llvm/test/CodeGen/Hexagon/swp-loop-carried.ll | 2 +-
llvm/test/CodeGen/Hexagon/swp-max-stage3.ll | 2 +-
.../CodeGen/Hexagon/swp-memrefs-epilog.ll | 2 +-
.../CodeGen/Hexagon/swp-rename-dead-phi.ll | 2 +-
llvm/test/CodeGen/Hexagon/swp-reuse-phi.ll | 2 +-
.../PowerPC/fma-mutate-duplicate-vreg.ll | 2 +-
29 files changed, 41 insertions(+), 136 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll b/llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll
index c87607a52774a..aeec6fd916514 100644
--- a/llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll
+++ b/llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgpu9.00-unknown-amdhsa -denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileCheck -check-prefixes=SLOWF64,FUSED,SLOWF32 %s
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgpu9.00-unknown-amdhsa -denormal-fp-math-f32=ieee -denormal-fp-math=ieee -fp-contract=on < %s | FileCheck -check-prefixes=SLOWF64,FASTF32,GFX9SLOW %s
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgpu10.30-unknown-amdhsa -denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileCheck -check-prefixes=SLOWF64,FUSED,FASTF32,GFX1030 %s
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgpu9.00-unknown-amdhsa -denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=SLOWF64,FUSED,SLOWF32 %s
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgpu9.00-unknown-amdhsa -denormal-fp-math-f32=ieee -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=SLOWF64,FASTF32,GFX9SLOW %s
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgpu10.30-unknown-amdhsa -denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=SLOWF64,FUSED,FASTF32,GFX1030 %s
-; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu9.00-unknown-amdhsa -denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileCheck -check-prefixes=SLOWF64-SIZE,FUSED-SIZE,SLOWF32-SIZE %s
-; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu9.00-unknown-amdhsa -denormal-fp-math-f32=ieee -denormal-fp-math=ieee -fp-contract=on < %s | FileCheck -check-prefixes=SLOWF64-SIZE,FASTF32-SIZE,GFX9SLOW-SIZE %s
-; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu10.30-unknown-amdhsa -denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileCheck -check-prefixes=SLOWF64-SIZE,FUSED-SIZE,FASTF32-SIZE,GFX1030-SIZE %s
+; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu9.00-unknown-amdhsa -denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=SLOWF64-SIZE,FUSED-SIZE,SLOWF32-SIZE %s
+; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu9.00-unknown-amdhsa -denormal-fp-math-f32=ieee -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=SLOWF64-SIZE,FASTF32-SIZE,GFX9SLOW-SIZE %s
+; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu10.30-unknown-amdhsa -denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=SLOWF64-SIZE,FUSED-SIZE,FASTF32-SIZE,GFX1030-SIZE %s
; END.
define void @fmul_fadd_f32(float %a, float %b, float %c, <2 x float> %va, <2 x float> %vb, <2 x float> %vc) #0 {
diff --git a/llvm/test/CodeGen/AArch64/PBQP-chain.ll b/llvm/test/CodeGen/AArch64/PBQP-chain.ll
index 10b299f6afa79..e9dced1361ffd 100644
--- a/llvm/test/CodeGen/AArch64/PBQP-chain.ll
+++ b/llvm/test/CodeGen/AArch64/PBQP-chain.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mcpu=cortex-a57 -mattr=+neon -fp-contract=fast -regalloc=pbqp -pbqp-coalescing | FileCheck %s --check-prefix CHECK --check-prefix CHECK-EVEN
-; RUN: llc < %s -mcpu=cortex-a57 -mattr=+neon -fp-contract=fast -regalloc=pbqp -pbqp-coalescing | FileCheck %s --check-prefix CHECK --check-prefix CHECK-ODD
+; RUN: llc < %s -mcpu=cortex-a57 -mattr=+neon -regalloc=pbqp -pbqp-coalescing | FileCheck %s --check-prefix CHECK --check-prefix CHECK-EVEN
+; RUN: llc < %s -mcpu=cortex-a57 -mattr=+neon -regalloc=pbqp -pbqp-coalescing | FileCheck %s --check-prefix CHECK --check-prefix CHECK-ODD
;
; Test PBQP is able to fulfill the accumulator chaining constraint.
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll b/llvm/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll
index 6c9e250af0886..aafc1718d686f 100644
--- a/llvm/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll
+++ b/llvm/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a57 -mattr=+neon -fp-contract=fast -regalloc=pbqp -pbqp-coalescing | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a57 -mattr=+neon -regalloc=pbqp -pbqp-coalescing | FileCheck %s
; CHECK-LABEL: test:
define i32 @test(i32 %acc, ptr nocapture readonly %c) {
diff --git a/llvm/test/CodeGen/AArch64/PBQP-csr.ll b/llvm/test/CodeGen/AArch64/PBQP-csr.ll
index 55dbc5720b47f..232ef840d8471 100644
--- a/llvm/test/CodeGen/AArch64/PBQP-csr.ll
+++ b/llvm/test/CodeGen/AArch64/PBQP-csr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a57 -mattr=+neon -fp-contract=fast -regalloc=pbqp -pbqp-coalescing | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a57 -mattr=+neon -regalloc=pbqp -pbqp-coalescing | FileCheck %s
%pl = type { i32, i32, i32, i32, ptr, ptr, ptr }
%p = type { i32, ptr, [27 x ptr], ptr, ptr, ptr, i32 }
diff --git a/llvm/test/CodeGen/AArch64/arithmetic_fence.ll b/llvm/test/CodeGen/AArch64/arithmetic_fence.ll
index c6a711d923032..2fa2a0ffabb01 100644
--- a/llvm/test/CodeGen/AArch64/arithmetic_fence.ll
+++ b/llvm/test/CodeGen/AArch64/arithmetic_fence.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=-neon -fp-contract=fast | FileCheck %s --check-prefix=Aarch64
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s --check-prefix=Aarch64-Neon
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=-neon | FileCheck %s --check-prefix=Aarch64
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=Aarch64-Neon
define float @f1(float %a, float %b, float %c) {
; Aarch64-LABEL: f1:
diff --git a/llvm/test/CodeGen/AArch64/arm64-2013-01-13-ffast-fcmp.ll b/llvm/test/CodeGen/AArch64/arm64-2013-01-13-ffast-fcmp.ll
index 9b08538ad6e96..a3faac2af384e 100644
--- a/llvm/test/CodeGen/AArch64/arm64-2013-01-13-ffast-fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-2013-01-13-ffast-fcmp.ll
@@ -1,12 +1,7 @@
; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -aarch64-neon-syntax=apple | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -aarch64-neon-syntax=apple -fp-contract=fast | FileCheck %s --check-prefix=FAST
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
-;FAST-LABEL: _Z9example25v:
-;FAST: fcmgt.4s
-;FAST: ret
-
;CHECK-LABEL: _Z9example25v:
;CHECK: fcmgt.4s
;CHECK: ret
diff --git a/llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll b/llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
index 8db13306d92d5..1fa1cf135051a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast -aarch64-enable-sink-fold=true | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s -global-isel -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast -aarch64-enable-sink-fold=true | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -aarch64-enable-sink-fold=true | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -global-isel -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -aarch64-enable-sink-fold=true | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <4 x i8> @test_varidx_extract_v8s8(<8 x i8> %x, i32 %idx) {
; CHECK-SD-LABEL: test_varidx_extract_v8s8:
diff --git a/llvm/test/CodeGen/AArch64/arm64-fml-combines.ll b/llvm/test/CodeGen/AArch64/arm64-fml-combines.ll
index 60c48bfce3f85..1533c7626fba9 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fml-combines.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fml-combines.ll
@@ -1,5 +1,4 @@
; RUN: llc < %s -O3 -mtriple=arm64-apple-ios -mattr=+fullfp16 | FileCheck %s
-; RUN: llc < %s -O3 -mtriple=arm64-apple-ios -fp-contract=fast -mattr=+fullfp16 | FileCheck %s
define void @foo_2d(ptr %src) {
entry:
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll b/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
index 7581671a51f60..50b179be3a02c 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast < %s -verify-machineinstrs -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon < %s -verify-machineinstrs -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for test_vfms_n_f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vfmsq_n_f32
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-scalar-by-elem-mul.ll b/llvm/test/CodeGen/AArch64/arm64-neon-scalar-by-elem-mul.ll
index 091cda89bfe40..b1a5bae4699b9 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-scalar-by-elem-mul.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-scalar-by-elem-mul.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
define float @test_fmul_lane_ss2S_0(float %a, <2 x float> %v) {
; CHECK-LABEL: test_fmul_lane_ss2S_0:
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll b/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
index 870448b92e18e..9c6eff55022e8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast \
+; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon \
; RUN: < %s -verify-machineinstrs | FileCheck %s
define <8x i8> @test_select_cc_v8i8_i8(i8 %a, i8 %b, <8x i8> %c, <8x i8> %d ) {
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-vector-list-spill.ll b/llvm/test/CodeGen/AArch64/arm64-neon-vector-list-spill.ll
index bb06778696c97..aa68f951076e6 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-vector-list-spill.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-vector-list-spill.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
; FIXME: We should not generate ld/st for such register spill/fill, because the
; test case seems very simple and the register pressure is not high. If the
diff --git a/llvm/test/CodeGen/AArch64/fnmul.ll b/llvm/test/CodeGen/AArch64/fnmul.ll
index 0b145a282ba6a..16a04f6018b0a 100644
--- a/llvm/test/CodeGen/AArch64/fnmul.ll
+++ b/llvm/test/CodeGen/AArch64/fnmul.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-;RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 -fp-contract=fast -verify-machineinstrs -global-isel=0 | FileCheck %s
;RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 -verify-machineinstrs -global-isel=0 | FileCheck %s
diff --git a/llvm/test/CodeGen/AArch64/fp16-fmla.ll b/llvm/test/CodeGen/AArch64/fp16-fmla.ll
index a81721afb8453..6bbbd9144e40e 100644
--- a/llvm/test/CodeGen/AArch64/fp16-fmla.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-fmla.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 | FileCheck %s
define half @test_FMULADDH_OP1(half %a, half %b, half %c) {
; CHECK-LABEL: test_FMULADDH_OP1:
diff --git a/llvm/test/CodeGen/AArch64/neon-fpextend_f16.ll b/llvm/test/CodeGen/AArch64/neon-fpextend_f16.ll
index 097e18b810411..63a465d05b71c 100644
--- a/llvm/test/CodeGen/AArch64/neon-fpextend_f16.ll
+++ b/llvm/test/CodeGen/AArch64/neon-fpextend_f16.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
; This is testing that we can scalarize the v1f16 input to fp_extend even
; though the v1f64 result is legal.
diff --git a/llvm/test/CodeGen/AArch64/neon-fpround_f128.ll b/llvm/test/CodeGen/AArch64/neon-fpround_f128.ll
index 64bb9934360fb..cf0a400697780 100644
--- a/llvm/test/CodeGen/AArch64/neon-fpround_f128.ll
+++ b/llvm/test/CodeGen/AArch64/neon-fpround_f128.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
define <1 x double> @test_fpround_v1f128(ptr %a) {
; CHECK-LABEL: test_fpround_v1f128:
diff --git a/llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll b/llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
index 544d7680f01b8..7da7a89745f2e 100644
--- a/llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
+++ b/llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
attributes #0 = { strictfp }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
index 5909e89b9199e..c012f0cf07821 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu9.00 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
-; RUN: llc -global-isel -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu10.10 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GFX10,GFX10-CONTRACT %s
; RUN: llc -global-isel -mtriple=amdgpu10.10 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
; fold (fadd (fma x, y, (fpext (fmul u, v))), z) -> (fma x, y, (fma (fpext u), (fpext v), z))
@@ -20,13 +19,6 @@ define amdgpu_vs float @test_f16_f32_add_fma_ext_mul(float %x, float %y, float %
; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX10-CONTRACT-LABEL: test_f16_f32_add_fma_ext_mul:
-; GFX10-CONTRACT: ; %bb.0: ; %.entry
-; GFX10-CONTRACT-NEXT: v_mul_f16_e32 v3, v3, v4
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v0, v1, v3 op_sel_hi:[0,0,1]
-; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX10-CONTRACT-NEXT: ; return to shader part epilog
-;
; GFX10-DENORM-LABEL: test_f16_f32_add_fma_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_mul_f16_e32 v3, v3, v4
@@ -56,13 +48,6 @@ define amdgpu_vs float @test_f16_f32_add_ext_fma_mul(half %x, half %y, float %z,
; GFX10-NEXT: v_fma_mix_f32 v0, v3, 1.0, v2 op_sel_hi:[1,1,0]
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX10-CONTRACT-LABEL: test_f16_f32_add_ext_fma_mul:
-; GFX10-CONTRACT: ; %bb.0: ; %.entry
-; GFX10-CONTRACT-NEXT: v_mul_f16_e32 v3, v3, v4
-; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v3, v0, v1
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v3, 1.0, v2 op_sel_hi:[1,1,0]
-; GFX10-CONTRACT-NEXT: ; return to shader part epilog
-;
; GFX10-DENORM-LABEL: test_f16_f32_add_ext_fma_mul:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_mul_f16_e32 v3, v3, v4
@@ -93,13 +78,6 @@ define amdgpu_vs float @test_f16_f32_add_fma_ext_mul_rhs(float %x, float %y, flo
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX10-CONTRACT-LABEL: test_f16_f32_add_fma_ext_mul_rhs:
-; GFX10-CONTRACT: ; %bb.0: ; %.entry
-; GFX10-CONTRACT-NEXT: v_mul_f16_e32 v3, v3, v4
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v1, v1, v2, v3 op_sel_hi:[0,0,1]
-; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX10-CONTRACT-NEXT: ; return to shader part epilog
-;
; GFX10-DENORM-LABEL: test_f16_f32_add_fma_ext_mul_rhs:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_mul_f16_e32 v3, v3, v4
@@ -129,13 +107,6 @@ define amdgpu_vs float @test_f16_f32_add_ext_fma_mul_rhs(float %x, half %y, half
; GFX10-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0]
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX10-CONTRACT-LABEL: test_f16_f32_add_ext_fma_mul_rhs:
-; GFX10-CONTRACT: ; %bb.0: ; %.entry
-; GFX10-CONTRACT-NEXT: v_mul_f16_e32 v3, v3, v4
-; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v3, v1, v2
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0]
-; GFX10-CONTRACT-NEXT: ; return to shader part epilog
-;
; GFX10-DENORM-LABEL: test_f16_f32_add_ext_fma_mul_rhs:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_mul_f16_e32 v3, v3, v4
@@ -181,20 +152,6 @@ define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_fma_ext_mul(<4 x float> %x, <
; GFX10-NEXT: v_add_f32_e32 v3, v3, v11
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_fma_ext_mul:
-; GFX10-CONTRACT: ; %bb.0: ; %.entry
-; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v12, v12, v14
-; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v13, v13, v15
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v0, v4, v12 op_sel_hi:[0,0,1]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v1, v1, v5, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v2, v2, v6, v13 op_sel_hi:[0,0,1]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v3, v3, v7, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]
-; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v8
-; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v9
-; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v10
-; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v11
-; GFX10-CONTRACT-NEXT: ; return to shader part epilog
-;
; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_fma_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_pk_mul_f16 v12, v12, v14
@@ -244,18 +201,6 @@ define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_ext_fma_mul(<4 x half> %x, <4
; GFX10-NEXT: v_fma_mix_f32 v3, v3, 1.0, v7 op_sel:[1,0,0] op_sel_hi:[1,1,0]
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_ext_fma_mul:
-; GFX10-CONTRACT: ; %bb.0: ; %.entry
-; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v8, v8, v10
-; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v9, v9, v11
-; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v2, v0, v2, v8
-; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v3, v1, v3, v9
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v2, 1.0, v4 op_sel_hi:[1,1,0]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v1, v2, 1.0, v5 op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v2, v3, 1.0, v6 op_sel_hi:[1,1,0]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v3, v3, 1.0, v7 op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX10-CONTRACT-NEXT: ; return to shader part epilog
-;
; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_pk_mul_f16 v8, v8, v10
@@ -307,20 +252,6 @@ define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_fma_ext_mul_rhs(<4 x float> %
; GFX10-NEXT: v_add_f32_e32 v3, v3, v7
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs:
-; GFX10-CONTRACT: ; %bb.0: ; %.entry
-; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v12, v12, v14
-; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v13, v13, v15
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v4, v4, v8, v12 op_sel_hi:[0,0,1]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v5, v5, v9, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v6, v6, v10, v13 op_sel_hi:[0,0,1]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v7, v7, v11, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]
-; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v5
-; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v6
-; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v7
-; GFX10-CONTRACT-NEXT: ; return to shader part epilog
-;
; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_pk_mul_f16 v12, v12, v14
@@ -370,18 +301,6 @@ define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_ext_fma_mul_rhs(<4 x float> %
; GFX10-NEXT: v_fma_mix_f32 v3, v5, 1.0, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0]
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs:
-; GFX10-CONTRACT: ; %bb.0: ; %.entry
-; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v8, v8, v10
-; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v9, v9, v11
-; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v4, v4, v6, v8
-; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v5, v5, v7, v9
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v4, 1.0, v0 op_sel_hi:[1,1,0]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v1, v4, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v2, v5, 1.0, v2 op_sel_hi:[1,1,0]
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v3, v5, 1.0, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX10-CONTRACT-NEXT: ; return to shader part epilog
-;
; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_pk_mul_f16 v8, v8, v10
@@ -418,13 +337,6 @@ define amdgpu_ps float @test_matching_source_from_unmerge(ptr addrspace(3) %aptr
; GFX10-NEXT: v_fma_mix_f32 v0, v2, v3, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX10-CONTRACT-LABEL: test_matching_source_from_unmerge:
-; GFX10-CONTRACT: ; %bb.0: ; %.entry
-; GFX10-CONTRACT-NEXT: ds_read_b64 v[2:3], v0
-; GFX10-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v2, v3, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GFX10-CONTRACT-NEXT: ; return to shader part epilog
-;
; GFX10-DENORM-LABEL: test_matching_source_from_unmerge:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: ds_read_b64 v[2:3], v0
@@ -446,3 +358,5 @@ declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #
declare <4 x half> @llvm.fmuladd.v4f16(<4 x half>, <4 x half>, <4 x half>) #0
attributes #0 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX10-CONTRACT: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
index ce4de6e628573..cbdf1170a3aa0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu9.00 -fp-contract=fast < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9-CONTRACT %s
; RUN: llc -global-isel -mtriple=amdgpu9.00 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
-; RUN: llc -global-isel -mtriple=amdgpu10.10 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=GFX10-CONTRACT %s
; RUN: llc -global-isel -mtriple=amdgpu10.10 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 -fp-contract=fast < %s | FileCheck -check-prefixes=GFX11-CONTRACT,GFX11-CONTRACT-TRUE16 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 -fp-contract=fast < %s | FileCheck -check-prefixes=GFX11-CONTRACT,GFX11-CONTRACT-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-CONTRACT,GFX11-CONTRACT-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-CONTRACT,GFX11-CONTRACT-FAKE16 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX11-DENORM,GFX11-DENORM-TRUE16 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX11-DENORM,GFX11-DENORM-FAKE16 %s
diff --git a/llvm/test/CodeGen/AMDGPU/fdot2.ll b/llvm/test/CodeGen/AMDGPU/fdot2.ll
index ce04bf760303e..a9665ba607936 100644
--- a/llvm/test/CodeGen/AMDGPU/fdot2.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdot2.ll
@@ -3,8 +3,8 @@
; RUN: llc -mtriple=amdgpu10.11 -denormal-fp-math-f32=preserve-sign < %s | FileCheck %s -check-prefixes=GCN,GCN-DL-UNSAFE,GFX10-DL-UNSAFE,GFX10-CONTRACT
; RUN: llc -mtriple=amdgpu10.12 -denormal-fp-math-f32=preserve-sign < %s | FileCheck %s -check-prefixes=GCN,GCN-DL-UNSAFE,GFX10-DL-UNSAFE,GFX10-CONTRACT
; RUN: llc -mtriple=amdgpu9.06 -denormal-fp-math-f32=preserve-sign < %s | FileCheck %s -check-prefixes=GCN,GFX906
-; RUN: llc -mtriple=amdgpu9.06 -denormal-fp-math=preserve-sign -fp-contract=fast < %s | FileCheck %s -check-prefixes=GCN,GFX906-CONTRACT
-; RUN: llc -mtriple=amdgpu9.06 -denormal-fp-math=ieee -fp-contract=fast < %s | FileCheck %s -check-prefixes=GCN,GFX906-DENORM-CONTRACT
+; RUN: llc -mtriple=amdgpu9.06 -denormal-fp-math=preserve-sign < %s | FileCheck %s -check-prefixes=GCN,GFX906-CONTRACT
+; RUN: llc -mtriple=amdgpu9.06 -denormal-fp-math=ieee < %s | FileCheck %s -check-prefixes=GCN,GFX906-DENORM-CONTRACT
; RUN: llc -mtriple=amdgpu9.06 -denormal-fp-math-f32=preserve-sign -mattr="+dot7-insts,-dot10-insts" < %s | FileCheck %s -check-prefixes=GCN,GFX906-DOT10-DISABLED
; RUN: llc -mtriple=amdgpu9.0a -denormal-fp-math-f32=preserve-sign < %s | FileCheck %s -check-prefixes=GCN,GFX90A-PS
; RUN: llc -mtriple=amdgpu9.0a -denormal-fp-math-f32=ieee < %s | FileCheck %s -check-prefixes=GCN,GFX90A-IEEE
diff --git a/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll b/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
index 6760124b7b2d3..77ca9241cbdbc 100644
--- a/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
+++ b/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
@@ -1,7 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -S -passes='simplifycfg<hoist-common-insts>' -mtriple=amdgpu10.30-- --fp-contract=fast < %s | FileCheck -check-prefix=GFX -check-prefix=FP-CONTRACT-FAST %s
-; RUN: opt -S -passes='simplifycfg<hoist-common-insts>' -mtriple=amdgpu10.30-- --fp-contract=off < %s | FileCheck -check-prefix=GFX -check-prefix=UNSAFE-FP-MATH %s
-; RUN: opt -S -passes='simplifycfg<hoist-common-insts>' -mtriple=amdgpu10.30-- --fp-contract=off < %s | FileCheck -check-prefix=GFX -check-prefix=NO-UNSAFE-FP-MATH %s
+; RUN: opt -S -passes='simplifycfg<hoist-common-insts>' -mtriple=amdgpu10.30-- < %s | FileCheck -check-prefixes=GFX,FP-CONTRACT-FAST,UNSAFE-FP-MATH,NO-UNSAFE-FP-MATH %s
define double @is_profitable_f64_contract(ptr dereferenceable(8) %ptr_x, ptr dereferenceable(8) %ptr_y, ptr dereferenceable(8) %ptr_a) #0 {
; GFX-LABEL: define double @is_profitable_f64_contract(
diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse.ll
index 9ae6fa01148d4..1042a0f343fbf 100644
--- a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse.ll
@@ -1,4 +1,4 @@
-; RUN: llc -fp-contract=fast -O3 -mtriple=hexagon -mcpu=hexagonv5 < %s
+; RUN: llc -O3 -mtriple=hexagon -mcpu=hexagonv5 < %s
; REQUIRES: asserts
; Test that the pipeliner doesn't ICE due because the PHI generation
diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse2.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse2.ll
index 3a5afb7dcb720..803114e5b8e0c 100644
--- a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse2.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -fp-contract=fast -O3 -mtriple=hexagon < %s
+; RUN: llc -O3 -mtriple=hexagon < %s
; REQUIRES: asserts
; Test that the pipeliner doesn't ICE due because the PHI generation
diff --git a/llvm/test/CodeGen/Hexagon/swp-loop-carried.ll b/llvm/test/CodeGen/Hexagon/swp-loop-carried.ll
index 64c34f246f321..1c250a3a58795 100644
--- a/llvm/test/CodeGen/Hexagon/swp-loop-carried.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-loop-carried.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -fp-contract=fast -enable-pipeliner < %s
+; RUN: llc -mtriple=hexagon -enable-pipeliner < %s
; REQUIRES: asserts
; A Phi that depends on another Phi is loop carried.
diff --git a/llvm/test/CodeGen/Hexagon/swp-max-stage3.ll b/llvm/test/CodeGen/Hexagon/swp-max-stage3.ll
index e027616b9976b..e21a48e30b93c 100644
--- a/llvm/test/CodeGen/Hexagon/swp-max-stage3.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-max-stage3.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -O3 -fp-contract=fast -pipeliner-max-stages=3 < %s
+; RUN: llc -mtriple=hexagon -O3 -pipeliner-max-stages=3 < %s
; REQUIRES: asserts
; Check Phis are generated correctly in epilogs after setting -swp-max-stages=3
diff --git a/llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll b/llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll
index c9613156a4dfc..88456d22c78e6 100644
--- a/llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -O2 -fp-contract=fast < %s -pipeliner-experimental-cg=true | FileCheck %s
+; RUN: llc -mtriple=hexagon -O2 < %s -pipeliner-experimental-cg=true | FileCheck %s
; Test that the memoperands for instructions in the epilog are updated
; correctly. Previously, the pipeliner updated the offset for the memoperands
diff --git a/llvm/test/CodeGen/Hexagon/swp-rename-dead-phi.ll b/llvm/test/CodeGen/Hexagon/swp-rename-dead-phi.ll
index c1b31738a7b30..473d7310ec378 100644
--- a/llvm/test/CodeGen/Hexagon/swp-rename-dead-phi.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-rename-dead-phi.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -fp-contract=fast -enable-pipeliner < %s
+; RUN: llc -mtriple=hexagon -enable-pipeliner < %s
; REQUIRES: asserts
; Pipelining can eliminate the need for a Phi if the loop carried use
diff --git a/llvm/test/CodeGen/Hexagon/swp-reuse-phi.ll b/llvm/test/CodeGen/Hexagon/swp-reuse-phi.ll
index 36d390a7b10a8..21bb3455e0e96 100644
--- a/llvm/test/CodeGen/Hexagon/swp-reuse-phi.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-reuse-phi.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=hexagon -enable-pipeliner -fp-contract=fast < %s
+; RUN: llc -mtriple=hexagon -enable-pipeliner < %s
; REQUIRES: asserts
; Test that the code which reuses existing Phis works when the Phis are used
diff --git a/llvm/test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll b/llvm/test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll
index 2d34e83720e29..86cffebf26dec 100644
--- a/llvm/test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll
+++ b/llvm/test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -fp-contract=fast -O2 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -O2 < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-grtev4-linux-gnu"
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