[llvm] [SelectionDAG] Widen vector math libcalls when no routine is available (PR #218948)

[David Sherwood via llvm-commits]

=?utf-8?q?Mattéo?= Rizza Murgier,=?utf-8?q?Mattéo?= Rizza Murgier,
=?utf-8?q?Mattéo?= Rizza Murgier,=?utf-8?q?Mattéo?= Rizza Murgier,
=?utf-8?q?Mattéo?= Rizza Murgier,=?utf-8?q?Mattéo?= Rizza Murgier,
=?utf-8?q?Mattéo?= Rizza Murgier,=?utf-8?q?Mattéo?= Rizza Murgier
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/218948 at github.com>


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@@ -2185,12 +2192,24 @@ bool VectorLegalizer::tryExpandVecMathCall(SDNode *Node, RTLIB::Libcall LC,
     if (HasMaskArg && I == E - 1) {
       assert(cast<VectorType>(ParamTy)->getElementType()->isIntegerTy(1) &&
              "unexpected vector mask type");
-      EVT MaskVT = TLI.getSetCCResultType(DAG.getDataLayout(), Ctx, VT);
-      Args.emplace_back(DAG.getBoolConstant(true, DL, MaskVT, VT),
-                        MaskVT.getTypeForEVT(Ctx));
-
+      EVT MaskVT = TLI.getSetCCResultType(DAG.getDataLayout(), Ctx, CallVT);
+      EVT SubMaskVT =
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david-arm wrote:

OK thanks. At the moment the code should work because in practice for AArch64 the only masked variants of vector math calls also use scalable vectors, where types such as <vscale x 4 x i1> are legal. This could be problematic in future if someone ever decides to add a fixed-width masked variant where <4 x i1> is not legal, since we'd be explicitly introducing an illegal operand type and I don't know if there is anything after LegalizeVectorOps that would promote it to <4 x i32>.

https://github.com/llvm/llvm-project/pull/218948