[llvm] [TargetInstrInfo] Enable instruction size verification by default (PR #221687)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-arm

Author: Nikita Popov (nikic)

<details>
<summary>Changes</summary>

Enable verification for instruction sizes by default. When emitting machine code, this checks that the reported instruction size is not smaller than the actual instruction size. Not under-reporting instruction sizes is critical for any target that does branch relaxation (or similar) on MIR.

The default allows over-estimating the size by default. Targets can opt-in to precise instruction sizes if they want.

Exclude two instructions on ARM, which report incorrect sizes, but fixing those sizes breaks the constant islands pass for some reason.

---
Full diff: https://github.com/llvm/llvm-project/pull/221687.diff


2 Files Affected:

- (modified) llvm/include/llvm/CodeGen/TargetInstrInfo.h (+1-1) 
- (modified) llvm/lib/Target/ARM/ARMBaseInstrInfo.h (+9) 


``````````diff
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 2134b5e15146c..3c60e8d516a67 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -450,7 +450,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
   /// getInstSizeInBytes() should be verified.
   virtual InstSizeVerifyMode
   getInstSizeVerifyMode(const MachineInstr &MI) const {
-    return InstSizeVerifyMode::NoVerify;
+    return InstSizeVerifyMode::AllowOverEstimate;
   }
 
   /// Return true if the instruction is as cheap as a move instruction.
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 94595ab2b338b..3ad5b3d45ce55 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -193,6 +193,15 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
   ///
   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
+  InstSizeVerifyMode
+  getInstSizeVerifyMode(const MachineInstr &MI) const override {
+    // FIXME: These instructions report an incorrect size, but the ARM constant
+    // islands pass somehow depends on it being incorrect.
+    if (MI.getOpcode() == ARM::tTBB_JT || MI.getOpcode() == ARM::tTBH_JT)
+      return InstSizeVerifyMode::NoVerify;
+    return InstSizeVerifyMode::AllowOverEstimate;
+  }
+
   Register isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
   Register isStoreToStackSlot(const MachineInstr &MI,

``````````

</details>


https://github.com/llvm/llvm-project/pull/221687