[llvm] [InstCombine] Propagate demanded elements through fma/fmuladd (PR #221495)
Hugo Pompougnac via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 7 01:54:03 PDT 2026
https://github.com/qaco updated https://github.com/llvm/llvm-project/pull/221495
>From ef355e3455816ae7e720b70e6d59c828f17177b1 Mon Sep 17 00:00:00 2001
From: Hugo Pompougnac <tech at hugo-pompougnac.fr>
Date: Sat, 5 Sep 2026 22:22:12 +0200
Subject: [PATCH 1/2] [InstCombine] Propagate demanded elements through
fma/fmuladd
---
.../InstCombineSimplifyDemanded.cpp | 12 ++++++++
llvm/test/Transforms/InstCombine/fma.ll | 29 +++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 1002f34de0b8e..ddfe9dc9d8c88 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1991,6 +1991,18 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
PoisonElts = PoisonElts2 & PoisonElts3;
break;
}
+ case Intrinsic::fma:
+ case Intrinsic::fmuladd: {
+ // Elementwise: each result lane uses only the matching operand lane, so
+ // the demand passes through unchanged to every operand.
+ simplifyAndSetOp(II, 0, DemandedElts, PoisonElts2);
+ simplifyAndSetOp(II, 1, DemandedElts, PoisonElts3);
+ APInt PoisonEltsAcc(VWidth, 0);
+ simplifyAndSetOp(II, 2, DemandedElts, PoisonEltsAcc);
+ // A result lane is poison if any operand lane is poison.
+ PoisonElts = PoisonElts2 | PoisonElts3 | PoisonEltsAcc;
+ break;
+ }
default: {
// Handle target specific intrinsics
std::optional<Value *> V = targetSimplifyDemandedVectorEltsIntrinsic(
diff --git a/llvm/test/Transforms/InstCombine/fma.ll b/llvm/test/Transforms/InstCombine/fma.ll
index 4d87610dbc12f..346f9d152c1c8 100644
--- a/llvm/test/Transforms/InstCombine/fma.ll
+++ b/llvm/test/Transforms/InstCombine/fma.ll
@@ -995,3 +995,32 @@ define half @fma_non_negone(half %x, half %y) {
%sub = call half @llvm.fma.f16(half %x, half -1.5, half %y)
ret half %sub
}
+
+declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
+declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>)
+
+; fma is elementwise, so an undemanded result lane makes the matching operand
+; lane undemanded too: the insert into the dropped lane is removed.
+define <4 x float> @fma_undemanded_elt(<4 x float> %a, <4 x float> %b, <4 x float> %c, float %x) {
+; CHECK-LABEL: @fma_undemanded_elt(
+; CHECK-NEXT: [[FMA:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]])
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[FMA]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
+; CHECK-NEXT: ret <4 x float> [[R]]
+;
+ %a3 = insertelement <4 x float> %a, float %x, i64 3
+ %fma = call <4 x float> @llvm.fma.v4f32(<4 x float> %a3, <4 x float> %b, <4 x float> %c)
+ %r = shufflevector <4 x float> %fma, <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
+ ret <4 x float> %r
+}
+
+define <4 x float> @fmuladd_undemanded_elt(<4 x float> %a, <4 x float> %b, <4 x float> %c, float %x) {
+; CHECK-LABEL: @fmuladd_undemanded_elt(
+; CHECK-NEXT: [[FMA:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]])
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[FMA]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
+; CHECK-NEXT: ret <4 x float> [[R]]
+;
+ %b3 = insertelement <4 x float> %b, float %x, i64 3
+ %fma = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %a, <4 x float> %b3, <4 x float> %c)
+ %r = shufflevector <4 x float> %fma, <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
+ ret <4 x float> %r
+}
>From d392cc873b3850416c48c31edf290a0585a090e5 Mon Sep 17 00:00:00 2001
From: Hugo Pompougnac <tech at hugo-pompougnac.fr>
Date: Mon, 7 Sep 2026 10:52:48 +0200
Subject: [PATCH 2/2] After dtcxzyw's review
---
.../InstCombineSimplifyDemanded.cpp | 34 ++++++++++++-------
.../Transforms/InstCombine/minmax-fold.ll | 2 +-
2 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index ddfe9dc9d8c88..27eebb5d36884 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -14,6 +14,7 @@
#include "InstCombineInternal.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/Analysis/VectorUtils.h"
#include "llvm/IR/GetElementPtrTypeIterator.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/PatternMatch.h"
@@ -1991,18 +1992,6 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
PoisonElts = PoisonElts2 & PoisonElts3;
break;
}
- case Intrinsic::fma:
- case Intrinsic::fmuladd: {
- // Elementwise: each result lane uses only the matching operand lane, so
- // the demand passes through unchanged to every operand.
- simplifyAndSetOp(II, 0, DemandedElts, PoisonElts2);
- simplifyAndSetOp(II, 1, DemandedElts, PoisonElts3);
- APInt PoisonEltsAcc(VWidth, 0);
- simplifyAndSetOp(II, 2, DemandedElts, PoisonEltsAcc);
- // A result lane is poison if any operand lane is poison.
- PoisonElts = PoisonElts2 | PoisonElts3 | PoisonEltsAcc;
- break;
- }
default: {
// Handle target specific intrinsics
std::optional<Value *> V = targetSimplifyDemandedVectorEltsIntrinsic(
@@ -2010,6 +1999,27 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
simplifyAndSetOp);
if (V)
return *V;
+
+ // Trivially vectorizable intrinsics operate elementwise: each result lane
+ // uses only the matching lane of the (vector) operands, so the demand
+ // passes through unchanged to every vector operand.
+ Intrinsic::ID IID = II->getIntrinsicID();
+ if (isTriviallyVectorizable(IID)) {
+ APInt PoisonEltsAcc(VWidth, 0);
+ for (Use &Arg : II->args()) {
+ unsigned OpNo = Arg.getOperandNo();
+ // Scalar operands do not carry per-lane demand.
+ if (isVectorIntrinsicWithScalarOpAtArg(IID, OpNo, /*TTI=*/nullptr))
+ continue;
+ APInt OpPoisonElts(VWidth, 0);
+ simplifyAndSetOp(II, OpNo, DemandedElts, OpPoisonElts);
+ PoisonEltsAcc |= OpPoisonElts;
+ }
+ // A result lane is poison if any operand lane is poison, but only for
+ // intrinsics that are known to propagate poison elementwise.
+ if (intrinsicPropagatesPoison(IID))
+ PoisonElts = PoisonEltsAcc;
+ }
break;
}
} // switch on IntrinsicID
diff --git a/llvm/test/Transforms/InstCombine/minmax-fold.ll b/llvm/test/Transforms/InstCombine/minmax-fold.ll
index 3234ed5055f80..35441dc0b0f78 100644
--- a/llvm/test/Transforms/InstCombine/minmax-fold.ll
+++ b/llvm/test/Transforms/InstCombine/minmax-fold.ll
@@ -1416,7 +1416,7 @@ define i8 @PR14613_smax(i8 %x) {
define i8 @PR46271(<2 x i8> %x) {
; CHECK-LABEL: @PR46271(
-; CHECK-NEXT: [[NOT:%.*]] = call <2 x i8> @llvm.smax.v2i8(<2 x i8> [[X:%.*]], <2 x i8> splat (i8 -1))
+; CHECK-NEXT: [[NOT:%.*]] = call <2 x i8> @llvm.smax.v2i8(<2 x i8> [[X:%.*]], <2 x i8> <i8 poison, i8 -1>)
; CHECK-NEXT: [[R:%.*]] = extractelement <2 x i8> [[NOT]], i64 1
; CHECK-NEXT: [[R1:%.*]] = xor i8 [[R]], -1
; CHECK-NEXT: ret i8 [[R1]]
More information about the llvm-commits
mailing list