[llvm] [X86] Support further Zen5 and Zen6 instructions (PR #221659)

[Rohan Shenoy via llvm-commits]

https://github.com/222rohan updated https://github.com/llvm/llvm-project/pull/221659

>From ccf4d8d5461aba38b4d43a8523a80ece9c12ead0 Mon Sep 17 00:00:00 2001
From: Rohan Shenoy <RohanRadhesh.Shenoy at amd.com>
Date: Mon, 7 Sep 2026 12:30:52 +0530
Subject: [PATCH] [X86] Support further Zen5 and Zen6 instructions

Support the following system instructions,
RMPREAD: https://docs.amd.com/v/u/en-US/24594_3.38_APM_Vol3_PUB
RMPOPT: https://docs.amd.com/search/all?query=69201
RMPCHKD (RMP Dirty) : https://docs.amd.com/search/all?query=69203
---
 llvm/lib/Target/X86/X86InstrSNP.td       | 18 ++++++++++++++++++
 llvm/test/MC/Disassembler/X86/x86-64.txt |  9 +++++++++
 llvm/test/MC/X86/SNP-64.s                | 24 ++++++++++++++++++++++++
 3 files changed, 51 insertions(+)

diff --git a/llvm/lib/Target/X86/X86InstrSNP.td b/llvm/lib/Target/X86/X86InstrSNP.td
index 05ed6585db6df..da57f80fe167b 100644
--- a/llvm/lib/Target/X86/X86InstrSNP.td
+++ b/llvm/lib/Target/X86/X86InstrSNP.td
@@ -43,6 +43,21 @@ def RMPADJUST: I<0x01, MRM_FE, (outs), (ins), "rmpadjust", []>, TB, XS,
 let Uses = [RAX, RDX], Defs = [RAX, RCX, RDX, EFLAGS] in
 def RMPQUERY: I<0x01, MRM_FD, (outs), (ins), "rmpquery", []>, TB, XS,
                Requires<[In64BitMode]>;
+
+// F2 0F 01 FD
+let Uses = [RAX, RCX], Defs = [EAX, EFLAGS] in
+def RMPREAD: I<0x01, MRM_FD, (outs), (ins), "rmpread", []>, TB, XD,
+               Requires<[In64BitMode]>;
+
+// F2 0F 01 FC
+let Uses = [RAX, RCX], Defs = [EFLAGS] in
+def RMPOPT: I<0x01, MRM_FC, (outs), (ins), "rmpopt", []>, TB, XD,
+               Requires<[In64BitMode]>;
+
+// F3 0F 01 FC
+let Uses = [RAX, RCX], Defs = [RAX, RCX, EFLAGS] in
+def RMPCHKD: I<0x01, MRM_FC, (outs), (ins), "rmpchkd", []>, TB, XS,
+               Requires<[In64BitMode]>;
 } // SchedRW
 
 def : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>;
@@ -51,3 +66,6 @@ def : InstAlias<"pvalidate\t{%eax, %ecx, %edx|edx, ecx, eax|}", (PVALIDATE32)>,
 def : InstAlias<"rmpupdate\t{%rax, %rcx|rcx, rax|}", (RMPUPDATE)>, Requires<[In64BitMode]>;
 def : InstAlias<"rmpadjust\t{%rax, %rcx, %rdx|rdx, rcx, rax|}", (RMPADJUST)>, Requires<[In64BitMode]>;
 def : InstAlias<"rmpquery\t{%rax, %rdx|rdx, rax|}", (RMPQUERY)>, Requires<[In64BitMode]>;
+def : InstAlias<"rmpread\t{%rax, %rcx|rcx, rax|}", (RMPREAD)>, Requires<[In64BitMode]>;
+def : InstAlias<"rmpopt\t{%rax, %rcx|rcx, rax|}", (RMPOPT)>, Requires<[In64BitMode]>;
+def : InstAlias<"rmpchkd\t{%rax, %rcx|rcx, rax|}", (RMPCHKD)>, Requires<[In64BitMode]>;
diff --git a/llvm/test/MC/Disassembler/X86/x86-64.txt b/llvm/test/MC/Disassembler/X86/x86-64.txt
index 9a18097c8f962..4a6eccc09e78b 100644
--- a/llvm/test/MC/Disassembler/X86/x86-64.txt
+++ b/llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -747,6 +747,15 @@
 # CHECK: rmpquery
 0xf3 0x0f 0x01 0xfd
 
+# CHECK: rmpread
+0xf2 0x0f 0x01 0xfd
+
+# CHECK: rmpopt
+0xf2 0x0f 0x01 0xfc
+
+# CHECK: rmpchkd
+0xf3 0x0f 0x01 0xfc
+
 # CHECK: testui
 0xf3,0x0f,0x01,0xed
 
diff --git a/llvm/test/MC/X86/SNP-64.s b/llvm/test/MC/X86/SNP-64.s
index e2ff66338319c..4b31360e03772 100644
--- a/llvm/test/MC/X86/SNP-64.s
+++ b/llvm/test/MC/X86/SNP-64.s
@@ -20,6 +20,18 @@ rmpadjust %rax, %rcx, %rdx
 // CHECK: encoding: [0xf3,0x0f,0x01,0xfd]
 rmpquery %rax, %rdx
 
+// CHECK: rmpread
+// CHECK: encoding: [0xf2,0x0f,0x01,0xfd]
+rmpread %rax, %rcx
+
+// CHECK: rmpopt
+// CHECK: encoding: [0xf2,0x0f,0x01,0xfc]
+rmpopt %rax, %rcx
+
+// CHECK: rmpchkd
+// CHECK: encoding: [0xf3,0x0f,0x01,0xfc]
+rmpchkd %rax, %rcx
+
 // CHECK: rmpupdate
 // CHECK: encoding: [0xf2,0x0f,0x01,0xfe]
 rmpupdate
@@ -39,3 +51,15 @@ rmpadjust
 // CHECK: rmpquery
 // CHECK: encoding: [0xf3,0x0f,0x01,0xfd]
 rmpquery
+
+// CHECK: rmpread
+// CHECK: encoding: [0xf2,0x0f,0x01,0xfd]
+rmpread
+
+// CHECK: rmpopt
+// CHECK: encoding: [0xf2,0x0f,0x01,0xfc]
+rmpopt
+
+// CHECK: rmpchkd
+// CHECK: encoding: [0xf3,0x0f,0x01,0xfc]
+rmpchkd