[llvm] [AArch64] Reorder ZPR stack spills to maximize ld1b/st1b pairings (PR #218950)

[via llvm-commits]

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@@ -1828,7 +1828,7 @@ void computeCalleeSaveRegisterPairs(const AArch64FrameLowering &AFL,
       case RegPairInfo::PPR:
         break;
       case RegPairInfo::ZPR:
-        if (AFI->getPredicateRegForFillSpill() != 0 &&
+        if (!NeedsWinCFI && AFI->getPredicateRegForFillSpill() != 0 &&
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CarolineConcatto wrote:

Probably we should fix this in another PR. I would not mix different goals in the same PR. 

https://github.com/llvm/llvm-project/pull/218950