[llvm] [BOLT][RISCV] Implement register analysis hooks (PR #220581)

[via llvm-commits]

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@@ -40,6 +40,21 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
 public:
   using MCPlusBuilder::MCPlusBuilder;
 
+  MCPhysReg getFlagsReg() const override { return RISCV::NoRegister; }
+
+  bool isCleanReg(const MCInst &Inst) const override {
+    return Inst.getOpcode() == RISCV::ADDI && Inst.getOperand(1).isReg() &&
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Thrrreeee wrote:

> Do the instruction get uncompressed before this

They are not uniformly uncompressed before this point. I think `C.MV` is a register copy, and its source register cannot be x0, so it should not be recognized as a register-clearing instruction here.

https://github.com/llvm/llvm-project/pull/220581