[llvm] [AArch64][NeoverseV1/V2] Fix extended/shifted-register scheduling for… (PR #220920)

[Julien Villette via llvm-commits]

jvillette38 wrote:

Hello,
@davemgreen, @Asher8118 and @c-rhodes, if needed I can add some instructions to AArch64/Inputs/basic-instructions.s but it modifies lot of targets.
```
@@ -37,6 +37,8 @@ mov      x10, #-63432
 add      wsp, wsp, w10
 add      x25, x9, w25, uxtb
 add      w3, w5, w7
+add      w5, w3, w4, uxtb
+add      w5, w3, w4, uxtw
 add      wzr, w3, w5
 add      w20, wzr, w4
 add      w4, w6, wzr
@@ -79,6 +81,9 @@ adds     w5, w6, w7, asr #21
 adds     w8, w9, w10, asr #31
 adds     x3, x5, x7
 cmn      x3, x5
+adds     w5, w3, w4, uxtb
+adds     w5, w3, w4, uxtw
+adds     x5, x3, x4, uxtx
 adds     x20, xzr, x4
 adds     x4, x6, xzr
 adds     x11, x13, x15
@@ -115,10 +120,15 @@ sub      x2, x3, x4, asr #0
 sub      x5, x6, x7, asr #21
 sub      x8, x9, x10, asr #63
 sub      w13, wsp, w10
+sub      w5, w3, w4, uxtb
+sub      w5, w3, w4, uxtw
 sub      x16, x2, w19, uxtb
 subs     x13, x15, x14, sxtx #1
 subs     w3, w5, w7
 cmp      w3, w5
+subs     w5, w3, w4, uxtb
+subs     w5, w3, w4, uxtw
+subs     x5, x3, w4, uxtb
 subs     w4, w6, wzr
 subs     w11, w13, w15
 subs     w9, w3, wzr, lsl #1
@@ -1379,6 +1389,10 @@ ands     w7, wzr, w9, lsl #1
 ands     x3, x5, x20, ror #63
 bics     w3, w5, w7
 bics     x3, xzr, x3, lsl #1
+ands     w5, w3, w4, lsr #0
+ands     w5, w3, w4, asr #0
+ands     x5, x3, x4, ror #0
+bics     x5, x3, x4, lsr #0
 tst      w3, w7, lsl #31
 tst      x2, x20, asr #2
 mov      x3, x6
```

https://github.com/llvm/llvm-project/pull/220920