[llvm] [GlobalISel][AArch64] Do not remove dst type predicates from pattern children nodes. (PR #221576)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-tablegen

Author: David Green (davemgreen)

<details>
<summary>Changes</summary>

Given an instruction with a non-concrete type (G_CONCAT_VECTOR), with a child pattern instruction with a concrete type (G_FPTRUNC), the concrete type check for the child would incorrectly be removed. This patch makes sure they remain. This makes the match table a little larger, but many should be able to be optimized away (providing that the two operands with the same type can be matched up).

Fixes #<!-- -->221458

---
Full diff: https://github.com/llvm/llvm-project/pull/221576.diff


2 Files Affected:

- (modified) llvm/test/CodeGen/AArch64/fptrunc.ll (+1) 
- (modified) llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp (+7-1) 


``````````diff
diff --git a/llvm/test/CodeGen/AArch64/fptrunc.ll b/llvm/test/CodeGen/AArch64/fptrunc.ll
index 56b20eaac1c80..1e968eeea3d31 100644
--- a/llvm/test/CodeGen/AArch64/fptrunc.ll
+++ b/llvm/test/CodeGen/AArch64/fptrunc.ll
@@ -2,6 +2,7 @@
 ; RUN: llc -mtriple=aarch64 -global-isel=0 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
 ; RUN: llc -mtriple=aarch64 -global-isel=1 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 ; RUN: llc -mtriple=aarch64 -global-isel=1 -mattr=+fullfp16,+bf16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc -mtriple=aarch64 -global-isel=1 -mattr=+bf16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 define float @fptrunc_f64_f32(double %a) {
 ; CHECK-LABEL: fptrunc_f64_f32:
diff --git a/llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp b/llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
index cc1089fc316c7..8d432bceedc70 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
@@ -1628,8 +1628,14 @@ void InstructionMatcher::optimize() {
 
   if (InsnVarID > 0) {
     assert(!Operands.empty() && "Nested instruction is expected to def a vreg");
-    for (auto &OP : Operands[0]->predicates())
+    for (auto &OP : Operands[0]->predicates()) {
+      // LLTOperandMatcher need to be kept as they may have a more specific type
+      // than the parent instruction type.
+      if (const auto *LLTPred = dyn_cast<LLTOperandMatcher>(&*OP))
+        if (!LLTPred->getTy().get().isAnyScalar() && !LLTPred->getTy().get().isAnyVector())
+          continue;
       OP.reset();
+    }
     Operands[0]->eraseNullPredicates();
   }
   for (auto &OM : Operands) {

``````````

</details>


https://github.com/llvm/llvm-project/pull/221576