[llvm] [ARM] Fix instruction sizes for PATCHABLE opcodes (PR #220949)

[Simon Tatham via llvm-commits]

================
@@ -624,6 +624,11 @@ unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
       return 4;
     else
       return 2;
+  case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
+  case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
+  case TargetOpcode::PATCHABLE_TAIL_CALL:
+    // Size of xray sled: Branch + 6 nops.
+    return 28;
----------------
statham-arm wrote:

I admit I haven't ever looked into XRay sleds before, but looking at `ARMMCInstLower.cpp`, it looks to me as if each one is 28 bytes _after_ aligning to 4 bytes, which might or might not cost an extra 2-byte NOP.

But it's not clear from the comments what this function is supposed to do when the size of the (pseudo)instruction is variable!

https://github.com/llvm/llvm-project/pull/220949