[llvm] [DAG][X86] Bitfield insertion can combine into SHL + SHRD (PR #220182)

[Simon Pilgrim via llvm-commits]

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@@ -53859,6 +53859,61 @@ static SDValue combineOrXorWithSETCC(unsigned Opc, const SDLoc &DL, EVT VT,
   return SDValue();
 }
 
+// Fold an OR with a masked destination and a left-shifted
+// source into a shift + double-precision shift (SHRD):
+static SDValue combineOrOnSHLToSHRD(SDNode *N, SDLoc &DL, SelectionDAG &DAG,
+                                    const X86Subtarget &Subtarget) {
+  using namespace SDPatternMatch;
+  assert(N->getOpcode() == ISD::OR && "Invalid Node. Expected OR.");
+
+  // If optimizing for code size, run irrespective of slow SHLD.
+  // If not optimizing for code size and SHLD is slow, then bail.
+  bool IsOptSize = DAG.getMachineFunction().getFunction().hasOptSize();
+  if (!IsOptSize && Subtarget.isSHLDSlow())
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RKSimon wrote:

What happens if we always allow the fold pre-legalization? How good is the expansion back from SHL+FSHR?

https://github.com/llvm/llvm-project/pull/220182