[llvm] [TTI/RISCV] Strip getMaxVScale (PR #220547)
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Wed Sep 2 10:46:40 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-analysis
Author: Ramkumar Ramachandra (artagnon)
<details>
<summary>Changes</summary>
RISC-V is the only target using it at the moment, and it is unnecessary, as frontends insert a vscale_range attribute that we can use. As such, this patch is a non-functional cleanup, along with test updates, taking care to minimize the diff by inserting the vscale_range attribute in various tests.
---
Patch is 305.00 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/220547.diff
51 Files Affected:
- (modified) llvm/include/llvm/Analysis/TargetTransformInfo.h (-4)
- (modified) llvm/lib/Analysis/TargetTransformInfo.cpp (-4)
- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (-6)
- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h (-1)
- (modified) llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp (+3-7)
- (modified) llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h (+1-2)
- (modified) llvm/lib/Transforms/Vectorize/LoopVectorize.cpp (+3-4)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll (+7-9)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll (+3-3)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll (+10-10)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll (+78-103)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll (+2-5)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/indvar-overflow-check-scalable-tc.ll (+3-3)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll (+6-10)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll (+11-11)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll (+4-6)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll (+12-21)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll (+12-20)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/predicated-costs.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-prune-vf.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll (+17-17)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/runtime-check-dependent-on-stride.ll (+3-3)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll (+12-12)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll (+7-7)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/scalable-vf-hint.ll (+15-18)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-i64-rv32.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll (+31-99)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll (+30-31)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-bin-unary-ops-args.ll (+140-153)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-div.ll (+32-40)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll (+16-21)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll (+6-9)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-safe-dep-distance.ll (+9-11)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll (+7-7)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll (+7-30)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll (+40-40)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/zvl1024b-crash.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/RISCV/partial-reduce-dot-product.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/RISCV/reductions-evl.ll (+15-15)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics.ll (+137-94)
- (modified) llvm/test/Transforms/PhaseOrdering/RISCV/any-of-vectorization.ll (+1-1)
- (modified) llvm/test/Transforms/PhaseOrdering/loop-vectorize-bfi.ll (+1-1)
``````````diff
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index 5e22b890ec975..6f620366f73b8 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -1366,10 +1366,6 @@ class TargetTransformInfo {
/// \return The width of the smallest vector register type.
LLVM_ABI unsigned getMinVectorRegisterBitWidth() const;
- /// \return The maximum value of vscale if the target specifies an
- /// architectural maximum vector length, and std::nullopt otherwise.
- LLVM_ABI std::optional<unsigned> getMaxVScale() const;
-
/// \return the value of vscale to tune the cost model for.
LLVM_ABI std::optional<unsigned> getVScaleForTuning() const;
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index 67dee54028c0e..71f55f2e7e046 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -839,10 +839,6 @@ unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
return TTIImpl->getMinVectorRegisterBitWidth();
}
-std::optional<unsigned> TargetTransformInfo::getMaxVScale() const {
- return TTIImpl->getMaxVScale();
-}
-
std::optional<unsigned> TargetTransformInfo::getVScaleForTuning() const {
return TTIImpl->getVScaleForTuning();
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index cd14ff3d2dded..9538697368a89 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -444,12 +444,6 @@ bool RISCVTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
}
}
-std::optional<unsigned> RISCVTTIImpl::getMaxVScale() const {
- if (ST->hasVInstructions())
- return ST->getRealMaxVLen() / RISCV::RVVBitsPerBlock;
- return BaseT::getMaxVScale();
-}
-
std::optional<unsigned> RISCVTTIImpl::getVScaleForTuning() const {
if (ST->hasVInstructions())
if (unsigned MinVLen = ST->getRealMinVLen();
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 447c3d7c3326e..4523ebd6ae892 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -128,7 +128,6 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
return ST->hasVInstructions() ? TailFoldingStyle::DataWithEVL
: TailFoldingStyle::None;
}
- std::optional<unsigned> getMaxVScale() const override;
std::optional<unsigned> getVScaleForTuning() const override;
TypeSize
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
index c464c7894ae5c..31d3f49e167f0 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
@@ -301,11 +301,7 @@ ElementCount VFSelectionContext::getMaximizedVFForTarget(
return MaxVF;
}
-std::optional<unsigned> llvm::getMaxVScale(const Function &F,
- const TargetTransformInfo &TTI) {
- if (std::optional<unsigned> MaxVScale = TTI.getMaxVScale())
- return MaxVScale;
-
+std::optional<unsigned> llvm::getMaxVScale(const Function &F) {
if (F.hasFnAttribute(Attribute::VScaleRange))
return F.getFnAttribute(Attribute::VScaleRange).getVScaleRangeMax();
@@ -359,7 +355,7 @@ bool VFSelectionContext::isScalableVectorizationAllowed() {
return false;
}
- if (!Legal->isSafeForAnyVectorWidth() && !getMaxVScale(F, TTI)) {
+ if (!Legal->isSafeForAnyVectorWidth() && !getMaxVScale(F)) {
reportVectorizationInfo("The target does not provide maximum vscale value "
"for safe distance analysis.",
"ScalableVFUnfeasible", ORE, TheLoop);
@@ -380,7 +376,7 @@ VFSelectionContext::getMaxLegalScalableVF(unsigned MaxSafeElements) {
if (Legal->isSafeForAnyVectorWidth())
return MaxScalableVF;
- std::optional<unsigned> MaxVScale = getMaxVScale(F, TTI);
+ std::optional<unsigned> MaxVScale = getMaxVScale(F);
// Limit MaxScalableVF by the maximum safe dependence distance.
MaxScalableVF = ElementCount::getScalable(MaxSafeElements / *MaxVScale);
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
index 2e5b0f64bfed2..da0616d371f2c 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
@@ -56,8 +56,7 @@ extern cl::opt<bool> PreferInLoopReductions;
/// \return An upper bound for vscale based on TTI or the vscale_range
/// attribute.
-std::optional<unsigned> getMaxVScale(const Function &F,
- const TargetTransformInfo &TTI);
+std::optional<unsigned> getMaxVScale(const Function &F);
// Utility functions that are used by different vectorization classes
namespace LoopVectorizationUtils {
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index ba0421869216f..22aa221e4f652 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -1927,8 +1927,7 @@ static bool isIndvarOverflowCheckKnownFalse(
uint64_t MaxVF = VF.getKnownMinValue();
uint64_t MaxTC = TC->getKnownMinValue();
if (VF.isScalable() || TC->isScalable()) {
- std::optional<unsigned> MaxVScale =
- getMaxVScale(*Cost->TheFunction, Cost->TTI);
+ std::optional<unsigned> MaxVScale = getMaxVScale(*Cost->TheFunction);
if (!MaxVScale)
return false;
if (VF.isScalable())
@@ -3002,7 +3001,7 @@ LoopVectorizationCostModel::computeMaxVF(ElementCount UserVF, unsigned UserIC) {
std::optional<unsigned> MaxPowerOf2RuntimeVF =
MaxFactors.FixedVF.getFixedValue();
if (MaxFactors.ScalableVF) {
- std::optional<unsigned> MaxVScale = getMaxVScale(*TheFunction, TTI);
+ std::optional<unsigned> MaxVScale = getMaxVScale(*TheFunction);
if (MaxVScale) {
MaxPowerOf2RuntimeVF = std::max<unsigned>(
*MaxPowerOf2RuntimeVF,
@@ -5944,7 +5943,7 @@ DenseMap<const SCEV *, Value *> LoopVectorizationPlanner::executePlan(
RUN_VPLAN_PASS(VPlanTransforms::materializeBackedgeTakenCount, BestVPlan,
VectorPH);
std::optional<uint64_t> MaxRuntimeStep;
- if (auto MaxVScale = getMaxVScale(*OrigLoop->getHeader()->getParent(), TTI))
+ if (auto MaxVScale = getMaxVScale(*OrigLoop->getHeader()->getParent()))
MaxRuntimeStep = uint64_t(*MaxVScale) * BestVF.getKnownMinValue() * BestUF;
assert((LI->getUniqueLatchExitBlock(*OrigLoop) || RequiresScalarEpilogue) &&
"loops not exiting via the latch without required epilogue?");
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll b/llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
index 333f20a0d8d06..024dc163b377b 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
@@ -539,7 +539,7 @@ exit:
ret void
}
-attributes #0 = { "target-features"="+64bit,+v" }
+attributes #0 = { "target-features"="+64bit,+v" vscale_range(4, 1024) }
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll b/llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
index 23d9b5c5b7c52..139498a0b3b26 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
@@ -5,7 +5,7 @@ target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
; Test with a dead load in the loop, from
; https://github.com/llvm/llvm-project/issues/99701
-define void @dead_load(ptr %p, i16 %start) {
+define void @dead_load(ptr %p, i16 %start) vscale_range(4, 1024) {
; CHECK-LABEL: define void @dead_load(
; CHECK-SAME: ptr [[P:%.*]], i16 [[START:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
@@ -58,7 +58,7 @@ exit:
; Loop with a live-out %l and scalar epilogue required due to an interleave
; group. As the scalar epilogue is required the live-out is fed from the scalar
; epilogue and dead in the vector loop.
-define i8 @dead_live_out_due_to_scalar_epilogue_required(ptr %src, ptr %dst) {
+define i8 @dead_live_out_due_to_scalar_epilogue_required(ptr %src, ptr %dst) vscale_range(4, 1024) {
; CHECK-LABEL: define i8 @dead_live_out_due_to_scalar_epilogue_required(
; CHECK-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
@@ -128,7 +128,7 @@ exit:
; Test case for https://github.com/llvm/llvm-project/issues/106780.
-define i32 @cost_of_exit_branch_and_cond_insts(ptr %a, ptr %b, i1 %c, i16 %x) #0 {
+define i32 @cost_of_exit_branch_and_cond_insts(ptr %a, ptr %b, i1 %c, i16 %x) vscale_range(2, 1024) {
; CHECK-LABEL: define i32 @cost_of_exit_branch_and_cond_insts(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i1 [[C:%.*]], i16 [[X:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
@@ -267,9 +267,9 @@ return:
}
; Test case for https://github.com/llvm/llvm-project/issues/107473.
-define void @test_phi_in_latch_redundant(ptr %dst, i32 %a) {
+define void @test_phi_in_latch_redundant(ptr %dst, i32 %a) vscale_range(2, 1024) {
; CHECK-LABEL: define void @test_phi_in_latch_redundant(
-; CHECK-SAME: ptr [[DST:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr [[DST:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -318,9 +318,9 @@ exit:
}
; Test for https://github.com/llvm/llvm-project/issues/108098.
-define void @gather_interleave_group_with_dead_insert_pos(i64 %N, ptr noalias %src, ptr noalias %dst) #0 {
+define void @gather_interleave_group_with_dead_insert_pos(i64 %N, ptr noalias %src, ptr noalias %dst) vscale_range(4, 1024) {
; CHECK-LABEL: define void @gather_interleave_group_with_dead_insert_pos(
-; CHECK-SAME: i64 [[N:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR1]] {
+; CHECK-SAME: i64 [[N:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0)
; CHECK-NEXT: [[TMP0:%.*]] = add nuw i64 [[SMAX]], 1
@@ -377,8 +377,6 @@ exit:
ret void
}
-attributes #0 = { "target-features"="+64bit,+v" }
-
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll b/llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
index 3fd90b2848848..87143af37e76b 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
@@ -10,7 +10,7 @@
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
target triple = "riscv64"
-define void @vector_add(ptr noalias nocapture %a, i64 %v) {
+define void @vector_add(ptr noalias nocapture %a, i64 %v) vscale_range(4, 1024) {
; CHECK-LABEL: @vector_add(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
@@ -53,7 +53,7 @@ for.end:
ret void
}
-define i64 @vector_add_reduce(ptr noalias nocapture %a) {
+define i64 @vector_add_reduce(ptr noalias nocapture %a) vscale_range(4, 1024) {
; CHECK-LABEL: @vector_add_reduce(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
@@ -72,7 +72,7 @@ define i64 @vector_add_reduce(ptr noalias nocapture %a) {
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP13]], [[INDEX]]
; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP13]]
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
-; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: middle.block:
; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[TMP9]])
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll b/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
index d02dc36f7a6ae..8bbf90793da01 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
@@ -7,7 +7,7 @@
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
target triple = "riscv64"
-define void @vector_udiv(ptr noalias nocapture %a, i64 %v, i64 %n) {
+define void @vector_udiv(ptr noalias nocapture %a, i64 %v, i64 %n) vscale_range(2, 1024) {
; CHECK-LABEL: @vector_udiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
@@ -71,7 +71,7 @@ for.end:
ret void
}
-define void @vector_sdiv(ptr noalias nocapture %a, i64 %v, i64 %n) {
+define void @vector_sdiv(ptr noalias nocapture %a, i64 %v, i64 %n) vscale_range(2, 1024) {
; CHECK-LABEL: @vector_sdiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
@@ -135,7 +135,7 @@ for.end:
ret void
}
-define void @vector_urem(ptr noalias nocapture %a, i64 %v, i64 %n) {
+define void @vector_urem(ptr noalias nocapture %a, i64 %v, i64 %n) vscale_range(2, 1024) {
; CHECK-LABEL: @vector_urem(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
@@ -199,7 +199,7 @@ for.end:
ret void
}
-define void @vector_srem(ptr noalias nocapture %a, i64 %v, i64 %n) {
+define void @vector_srem(ptr noalias nocapture %a, i64 %v, i64 %n) vscale_range(2, 1024) {
; CHECK-LABEL: @vector_srem(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
@@ -263,7 +263,7 @@ for.end:
ret void
}
-define void @predicated_udiv(ptr noalias nocapture %a, i64 %v, i64 %n) {
+define void @predicated_udiv(ptr noalias nocapture %a, i64 %v, i64 %n) vscale_range(2, 1024) {
; CHECK-LABEL: @predicated_udiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
@@ -339,7 +339,7 @@ for.end:
ret void
}
-define void @predicated_sdiv(ptr noalias nocapture %a, i64 %v, i64 %n) {
+define void @predicated_sdiv(ptr noalias nocapture %a, i64 %v, i64 %n) vscale_range(2, 1024) {
; CHECK-LABEL: @predicated_sdiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
@@ -415,7 +415,7 @@ for.end:
ret void
}
-define void @predicated_udiv_by_constant(ptr noalias nocapture %a, i64 %n) {
+define void @predicated_udiv_by_constant(ptr noalias nocapture %a, i64 %n) vscale_range(2, 1024) {
; CHECK-LABEL: @predicated_udiv_by_constant(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
@@ -485,7 +485,7 @@ for.end:
ret void
}
-define void @predicated_sdiv_by_constant(ptr noalias nocapture %a, i64 %n) {
+define void @predicated_sdiv_by_constant(ptr noalias nocapture %a, i64 %n) vscale_range(2, 1024) {
; CHECK-LABEL: @predicated_sdiv_by_constant(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
@@ -555,7 +555,7 @@ for.end:
ret void
}
-define void @predicated_sdiv_by_minus_one(ptr noalias nocapture %a, i64 %n) {
+define void @predicated_sdiv_by_minus_one(ptr noalias nocapture %a, i64 %n) vscale_range(2, 1024) {
; CHECK-LABEL: @predicated_sdiv_by_minus_one(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
@@ -628,7 +628,7 @@ for.end:
; Test for https://github.com/llvm/llvm-project/issues/159402. For invariant divisors,
; selects can be introduced outside the vector loop and their cost should not be
; considered for each loop iteration.
-define void @udiv_sdiv_with_invariant_divisors(i8 %x, i16 %y, i1 %c, ptr %p) {
+define void @udiv_sdiv_with_invariant_divisors(i8 %x, i16 %y, i1 %c, ptr %p) vscale_range(2, 1024) {
; CHECK-LABEL: @udiv_sdiv_with_invariant_divisors(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll b/llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
index 5fe69bb581e47..1a62621fc92e2 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
@@ -19,7 +19,7 @@ define i64 @pr97452_scalable_vf1_for(ptr %src, ptr noalias %dst) #0 {
; CHECK-NEXT: [[VECTOR_RECUR_INIT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 0, i32 [[TMP5]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <vscale x 2 x i64> [ [[VECTOR_RECUR_INIT]], %[[VECTOR_PH]] ], [ [[VP_OP_LOAD:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 23, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[PREV_EVL:%.*]] = phi i32 [ [[TMP2]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
@@ -30,7 +30,7 @@ define i64 @pr97452_scalable_vf1_for(ptr %src, ptr noalias %dst) #0 {
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[EVL_BASED_IV]]
; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP10]], ptr align 8 [[TMP11]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])
; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP6]] to i64
-; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP12]], [[EVL_BASED_IV]]
+; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP12]], [[EVL_BASED_IV]]
; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP12]]
; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll b/llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
index 449d260d878bd..b6050309e4cc1 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
@@ -1,24 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; FIXME: fmaximumnum/fminimumnum have no vectorizing support yet.
; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+v,+zvfh" -S < %s | FileCheck %s
; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+v,+zvfhmin" -S < %s | FileCheck %s --check-prefix=ZVFHMIN
-define void @fmin32(ptr noundef readonly captures(none) %input1, ptr noundef readonly captures(none) %input2, ptr noundef writeonly captures(none) %output) {
+define void @fmin32(ptr noundef readonly captures(none) %input1, ptr noundef readonly captures(none) %input2, ptr noundef writeonly captures(none) %output) vscale_range(2, 1024) {
; CHECK-LABEL: define void @fmin32(
; CHECK-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[INPUT23:%.*]] = ptrtoaddr ptr [[INPUT2]] to i64
; CHECK-NEXT: [[INPUT12:%.*]] = ptrtoaddr ptr [[INPUT1]] to i64
; CHECK-NEXT: [[OUTPUT1:%.*]] = ptrtoaddr ptr [[OUTPUT]] to i64
-; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT: [[TMP13:%.*]] = shl nuw i64 [[TMP8]], 2
-; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP13]], i64 17)
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP14]]
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
; CHECK: [[VECTOR_MEMCHECK]]:
; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT: [[TMP4:%.*]] = shl i64 [[TMP15]...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/220547
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