[llvm] [LLVM][CodeGen][SVE] Improve code quality of predicate vector extracts. (PR #220254)

[Paul Walker via llvm-commits]

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@@ -32214,6 +32214,28 @@ void AArch64TargetLowering::ReplaceExtractSubVectorResults(
   SDLoc DL(N);
   EVT VT = N->getValueType(0);
 
+  if (VT.isFixedLengthVectorOf(MVT::i1)) {
+    EVT NewEltVT;
+    switch (VT.getVectorMinNumElements()) {
+    case 2:
+      NewEltVT = MVT::i32;
+      break;
+    case 4:
+      NewEltVT = MVT::i16;
+      break;
+    default:
+      NewEltVT = MVT::i8;
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paulwalker-arm wrote:

The transformation is safe for single element vector types, so there's no reason to assert?

https://github.com/llvm/llvm-project/pull/220254