[llvm] [AArch64] Support wide interleaved store combine (PR #217856)

[Kamlesh Kumar via llvm-commits]

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@@ -28055,26 +28055,71 @@ performInterleavedStoreCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
 
   const AArch64Subtarget &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
   // Fixed length vector using NEON
-  if (!IsMasked && (SubBits == 64 || SubBits == 128) &&
-      Subtarget.isNeonAvailable()) {
+  if (!IsMasked && Subtarget.isNeonAvailable()) {
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kamleshbhalui wrote:

I experimented with your suggestions, and It seems nice. I will update this PR.

https://github.com/llvm/llvm-project/pull/217856