[llvm] [AMDGPU] Fix LDS bank count for gfx704 and gfx950 (PR #220632)

[Chinmay Deshpande via llvm-commits]

https://github.com/chinmaydd updated https://github.com/llvm/llvm-project/pull/220632

>From cae8f2bde1a9e18976537c4a27017b82e6174971 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Wed, 2 Sep 2026 11:59:19 -0400
Subject: [PATCH 1/3] AMDGPU: Fix LDS bank count for gfx704 and gfx950

Both inherited a bank count that does not match the hardware: Bonaire
has 16 banks, and gfx950 doubled the count to 64 along with its larger
LDS. The ROCm device metadata has reported these values all along, so
the subtarget and the TargetParser table were the outliers.

Moving the count out of FeatureISAVersion9_4_Common is required because
the emitter rejects a GPU whose feature closure sets a field twice.

Change-Id: I9b6fb9edafbf3f2c5eb834308cc8388604382160
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
---
 llvm/lib/Target/AMDGPU/AMDGPU.td                 | 6 ++++--
 llvm/unittests/TargetParser/TargetParserTest.cpp | 4 ++++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index dc559a4523a9c..f4edf50d51db6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1870,7 +1870,7 @@ def FeatureISAVersion7_0_3 : FeatureSet<
 
 def FeatureISAVersion7_0_4 : FeatureSet<
   [FeatureSeaIslands,
-   FeatureLDSBankCount32]>;
+   FeatureLDSBankCount16]>;
 
 def FeatureISAVersion7_0_5 : FeatureSet<
   [FeatureSeaIslands,
@@ -2017,7 +2017,6 @@ def FeatureISAVersion9_4_Common : FeatureSet<
    FeatureGFX940Insts,
    FeatureRequiresAlignedVGPRs,
    FeatureFmaMixInsts,
-   FeatureLDSBankCount32,
    FeatureDLInsts,
    FeatureFmacF64Inst,
    FeatureDot1Insts,
@@ -2059,6 +2058,7 @@ def FeatureISAVersion9_4_Common : FeatureSet<
 def FeatureISAVersion9_5_Common : FeatureSet<
   !listconcat(FeatureISAVersion9_4_Common.Features,
   [FeatureAddressableLocalMemorySize163840,
+   FeatureLDSBankCount64,
    FeatureFP8Insts,
    FeatureFP8ConversionInsts,
    FeatureCvtFP8SDWASrcSel,
@@ -2080,6 +2080,7 @@ def FeatureISAVersion9_4_2 : FeatureSet<
   !listconcat(FeatureISAVersion9_4_Common.Features,
     [
       FeatureAddressableLocalMemorySize65536,
+      FeatureLDSBankCount32,
       FeatureFP8Insts,
       FeatureFP8ConversionInsts,
       FeatureCvtFP8SDWASrcSel,
@@ -2090,6 +2091,7 @@ def FeatureISAVersion9_4_2 : FeatureSet<
 def FeatureISAVersion9_4_Generic : FeatureSet<
   !listconcat(FeatureISAVersion9_4_Common.Features,
     [FeatureAddressableLocalMemorySize65536,
+     FeatureLDSBankCount32,
      FeatureRequiresCOV6])>;
 
 def FeatureISAVersion9_5_0 : FeatureSet<FeatureISAVersion9_5_Common.Features>;
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index e61d64d5bad28..bb83e33bab6f6 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -3164,7 +3164,10 @@ TEST(TargetParserTest, testAMDGPUgetNumWorkGroupSIMDs) {
 
 TEST(TargetParserTest, testAMDGPUgetLDSBankCount) {
   EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch702), 16u);
+  EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch704), 16u);
   EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch900), 32u);
+  EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch942), 32u);
+  EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch950), 64u);
   EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch1030), 32u);
   EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch1200), 32u);
   // gfx12.5 doubled the bank count.
@@ -3172,6 +3175,7 @@ TEST(TargetParserTest, testAMDGPUgetLDSBankCount) {
 
   // The GPUKind overload resolves to the same values.
   EXPECT_EQ(AMDGPU::getLDSBankCount(AMDGPU::GK_GFX900), 32u);
+  EXPECT_EQ(AMDGPU::getLDSBankCount(AMDGPU::GK_GFX950), 64u);
   EXPECT_EQ(AMDGPU::getLDSBankCount(AMDGPU::GK_GFX1250), 64u);
   EXPECT_EQ(AMDGPU::getLDSBankCount(AMDGPU::GK_GFX1251), 64u);
 }

>From be3bc93c6bd0ff7fbfed689cb30d836fe6cd03cd Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Wed, 2 Sep 2026 09:03:28 -0700
Subject: [PATCH 2/3] Update AMDGPU.td

---
 llvm/lib/Target/AMDGPU/AMDGPU.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index f4edf50d51db6..1e6e1461394c8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1874,7 +1874,7 @@ def FeatureISAVersion7_0_4 : FeatureSet<
 
 def FeatureISAVersion7_0_5 : FeatureSet<
   [FeatureSeaIslands,
-   FeatureLDSBankCount16]>;
+   FeatureLDSBankCount32]>;
 
 def FeatureISAVersion8_0_Common : FeatureSet<
   [FeatureVolcanicIslands,

>From b13a22e02c62af00cfc907d12ea172945f70755e Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Wed, 2 Sep 2026 09:04:42 -0700
Subject: [PATCH 3/3] Apply batched suggestions from code review

Co-authored-by: Chinmay Deshpande <chdeshpa at amd.com>
---
 llvm/lib/Target/AMDGPU/AMDGPU.td                 | 4 ++--
 llvm/unittests/TargetParser/TargetParserTest.cpp | 1 -
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 1e6e1461394c8..e0316f094a165 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1870,11 +1870,11 @@ def FeatureISAVersion7_0_3 : FeatureSet<
 
 def FeatureISAVersion7_0_4 : FeatureSet<
   [FeatureSeaIslands,
-   FeatureLDSBankCount16]>;
+   FeatureLDSBankCount32]>;
 
 def FeatureISAVersion7_0_5 : FeatureSet<
   [FeatureSeaIslands,
-   FeatureLDSBankCount32]>;
+   FeatureLDSBankCount16]>;
 
 def FeatureISAVersion8_0_Common : FeatureSet<
   [FeatureVolcanicIslands,
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index bb83e33bab6f6..3f1d965bfefd9 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -3164,7 +3164,6 @@ TEST(TargetParserTest, testAMDGPUgetNumWorkGroupSIMDs) {
 
 TEST(TargetParserTest, testAMDGPUgetLDSBankCount) {
   EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch702), 16u);
-  EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch704), 16u);
   EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch900), 32u);
   EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch942), 32u);
   EXPECT_EQ(AMDGPU::getLDSBankCount(Triple::AMDGPUSubArch950), 64u);