[llvm] [AArch64] Reorder ZPR stack spills to maximize ld1b/st1b pairings (PR #218950)

[Kieran B via llvm-commits]

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@@ -2797,6 +2797,94 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
   AFI->setSVECalleeSavedStackSize(ZPRCSStackSize, alignTo(PPRCSStackSize, 16));
 }
 
+static void orderZPRCalleeSavesForPairs(MachineFunction &MF,
+                                        const TargetRegisterInfo *RegInfo,
+                                        std::vector<CalleeSavedInfo> &CSI) {
+  // Reorder callee-saved ZPRs to maximize pairing which requires
+  // consecutive even/odd registers at even scaled stack offsets.
+  // Additional requirements are checked when the register pairs are formed.
+  assert(!isTargetWindows(MF) &&
+         "ZPR callee-save reordering not supported on Windows");
+
+  auto *AFI = MF.getInfo<AArch64FunctionInfo>();
+  if (!AFI->getPredicateRegForFillSpill())
+    return;
+
+  SmallVector<CalleeSavedInfo> ZPRSaves;
+  SmallVector<size_t> ZPRPositions;
+
+  for (auto [Index, CS] : llvm::enumerate(CSI)) {
+    if (AArch64::ZPRRegClass.contains(CS.getReg())) {
+      ZPRSaves.push_back(CS);
+      ZPRPositions.push_back(Index);
+    }
+  }
+
+  if (ZPRSaves.size() < 2)
+    return;
+
+  llvm::sort(ZPRSaves, [](const auto &A, const auto &B) {
+    return A.getReg() < B.getReg();
+  });
+
+  SmallVector<std::pair<CalleeSavedInfo, CalleeSavedInfo>> Pairs;
+  SmallVector<CalleeSavedInfo> Singles;
+  for (size_t i = 0; i < ZPRSaves.size();) {
+    if (i + 1 < ZPRSaves.size() &&
+        ZPRSaves[i + 1].getReg() == ZPRSaves[i].getReg() + 1 &&
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kieroxide wrote:

Done.

https://github.com/llvm/llvm-project/pull/218950