[llvm] [AArch64] Improve scalar fixed-point int-to-fp codegen (PR #220299)

[Vimal Patel via llvm-commits]

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@@ -43,17 +43,109 @@ define float @do_stuff(<8 x i16> noundef %var_135) {
 ; CHECK-LABEL: do_stuff:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    umaxv.8h h0, v0
-; CHECK-NEXT:    ucvtf s0, s0, #1
+; CHECK-NEXT:    fmov w8, s0
+; CHECK-NEXT:    ucvtf s0, w8, #1
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pvimal816a wrote:

Actually, with this PR int_aarch64_neon_vcvtfxu2fp will lower to a variant of `scvtf/ucvtf` whose first input operand is in GPR unless it's a result of `bitcast`. This is not true in this case and that's why we've `fmov` just above `ucvtf` here. To fix this case in forward direction I was thinking to add additional patterns to match `vector-extract + int_aarch64_neon_vcvtfxu2fp` to avoid roundtrip to GPR bank. But, that'' increase the scope of this PR, so I can do that as a follow-up PR.

https://github.com/llvm/llvm-project/pull/220299