[llvm] [RISCV] Disable register overlap for vector indexed loads. (PR #220079)

[Pengcheng Wang via llvm-commits]

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@@ -1898,9 +1898,10 @@ multiclass VPseudoILoad<bit Ordered> {
           defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = dataEMUL.vrclass;
           defvar IdxVreg = idxEMUL.vrclass;
-          defvar HasConstraint = !ne(dataEEW, idxEEW);
-          defvar TypeConstraints = 
-            !if(!eq(dataEEW, idxEEW), 1, !if(!gt(dataEEW, idxEEW), !if(!ge(idxEMULOctuple, 8), 3, 1), 2));
+          // Don't allow overlapping registers even though it's allowed by the
+          // spec due to hardware issue on some CPUs.
+          defvar HasConstraint = true;
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wangpc-pp wrote:

I discussed with my team and the conclusion is that this should be implementation-specific. We need a broader discussion.

https://github.com/llvm/llvm-project/pull/220079