[llvm] 7a199bd - AMDGPU: Fix using legacy triples in more tests (#220220)

[via llvm-commits]

Author: Matt Arsenault
Date: 2026-09-01T12:04:30Z
New Revision: 7a199bdb4fd7e7f0c74aafdd80735e9b3dfe661b

URL: https://github.com/llvm/llvm-project/commit/7a199bdb4fd7e7f0c74aafdd80735e9b3dfe661b
DIFF: https://github.com/llvm/llvm-project/commit/7a199bdb4fd7e7f0c74aafdd80735e9b3dfe661b.diff

LOG: AMDGPU: Fix using legacy triples in more tests (#220220)

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/coexec-hazardrec-preRA.mir
    llvm/test/CodeGen/AMDGPU/perm-uniform-bytes.ll
    llvm/test/CodeGen/AMDGPU/wmma-trans-multi-shadow-hazard.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/coexec-hazardrec-preRA.mir b/llvm/test/CodeGen/AMDGPU/coexec-hazardrec-preRA.mir
index 43a735248ea5a..3d11b0dba1fcf 100644
--- a/llvm/test/CodeGen/AMDGPU/coexec-hazardrec-preRA.mir
+++ b/llvm/test/CodeGen/AMDGPU/coexec-hazardrec-preRA.mir
@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched %s -o - | FileCheck -check-prefix=CHECK %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched -debug-only=gcn-hazard-recognizer %s -o /dev/null 2>&1 | FileCheck -check-prefix=DBG %s
+# RUN: llc -mtriple=amdgpu12.50 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched %s -o - | FileCheck -check-prefix=CHECK %s
+# RUN: llc -mtriple=amdgpu12.50 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched -debug-only=gcn-hazard-recognizer %s -o /dev/null 2>&1 | FileCheck -check-prefix=DBG %s
 
 # REQUIRES: asserts
 

diff  --git a/llvm/test/CodeGen/AMDGPU/perm-uniform-bytes.ll b/llvm/test/CodeGen/AMDGPU/perm-uniform-bytes.ll
index 13ec3dcec7176..6a6e7675eb407 100644
--- a/llvm/test/CodeGen/AMDGPU/perm-uniform-bytes.ll
+++ b/llvm/test/CodeGen/AMDGPU/perm-uniform-bytes.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O2 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -O2 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=GFX10 %s
 
 ; Verify that uniform (SGPR) byte-packing operations produce v_perm_b32
 ; instead of scalar s_and/s_lshl/s_or sequences. The OR and AND DAG combines

diff  --git a/llvm/test/CodeGen/AMDGPU/wmma-trans-multi-shadow-hazard.mir b/llvm/test/CodeGen/AMDGPU/wmma-trans-multi-shadow-hazard.mir
index 4a37ebce24a78..b54bf471890b4 100644
--- a/llvm/test/CodeGen/AMDGPU/wmma-trans-multi-shadow-hazard.mir
+++ b/llvm/test/CodeGen/AMDGPU/wmma-trans-multi-shadow-hazard.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched %s -o - | FileCheck -check-prefix=CHECK %s
+# RUN: llc -mtriple=amdgpu12.50 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched %s -o - | FileCheck -check-prefix=CHECK %s
 
 # Tests for the multi-shadow hazard: WMMA + TRANS + VALU cannot all execute
 # simultaneously. When both a WMMA and a TRANS instruction are actively