[llvm] [AArch64] Replace uses of AArch64::NoRegister with Register() or isValid() NFC (PR #220227)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 1 04:47:37 PDT 2026
https://github.com/janr-bay created https://github.com/llvm/llvm-project/pull/220227
This came up during work on another PR, @topperc suggested it as ongoing work [here](https://github.com/llvm/llvm-project/pull/210992#discussion_r3738407180). This replaces all remaining uses for aarch64, similar to previous changes for the [RISCV backend](https://github.com/llvm/llvm-project/commit/62791b43774615b24d565130c8c3f1e6e5145dd8#diff-b2797a1529366b39522e2b80e2719e331875ec3f70214b2a4ce9524821d471b9) and [AMDGPU backend](https://github.com/llvm/llvm-project/commit/191d70f2f52d9cd38e0c57f8319b466eff1ac023)
>From 9b46cc5fcafe16b6d03d92a63762698f641fc5b2 Mon Sep 17 00:00:00 2001
From: Jan Rehders <jrehders at baylibre.com>
Date: Tue, 11 Aug 2026 13:48:11 +0200
Subject: [PATCH 1/2] [AArch64] Replace uses of AArch64::NoRegister with
Register() or isValid() NFC
---
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 12 ++++++------
.../Target/AArch64/AArch64FrameLowering.cpp | 18 +++++++++---------
.../lib/Target/AArch64/AArch64ISelLowering.cpp | 8 ++++----
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 4 ++--
.../AArch64/AArch64LoadStoreOptimizer.cpp | 8 ++++----
.../Target/AArch64/AArch64MIPeepholeOpt.cpp | 8 ++++----
.../AArch64/AArch64MachineFunctionInfo.h | 4 ++--
.../Target/AArch64/AArch64PrologueEpilogue.cpp | 12 ++++++------
.../lib/Target/AArch64/AArch64SLSHardening.cpp | 6 +++---
.../AArch64/AArch64SRLTDefineSuperRegs.cpp | 6 +++---
.../AArch64/GISel/AArch64CallLowering.cpp | 4 ++--
.../AArch64/GISel/AArch64GlobalISelUtils.cpp | 2 +-
.../GISel/AArch64InstructionSelector.cpp | 2 +-
llvm/lib/Target/AArch64/MachineSMEABIPass.cpp | 18 +++++++++---------
14 files changed, 56 insertions(+), 56 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 005f69b08a4d3..d9df7cac88541 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -2070,7 +2070,7 @@ Register AArch64AsmPrinter::emitPtrauthDiscriminator(uint64_t Disc,
assert(isUInt<16>(Disc) && "Constant discriminator is too wide");
// So far we've used NoRegister in pseudos. Now we need real encodings.
- if (AddrDisc == AArch64::NoRegister)
+ if (!AddrDisc.isValid())
AddrDisc = AArch64::XZR;
// If there is no constant discriminator, there's no blend involved:
@@ -2294,13 +2294,13 @@ AArch64AsmPrinter::PtrAuthSchema AArch64AsmPrinter::PtrAuthSchema::CreateImmReg(
Schema.IntDisc = IntDisc;
Schema.AddrDisc = AddrDiscOp.getReg();
Schema.AddrDiscIsKilled = AddrDiscOp.isKill();
- Schema.PCDisc = AArch64::NoRegister;
+ Schema.PCDisc = Register();
return Schema;
}
AArch64AsmPrinter::PtrAuthSchema AArch64AsmPrinter::PtrAuthSchema::CreateRegReg(
AArch64PACKey::ID Key, Register AddrDisc, Register PCDisc) {
- assert(PCDisc != AArch64::NoRegister &&
+ assert(PCDisc.isValid() &&
"Use CreateImmReg for non-PC schemas");
PtrAuthSchema Schema;
Schema.Key = Key;
@@ -2413,11 +2413,11 @@ void AArch64AsmPrinter::emitPtrauthAuthResign(
std::optional<PtrAuthSchema> SignSchema, std::optional<int64_t> Addend,
Value *DS) {
const PtrauthCheckMode CheckMode = getCheckMode(MF);
- const bool IsAuthWithPC = AuthSchema.PCDisc != AArch64::NoRegister;
- assert(!SignSchema || SignSchema->PCDisc == AArch64::NoRegister);
+ const bool IsAuthWithPC = AuthSchema.PCDisc.isValid();
+ assert(!SignSchema || !SignSchema->PCDisc.isValid());
Register SignAddrDiscOrNone =
- SignSchema ? SignSchema->AddrDisc : AArch64::NoRegister;
+ SignSchema ? SignSchema->AddrDisc : Register();
// 1. Authenticate Pointer - this is the only common step.
// It is more complex than signing because AUTI[AB]171615 may be used.
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index a54e7344d58f1..e93e42f813ac4 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -949,7 +949,7 @@ AArch64FrameLowering::findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB,
if (LiveRegs.available(MRI, Reg))
return Reg;
}
- return AArch64::NoRegister;
+ return Register();
}
bool AArch64FrameLowering::canUseAsPrologue(
@@ -980,14 +980,14 @@ bool AArch64FrameLowering::canUseAsPrologue(
return false;
if (RegInfo->hasStackRealignment(*MF) || TLI->hasInlineStackProbe(*MF))
- if (findScratchNonCalleeSaveRegister(TmpMBB) == AArch64::NoRegister)
+ if (!findScratchNonCalleeSaveRegister(TmpMBB).isValid())
return false;
// May need a scratch register (for return value) if require making a special
// call
if (requiresSaveVG(*MF) ||
windowsRequiresStackProbe(*MF, std::numeric_limits<uint64_t>::max()))
- if (findScratchNonCalleeSaveRegister(TmpMBB, true) == AArch64::NoRegister)
+ if (!findScratchNonCalleeSaveRegister(TmpMBB, true).isValid())
return false;
return true;
@@ -2047,7 +2047,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
Register X0Scratch;
llvm::scope_exit RestoreX0([&] {
- if (X0Scratch != AArch64::NoRegister)
+ if (X0Scratch.isValid())
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::COPY), AArch64::X0)
.addReg(X0Scratch)
.setMIFlag(MachineInstr::FrameSetup);
@@ -2056,7 +2056,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
if (Reg1 == AArch64::VG) {
// Find an available register to store value of VG to.
Reg1 = findScratchNonCalleeSaveRegister(&MBB, true);
- assert(Reg1 != AArch64::NoRegister);
+ assert(Reg1.isValid());
if (MF.getSubtarget<AArch64Subtarget>().hasSVE()) {
BuildMI(MBB, MI, DL, TII.get(AArch64::CNTD_XPiI), Reg1)
.addImm(31)
@@ -2579,10 +2579,10 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
// PairedReg could be in a different register class from Reg, which would
// lead to a FPR (usually D8) accidentally being marked saved.
if (RegIsGPR64 && !AArch64::GPR64RegClass.contains(PairedReg)) {
- PairedReg = AArch64::NoRegister;
+ PairedReg = Register();
HasUnpairedGPR64 = true;
}
- assert(PairedReg == AArch64::NoRegister ||
+ assert(!PairedReg.isValid() ||
AArch64::GPR64RegClass.contains(Reg, PairedReg) ||
AArch64::FPR64RegClass.contains(Reg, PairedReg) ||
AArch64::FPR128RegClass.contains(Reg, PairedReg));
@@ -2598,7 +2598,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
// MachO's compact unwind format relies on all registers being stored in
// pairs.
// FIXME: the usual format is actually better if unwinding isn't needed.
- if (producePairRegisters(MF) && PairedReg != AArch64::NoRegister &&
+ if (producePairRegisters(MF) && PairedReg.isValid() &&
!SavedRegs.test(PairedReg)) {
SavedRegs.set(PairedReg);
if (AArch64::GPR64RegClass.contains(PairedReg) &&
@@ -2753,7 +2753,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
// Failed to make a pair for compact unwind format, revert spilling.
if (produceCompactUnwindFrame(*this, MF)) {
SavedRegs.reset(UnspilledCSGPR);
- ExtraCSSpill = AArch64::NoRegister;
+ ExtraCSSpill = Register();
}
} else
SavedRegs.set(UnspilledCSGPRPaired);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 70396749e3426..84080486a16cc 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -465,7 +465,7 @@ extractPtrauthBlendDiscriminators(SDValue Disc, SelectionDAG *DAG) {
// If there's no address discriminator, use NoRegister, which we'll later
// replace with XZR, or directly use a Z variant of the inst. when available.
if (!AddrDisc)
- AddrDisc = DAG->getRegister(AArch64::NoRegister, MVT::i64);
+ AddrDisc = DAG->getRegister(Register(), MVT::i64);
return std::make_tuple(
DAG->getTargetConstant(ConstDiscN->getZExtValue(), DL, MVT::i64),
@@ -3588,7 +3588,7 @@ void AArch64TargetLowering::fixupPtrauthDiscriminator(
// Small immediate integer constant passed via VReg.
if (DiscMI->getOperand(1).isImm() &&
isUInt<16>(DiscMI->getOperand(1).getImm())) {
- AddrDisc = AArch64::NoRegister;
+ AddrDisc = Register();
IntDisc = DiscMI->getOperand(1).getImm();
}
break;
@@ -3598,7 +3598,7 @@ void AArch64TargetLowering::fixupPtrauthDiscriminator(
// For uniformity, always use NoRegister, as XZR is not necessarily contained
// in the requested register class.
if (AddrDisc == AArch64::XZR)
- AddrDisc = AArch64::NoRegister;
+ AddrDisc = Register();
// Make sure AddrDisc operand respects the register class imposed by MI.
if (AddrDisc && MRI.getRegClass(AddrDisc) != AddrDiscRC) {
@@ -11532,7 +11532,7 @@ AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
Opcode = AArch64ISD::AUTH_CALL;
Ops.push_back(DAG.getTargetConstant(AArch64PACKey::IA, DL, MVT::i32));
Ops.push_back(DAG.getTargetConstant(0, DL, MVT::i64)); // Integer Disc.
- Ops.push_back(DAG.getRegister(AArch64::NoRegister, MVT::i64)); // Addr Disc.
+ Ops.push_back(DAG.getRegister(Register(), MVT::i64)); // Addr Disc.
}
Ops.push_back(DAG.getRegister(AArch64::X0, MVT::i64));
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index fe0c59622e17b..ebaacf94b2997 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -490,7 +490,7 @@ void AArch64InstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
bool HasBTI = AFI && AFI->branchTargetEnforcement();
if (MBB.getSectionID() == MBBSectionID::ColdSectionID && !HasBTI) {
Register Scavenged = RS->FindUnusedReg(&AArch64::GPR64RegClass);
- if (Scavenged != AArch64::NoRegister) {
+ if (Scavenged.isValid()) {
buildIndirectBranch(Scavenged, NewDestBB);
RS->setRegUsed(Scavenged);
return;
@@ -6593,7 +6593,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
unsigned Opc = 0;
bool Offset = true;
unsigned StackID = TargetStackID::Default;
- Register PNRReg = MCRegister::NoRegister;
+ Register PNRReg;
switch (TRI.getSpillSize(*RC)) {
case 1:
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 289552a8d9411..adb17b51d985e 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -1107,7 +1107,7 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
else
MatchingReg = GetMatchingSubReg(
TRI->getMinimalPhysRegClass(MOP.getReg()));
- assert(MatchingReg != AArch64::NoRegister &&
+ assert(MatchingReg.isValid() &&
"Cannot find matching regs for renaming");
MOP.setReg(MatchingReg);
}
@@ -2654,7 +2654,7 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
bool IsPairedInsn = AArch64InstrInfo::isPairedLdSt(MemMI);
Register DestReg[] = {getLdStRegOp(MemMI, 0).getReg(),
IsPairedInsn ? getLdStRegOp(MemMI, 1).getReg()
- : AArch64::NoRegister};
+ : Register()};
// If the load/store is the first instruction in the block, there's obviously
// not any matching update. Ditto if the memory offset isn't zero.
@@ -2719,10 +2719,10 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
// i.e. the combined instruction is put in the place of the memory
// instruction. Same applies if we see a memory access or side effects.
if (MI.mayLoadOrStore() || MI.hasUnmodeledSideEffects() ||
- (DestReg[0] != AArch64::NoRegister &&
+ (DestReg[0].isValid() &&
!(ModifiedRegUnits.available(DestReg[0]) &&
UsedRegUnits.available(DestReg[0]))) ||
- (DestReg[1] != AArch64::NoRegister &&
+ (DestReg[1].isValid() &&
!(ModifiedRegUnits.available(DestReg[1]) &&
UsedRegUnits.available(DestReg[1]))))
MergeEither = false;
diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index 554d5938cf2cd..9b42f535ae232 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -918,7 +918,7 @@ bool AArch64MIPeepholeOptImpl::visitCopy(MachineInstr &MI) {
if (SrcMI->getOpcode() != AArch64::SBFMXri ||
SrcMI->getOperand(2).getImm() != 0 ||
SrcMI->getOperand(3).getImm() != 31)
- return AArch64::NoRegister;
+ return Register();
return SrcMI->getOperand(1).getReg();
};
// Look for SUBREG_TO_REG(ORRWrr(WZR, COPY(X.sub_32)))
@@ -926,16 +926,16 @@ bool AArch64MIPeepholeOptImpl::visitCopy(MachineInstr &MI) {
if (SrcMI->getOpcode() != AArch64::SUBREG_TO_REG ||
SrcMI->getOperand(2).getImm() != AArch64::sub_32 ||
!MRI->hasOneNonDBGUse(SrcMI->getOperand(1).getReg()))
- return AArch64::NoRegister;
+ return Register();
MachineInstr *Orr = MRI->getUniqueVRegDef(SrcMI->getOperand(1).getReg());
if (!Orr || Orr->getOpcode() != AArch64::ORRWrr ||
Orr->getOperand(1).getReg() != AArch64::WZR ||
!MRI->hasOneNonDBGUse(Orr->getOperand(2).getReg()))
- return AArch64::NoRegister;
+ return Register();
MachineInstr *Cpy = MRI->getUniqueVRegDef(Orr->getOperand(2).getReg());
if (!Cpy || Cpy->getOpcode() != AArch64::COPY ||
Cpy->getOperand(1).getSubReg() != AArch64::sub_32)
- return AArch64::NoRegister;
+ return Register();
DeadInstrs.insert(Orr);
return Cpy->getOperand(1).getReg();
};
diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
index 60a5a978bb09a..dafe83932ea6a 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
@@ -227,7 +227,7 @@ class AArch64FunctionInfo final : public MachineFunctionInfo {
// Holds a register containing pstate.sm. This is set
// on function entry to record the initial pstate of a function.
- Register PStateSMReg = MCRegister::NoRegister;
+ Register PStateSMReg = Register();
// Has the PNReg used to build PTRUE instruction.
// The PTRUE is used for the LD/ST of ZReg pairs in save and restore.
@@ -238,7 +238,7 @@ class AArch64FunctionInfo final : public MachineFunctionInfo {
// Holds the TPIDR2 block if allocated early (for Windows/stack probes
// support).
- Register EarlyAllocSMESaveBuffer = AArch64::NoRegister;
+ Register EarlyAllocSMESaveBuffer = Register();
public:
AArch64FunctionInfo(const Function &F, const AArch64Subtarget *STI);
diff --git a/llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp b/llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
index 230ea947c5e54..ceb7444be805b 100644
--- a/llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
@@ -543,7 +543,7 @@ void AArch64PrologueEmitter::allocateStackSpace(
// have SVE objects, we can use a more efficient sequence for stack probing.
if (AllocSize.getScalable() == 0 && RealignmentPadding == 0) {
Register ScratchReg = AFL.findScratchNonCalleeSaveRegister(&MBB);
- assert(ScratchReg != AArch64::NoRegister);
+ assert(ScratchReg.isValid());
BuildMI(MBB, MBBI, DL, TII->get(AArch64::PROBED_STACKALLOC))
.addDef(ScratchReg)
.addImm(AllocSize.getFixed())
@@ -578,7 +578,7 @@ void AArch64PrologueEmitter::allocateStackSpace(
Register ScratchReg = RealignmentPadding
? AFL.findScratchNonCalleeSaveRegister(&MBB)
: AArch64::SP;
- assert(ScratchReg != AArch64::NoRegister);
+ assert(ScratchReg.isValid());
// SUB Xd, SP, AllocSize
emitFrameOffset(MBB, MBBI, DL, ScratchReg, AArch64::SP, -AllocSize, TII,
MachineInstr::FrameSetup, false, NeedsWinCFI, &HasWinCFI,
@@ -611,7 +611,7 @@ void AArch64PrologueEmitter::allocateStackSpace(
// TODO: As an optimisation, the loop can be "unrolled" into a few parts,
// each of them guaranteed to adjust the stack by less than the probe size.
Register TargetReg = AFL.findScratchNonCalleeSaveRegister(&MBB);
- assert(TargetReg != AArch64::NoRegister);
+ assert(TargetReg.isValid());
// SUB Xd, SP, AllocSize
emitFrameOffset(MBB, MBBI, DL, TargetReg, AArch64::SP, -AllocSize, TII,
MachineInstr::FrameSetup, false, NeedsWinCFI, &HasWinCFI,
@@ -1089,14 +1089,14 @@ void AArch64PrologueEmitter::emitWindowsStackProbe(
// Find an available register to spill the value of X15 to, if X15 is being
// used already for nest.
- unsigned X15Scratch = AArch64::NoRegister;
+ Register X15Scratch;
if (llvm::any_of(MBB.liveins(),
[this](const MachineBasicBlock::RegisterMaskPair &LiveIn) {
return RegInfo.isSuperOrSubRegisterEq(AArch64::X15,
LiveIn.PhysReg);
})) {
X15Scratch = AFL.findScratchNonCalleeSaveRegister(&MBB, /*HasCall=*/true);
- assert(X15Scratch != AArch64::NoRegister &&
+ assert(X15Scratch.isValid() &&
(X15Scratch < AArch64::X15 || X15Scratch > AArch64::X17));
#ifndef NDEBUG
LiveRegs.removeReg(AArch64::X15); // ignore X15 since we restore it
@@ -1241,7 +1241,7 @@ void AArch64PrologueEmitter::emitWindowsStackProbe(
// we've set a frame pointer and already finished the SEH prologue.
assert(!NeedsWinCFI);
}
- if (X15Scratch != AArch64::NoRegister) {
+ if (X15Scratch.isValid()) {
BuildMI(MBB, MBBI, DL, TII->get(AArch64::ORRXrr), AArch64::X15)
.addReg(AArch64::XZR)
.addReg(X15Scratch, RegState::Undef)
diff --git a/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp b/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
index 8bc0a236ac5f2..b1b342bff9ee1 100644
--- a/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
@@ -320,7 +320,7 @@ parseThunkName(StringRef ThunkName) {
// Parse register operands.
Register Xn = ParseRegName(XnStr);
- Register Xm = Kind.HasXmOperand ? ParseRegName(XmStr) : AArch64::NoRegister;
+ Register Xm = Kind.HasXmOperand ? ParseRegName(XmStr) : Register();
return std::make_tuple(std::ref(Kind), Xn, Xm);
}
@@ -368,7 +368,7 @@ void SLSHardeningInserter::populateThunk(MachineFunction &MF) {
.addImm(0);
MachineInstrBuilder Builder =
BuildMI(Entry, DebugLoc(), TII->get(Kind.BROpcode)).addReg(AArch64::X16);
- if (Xm != AArch64::NoRegister) {
+ if (Xm.isValid()) {
Entry->addLiveIn(Xm);
Builder.addReg(Xm);
}
@@ -429,7 +429,7 @@ void SLSHardeningInserter::convertBLRToBL(
"Expected one or two register inputs");
Register Xn = BLR.getOperand(0).getReg();
Register Xm =
- Kind.HasXmOperand ? BLR.getOperand(1).getReg() : AArch64::NoRegister;
+ Kind.HasXmOperand ? BLR.getOperand(1).getReg() : Register();
DebugLoc DL = BLR.getDebugLoc();
diff --git a/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp b/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp
index 8faecc3ab23c7..acc1476252613 100644
--- a/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp
@@ -175,9 +175,9 @@ Register AArch64SRLTDefineSuperRegsImpl::getWidestSuperReg(
return true;
};
- Register LargestSuperReg = AArch64::NoRegister;
+ Register LargestSuperReg;
for (Register SR : TRI->superregs(R))
- if (IsSuitableSuperReg(SR) && (LargestSuperReg == AArch64::NoRegister ||
+ if (IsSuitableSuperReg(SR) && (!LargestSuperReg.isValid() ||
TRI->isSuperRegister(LargestSuperReg, SR)))
LargestSuperReg = SR;
@@ -220,7 +220,7 @@ bool AArch64SRLTDefineSuperRegsImpl::run(MachineFunction &MF) {
for (const MachineOperand &DefOp : MI.defs())
if (Register R = getWidestSuperReg(DefOp.getReg(), RequiredBaseRegUnits,
QHiRegUnits);
- R != AArch64::NoRegister)
+ R.isValid())
SuperRegs.insert(R);
if (!SuperRegs.size())
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 9a6ec51d5f288..0c94fe7ca45f7 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -1188,7 +1188,7 @@ bool AArch64CallLowering::lowerTailCall(
MIB.addImm(IntDisc);
MIB.addUse(AddrDisc);
- if (AddrDisc != AArch64::NoRegister) {
+ if (AddrDisc.isValid()) {
MIB->getOperand(4).setReg(constrainOperandRegClass(
MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
*MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(),
@@ -1463,7 +1463,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
MIB.addImm(IntDisc);
MIB.addUse(AddrDisc);
- if (AddrDisc != AArch64::NoRegister) {
+ if (AddrDisc.isValid()) {
constrainOperandRegClass(MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
*MF.getSubtarget().getRegBankInfo(), *MIB,
MIB->getDesc(), MIB->getOperand(CalleeOpNo + 3),
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
index e5c6f73c89828..acd14d3d7189a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
@@ -112,7 +112,7 @@ AArch64GISelUtils::extractPtrauthBlendDiscriminators(Register Disc,
if (auto ConstDiscVal = getIConstantVRegVal(Disc, MRI)) {
if (isUInt<16>(ConstDiscVal->getZExtValue())) {
ConstDisc = ConstDiscVal->getZExtValue();
- AddrDisc = AArch64::NoRegister;
+ AddrDisc = Register();
}
return std::make_tuple(ConstDisc, AddrDisc);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 0b018dc7b22a8..08c4678e6fb88 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -6764,7 +6764,7 @@ bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
std::tie(PACConstDiscC, PACAddrDisc) =
extractPtrauthBlendDiscriminators(PACDisc, MRI);
- if (PACAddrDisc == AArch64::NoRegister)
+ if (!PACAddrDisc.isValid())
PACAddrDisc = AArch64::XZR;
MIB.buildCopy({AArch64::X17}, {ValReg});
diff --git a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
index 076917d242c79..c9f6b6939a83a 100644
--- a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+++ b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
@@ -121,8 +121,8 @@ enum LiveRegs : uint8_t {
/// Holds the virtual registers live physical registers have been saved to.
struct PhysRegSave {
LiveRegs PhysLiveRegs;
- Register StatusFlags = AArch64::NoRegister;
- Register X0Save = AArch64::NoRegister;
+ Register StatusFlags = Register();
+ Register X0Save = Register();
};
/// Contains the needed ZA state (and live registers) at an instruction. That is
@@ -168,12 +168,12 @@ class EmitContext {
/// Get or create agnostic ZA buffer pointer in \p MF.
Register getAgnosticZABufferPtr(MachineFunction &MF) {
- if (AgnosticZABufferPtr != AArch64::NoRegister)
+ if (AgnosticZABufferPtr.isValid())
return AgnosticZABufferPtr;
Register BufferPtr =
MF.getInfo<AArch64FunctionInfo>()->getEarlyAllocSMESaveBuffer();
AgnosticZABufferPtr =
- BufferPtr != AArch64::NoRegister
+ BufferPtr.isValid()
? BufferPtr
: MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
return AgnosticZABufferPtr;
@@ -192,13 +192,13 @@ class EmitContext {
bool needsSaveBuffer() const {
assert(!(TPIDR2BlockFI && AgnosticZABufferPtr) &&
"Cannot have both a TPIDR2 block and agnostic ZA buffer");
- return TPIDR2BlockFI || AgnosticZABufferPtr != AArch64::NoRegister;
+ return TPIDR2BlockFI || AgnosticZABufferPtr.isValid();
}
private:
std::optional<int> ZT0SaveFI;
std::optional<int> TPIDR2BlockFI;
- Register AgnosticZABufferPtr = AArch64::NoRegister;
+ Register AgnosticZABufferPtr = Register();
};
StringRef getZAStateString(ZAState State) {
@@ -785,13 +785,13 @@ void MachineSMEABI::restorePhyRegSave(const PhysRegSave &RegSave,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
DebugLoc DL) {
- if (RegSave.StatusFlags != AArch64::NoRegister)
+ if (RegSave.StatusFlags.isValid())
BuildMI(MBB, MBBI, DL, TII->get(AArch64::MSR))
.addImm(AArch64SysReg::NZCV)
.addReg(RegSave.StatusFlags)
.addReg(AArch64::NZCV, RegState::ImplicitDefine);
- if (RegSave.X0Save != AArch64::NoRegister)
+ if (RegSave.X0Save.isValid())
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY),
RegSave.PhysLiveRegs & LiveRegs::W0_HI ? AArch64::X0 : AArch64::W0)
.addReg(RegSave.X0Save);
@@ -878,7 +878,7 @@ void MachineSMEABI::emitAllocateLazySaveBuffer(
BuildMI(MBB, MBBI, DL, TII->get(AArch64::RDSVLI_XI), SVL).addImm(1);
// 1. Allocate the lazy save buffer.
- if (Buffer == AArch64::NoRegister) {
+ if (!Buffer.isValid()) {
// TODO: On Windows, we allocate the lazy save buffer in SelectionDAG (so
// Buffer != AArch64::NoRegister). This is done to reuse the existing
// expansions (which can insert stack checks). This works, but it means we
>From a8582a6d754f05ff01a92bf5bf7c6731984f873f Mon Sep 17 00:00:00 2001
From: Jan Rehders <jrehders at baylibre.com>
Date: Tue, 11 Aug 2026 14:51:18 +0200
Subject: [PATCH 2/2] [AArch64] Replace unsigned with Register NFC
---
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index e93e42f813ac4..d253d2aa0f3a1 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -2531,8 +2531,8 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
- unsigned UnspilledCSGPR = AArch64::NoRegister;
- unsigned UnspilledCSGPRPaired = AArch64::NoRegister;
+ Register UnspilledCSGPR;
+ Register UnspilledCSGPRPaired;
MachineFrameInfo &MFI = MF.getFrameInfo();
const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
@@ -2540,7 +2540,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
MCRegister BasePointerReg =
RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister() : MCRegister();
- unsigned ExtraCSSpill = 0;
+ Register ExtraCSSpill;
bool HasUnpairedGPR64 = false;
bool HasPairZReg = false;
BitVector UserReservedRegs = RegInfo->getUserReservedRegs(MF);
@@ -2739,7 +2739,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
// above to keep the number of spills even, we don't need to do anything else
// here.
if (BigStack) {
- if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) {
+ if (!ExtraCSSpill.isValid() && UnspilledCSGPR.isValid()) {
LLVM_DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)
<< " to get a scratch register.\n");
SavedRegs.set(UnspilledCSGPR);
@@ -2749,7 +2749,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
// pairs, so if we need to spill one extra for BigStack, then we need to
// store the pair.
if (producePairRegisters(MF)) {
- if (UnspilledCSGPRPaired == AArch64::NoRegister) {
+ if (!UnspilledCSGPRPaired.isValid()) {
// Failed to make a pair for compact unwind format, revert spilling.
if (produceCompactUnwindFrame(*this, MF)) {
SavedRegs.reset(UnspilledCSGPR);
@@ -2762,7 +2762,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
// If we didn't find an extra callee-saved register to spill, create
// an emergency spill slot.
- if (!ExtraCSSpill || MF.getRegInfo().isPhysRegUsed(ExtraCSSpill)) {
+ if (!ExtraCSSpill.isValid() || MF.getRegInfo().isPhysRegUsed(ExtraCSSpill)) {
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
const TargetRegisterClass &RC = AArch64::GPR64RegClass;
unsigned Size = TRI->getSpillSize(RC);
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