[llvm] b0a9909 - [VPlan] Expand AddRecs in Plan's entry (#209921)
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Tue Sep 1 02:57:39 PDT 2026
Author: Ramkumar Ramachandra
Date: 2026-09-01T09:57:34Z
New Revision: b0a99098b78dca2933ad1cc90a3eb8484ba7910f
URL: https://github.com/llvm/llvm-project/commit/b0a99098b78dca2933ad1cc90a3eb8484ba7910f
DIFF: https://github.com/llvm/llvm-project/commit/b0a99098b78dca2933ad1cc90a3eb8484ba7910f.diff
LOG: [VPlan] Expand AddRecs in Plan's entry (#209921)
Extend VPSCEVExpander to expand AddRecs in the Plan's entry. In the
general case, an AddRec's loop header refers to a BasicBlock that is no
longer in the Plan, and we have to fall back to the IR SCEV expander.
However, when the Plan's entry has a canonical IV that we can re-use as
a VPIRPhi, expand the AddRec to VPInstructions.
Added:
Modified:
llvm/lib/Transforms/Vectorize/VPlan.h
llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
index 7d2c2fa1bdd23..630f6036ea535 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -1806,7 +1806,7 @@ struct LLVM_ABI_FOR_TEST VPIRPhi : public VPIRInstruction,
return R && classof(R);
}
- PHINode &getIRPhi() { return cast<PHINode>(getInstruction()); }
+ PHINode &getIRPhi() const { return cast<PHINode>(getInstruction()); }
void execute(VPTransformState &State) override;
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index f9550ebaf15a8..880c3a1f57e68 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -1060,13 +1060,40 @@ VPValue *VPSCEVExpander::expand(const SCEV *S) {
return Result;
}
case scAddRecExpr: {
+ auto *AR = cast<SCEVAddRecExpr>(S);
+ VPlan &Plan = Builder.getPlan();
[[maybe_unused]] BasicBlock *PH =
- cast<VPIRBasicBlock>(Builder.getPlan().getEntry())->getIRBasicBlock();
- assert(
- SE.DT.dominates(cast<SCEVAddRecExpr>(S)->getLoop()->getHeader(), PH) &&
- "can only expand AddRecs for loops outside VPlan's scope");
- // AddRecs outside VPlan's scope must be expanded via VPExpandSCEV.
- return vputils::getOrCreateVPValueForSCEVExpr(Builder.getPlan(), S);
+ cast<VPIRBasicBlock>(Plan.getEntry())->getIRBasicBlock();
+ assert(SE.DT.dominates(AR->getLoop()->getHeader(), PH) &&
+ "can only expand AddRecs for loops outside VPlan's scope");
+
+ // Try to expand AR by re-using an existing canonical IV in the Plan's
+ // entry. A canonical IV must be affine and integer typed.
+ if (!AR->isAffine() || !AR->getType()->isIntegerTy())
+ return vputils::getOrCreateVPValueForSCEVExpr(Plan, AR);
+ auto FoundCanIV =
+ find_if(Plan.getEntry()->phis(), [&](const VPRecipeBase &R) {
+ if (!SE.isSCEVable(cast<VPIRPhi>(R).getIRPhi().getType()))
+ return false;
+ const SCEV *Candidate = SE.getSCEV(&cast<VPIRPhi>(R).getIRPhi());
+ return match(Candidate,
+ m_scev_AffineAddRec(m_scev_Zero(), m_scev_One(),
+ m_SpecificLoop(AR->getLoop()))) &&
+ Candidate->getType() == AR->getType();
+ });
+ if (FoundCanIV == Plan.getEntry()->phis().end())
+ return vputils::getOrCreateVPValueForSCEVExpr(Plan, AR);
+
+ // {Start, +, Step} --> Start + IV * Step, since the AddRec is affine.
+ // Compute Offset = IV * Step.
+ VPValue *Start = expand(AR->getStart());
+ Value *CanonicalIV = &cast<VPIRPhi>(FoundCanIV)->getIRPhi();
+ VPValue *Offset = expand(
+ SE.getMulExpr(SE.getUnknown(CanonicalIV), AR->getStepRecurrence(SE)));
+
+ // Compute Start + Offset with nuw from the AddRec.
+ return Builder.createAdd(Start, Offset, DL, "",
+ {AR->hasNoUnsignedWrap(), false});
}
case scCouldNotCompute:
llvm_unreachable("Attempt to expand a SCEVCouldNotCompute");
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
index be441dbbd2820..5b4369e0db7d9 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
@@ -323,10 +323,10 @@ define void @scev_addrec_expanded(ptr %dst) {
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<outer>:
; CHECK-NEXT: IR %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
-; CHECK-NEXT: IR %0 = add i64 %outer.iv, 4
-; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = udiv ir<%0>, ir<3>
-; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = add nuw nsw vp<[[VP2]]>, ir<1>
-; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP3]]>, ir<4>
+; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = add nuw ir<4>, ir<%outer.iv>
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = udiv vp<[[VP2]]>, ir<3>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = add nuw nsw vp<[[VP3]]>, ir<1>
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP4]]>, ir<4>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
;
@@ -526,13 +526,13 @@ define void @addrec_nuw_flags(ptr %dst) {
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<outer>:
; CHECK-NEXT: IR %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
-; CHECK-NEXT: IR %0 = shl nuw nsw i64 %outer.iv, 2
-; CHECK-NEXT: IR %1 = add i64 %0, 4
; CHECK-NEXT: IR %m = mul nuw i64 %outer.iv, 4
; CHECK-NEXT: IR %bound = add nuw i64 %m, 5
-; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = udiv ir<%1>, ir<3>
-; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = add nuw nsw vp<[[VP2]]>, ir<1>
-; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP3]]>, ir<4>
+; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = shl nuw nsw ir<%outer.iv>, ir<2>
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = add nuw ir<4>, vp<[[VP2]]>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = udiv vp<[[VP3]]>, ir<3>
+; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = add nuw nsw vp<[[VP4]]>, ir<1>
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP5]]>, ir<4>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
;
@@ -684,6 +684,47 @@ exit:
ret void
}
+define void @addrec_nonscevable(ptr %dst) {
+; CHECK-LABEL: VPlan for loop in 'addrec_nonscevable'
+; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<outer>:
+; CHECK-NEXT: IR %fp.phi = phi float [ 0.000000e+00, %entry ], [ %fp.next, %outer.latch ]
+; CHECK-NEXT: IR %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
+; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = add nuw ir<4>, ir<%outer.iv>
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = udiv vp<[[VP2]]>, ir<3>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = add nuw nsw vp<[[VP3]]>, ir<1>
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP4]]>, ir<4>
+; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
+; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
+;
+entry:
+ br label %outer
+
+outer:
+ %fp.phi = phi float [ 0.0, %entry ], [ %fp.next, %outer.latch ]
+ %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
+ br label %inner
+
+inner:
+ %iv = phi i64 [ 0, %outer ], [ %iv.next, %inner ]
+ %gep = getelementptr i8, ptr %dst, i64 %iv
+ store float %fp.phi, ptr %gep
+ %iv.next = add nuw i64 %iv, 3
+ %bound = add i64 %outer.iv, 5
+ %ec.inner = icmp ult i64 %iv.next, %bound
+ br i1 %ec.inner, label %inner, label %outer.latch
+
+outer.latch:
+ %fp.next = fadd float %fp.phi, 1.0
+ %outer.iv.next = add nuw i64 %outer.iv, 1
+ %ec.outer = icmp ult i64 %outer.iv.next, 100
+ br i1 %ec.outer, label %outer, label %exit
+
+exit:
+ ret void
+}
+
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.scalable.enable"}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
diff --git a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
index dbcd4f90fcc52..34b940bee6a1e 100644
--- a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
+++ b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
@@ -323,9 +323,8 @@ define void @test_expand_secv_in_entry_before_gep(ptr %dst) {
; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
; CHECK: [[OUTER_HEADER]]:
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[OUTER_IV_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[OUTER_IV]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 112
; CHECK-NEXT: [[GEP_M:%.*]] = getelementptr [36 x [36 x double]], ptr [[DST]], i64 0, i64 [[OUTER_IV]]
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 112, [[OUTER_IV]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-checks-
diff erence.ll b/llvm/test/Transforms/LoopVectorize/runtime-checks-
diff erence.ll
index 8bda68f620e21..e816b559bffe6 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-checks-
diff erence.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-checks-
diff erence.ll
@@ -526,13 +526,12 @@ define void @nested_loop_bound_needs_constant_correction(ptr %a, ptr %b, i64 %n)
; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
; CHECK: [[OUTER_HEADER]]:
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = mul nsw i64 [[OUTER_IV]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[N]], [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = shl i64 [[OUTER_IV]], 2
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[OUTER_IV]], 3
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP5]], 4
; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP6]]
+; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[N]], [[OUTER_IV]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], [[SCALAR_PH:label %.*]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK: [[VECTOR_MEMCHECK]]:
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