[llvm] [AArch64][GlobalISel] Regenerate knownbits tests. NFC (PR #220200)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 1 02:17:21 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
Mostly just adding IsKnownNeverZero. knownbits-srem.mir now has auto generated check lines.
---
Patch is 339.21 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/220200.diff
38 Files Affected:
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abds.mir (+21-21)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abdu.mir (+24-24)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abs.mir (+19-19)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-add.mir (+80-80)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ashr.mir (+29-29)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-assertzext.mir (+14-14)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-buildvector.mir (+20-20)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-concat.mir (+18-18)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir (+3-3)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ctls.mir (+49-49)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-cttz.mir (+22-22)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-extract-vector.mir (+37-37)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-fcmeq.mir (+9-9)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-fshl-fshr.mir (+95-95)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-vector.mir (+33-33)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-maxdepth.mir (+30-28)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-rotl-rotr.mir (+97-97)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir (+101-101)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir (+55-55)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sat.mir (+42-42)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir (+17-17)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir (+71-71)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shuffle.mir (+19-19)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-smulh.mir (+40-40)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-srem.mir (+37-54)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-stepvector.mir (+12-12)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sub.mir (+79-79)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sve-splat.mir (+7-7)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-trunk.mir (+14-14)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir (+101-101)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir (+55-55)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir (+28-28)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-umulh.mir (+40-40)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-unmerge.mir (+50-50)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vashr.mir (+11-11)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir (+463-463)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-zext.mir (+14-14)
``````````diff
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abds.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abds.mir
index f5e57d668ffd6..955f586bd8e60 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abds.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abds.mir
@@ -6,9 +6,9 @@ name: Cst
body: |
bb.0:
; CHECK-LABEL: name: @Cst
- ; CHECK-NEXT: %0:_ KnownBits:00001010 SignBits:4
- ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
- ; CHECK-NEXT: %2:_ KnownBits:00000111 SignBits:5
+ ; CHECK-NEXT: %0:_ KnownBits:00001010 SignBits:4 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:00000111 SignBits:5 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 10
%1:_(i8) = G_CONSTANT i8 3
%2:_(i8) = G_ABDS %0, %1
@@ -18,11 +18,11 @@ name: PartialKnown
body: |
bb.0:
; CHECK-LABEL: name: @PartialKnown
- ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4
- ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4
- ; CHECK-NEXT: %3:_ KnownBits:00000100 SignBits:5
- ; CHECK-NEXT: %4:_ KnownBits:0000???? SignBits:4
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4 IsKnownNeverZero:0
+ ; CHECK-NEXT: %3:_ KnownBits:00000100 SignBits:5 IsKnownNeverZero:1
+ ; CHECK-NEXT: %4:_ KnownBits:0000???? SignBits:4 IsKnownNeverZero:0
%0:_(i8) = G_IMPLICIT_DEF
%1:_(i8) = G_CONSTANT i8 15
%2:_(i8) = G_AND %0, %1
@@ -35,11 +35,11 @@ name: SignBits
body: |
bb.0:
; CHECK-LABEL: name: @SignBits
- ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1
- ; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:25
- ; CHECK-NEXT: %3:_ KnownBits:???????????????????????????????? SignBits:25
- ; CHECK-NEXT: %4:_ KnownBits:000000000000000000000000???????? SignBits:24
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:25 IsKnownNeverZero:0
+ ; CHECK-NEXT: %3:_ KnownBits:???????????????????????????????? SignBits:25 IsKnownNeverZero:0
+ ; CHECK-NEXT: %4:_ KnownBits:000000000000000000000000???????? SignBits:24 IsKnownNeverZero:0
%0:_(i32) = COPY $w0
%1:_(i32) = COPY $w1
%2:_(i32) = G_SEXT_INREG %0, 8
@@ -51,11 +51,11 @@ name: SignBitsAsymmetric
body: |
bb.0:
; CHECK-LABEL: name: @SignBitsAsymmetric
- ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1
- ; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:25
- ; CHECK-NEXT: %3:_ KnownBits:???????????????????????????????? SignBits:17
- ; CHECK-NEXT: %4:_ KnownBits:0000000000000000???????????????? SignBits:16
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:25 IsKnownNeverZero:0
+ ; CHECK-NEXT: %3:_ KnownBits:???????????????????????????????? SignBits:17 IsKnownNeverZero:0
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000000000???????????????? SignBits:16 IsKnownNeverZero:0
%0:_(i32) = COPY $w0
%1:_(i32) = COPY $w1
%2:_(i32) = G_SEXT_INREG %0, 8
@@ -67,9 +67,9 @@ name: Unknown
body: |
bb.0:
; CHECK-LABEL: name: @Unknown
- ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
%0:_(i8) = COPY $b0
%1:_(i8) = COPY $b1
%2:_(i8) = G_ABDS %0, %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abdu.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abdu.mir
index 864b4986b0498..750321932bf9f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abdu.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abdu.mir
@@ -6,9 +6,9 @@ name: Cst
body: |
bb.0:
; CHECK-LABEL: name: @Cst
- ; CHECK-NEXT: %0:_ KnownBits:00000101 SignBits:5
- ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
- ; CHECK-NEXT: %2:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %0:_ KnownBits:00000101 SignBits:5 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:00000010 SignBits:6 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 5
%1:_(i8) = G_CONSTANT i8 3
%2:_(i8) = G_ABDU %0, %1
@@ -18,9 +18,9 @@ name: CstZero
body: |
bb.0:
; CHECK-LABEL: name: @CstZero
- ; CHECK-NEXT: %0:_ KnownBits:11111111 SignBits:8
- ; CHECK-NEXT: %1:_ KnownBits:00000000 SignBits:8
- ; CHECK-NEXT: %2:_ KnownBits:11111111 SignBits:8
+ ; CHECK-NEXT: %0:_ KnownBits:11111111 SignBits:8 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000000 SignBits:8 IsKnownNeverZero:0
+ ; CHECK-NEXT: %2:_ KnownBits:11111111 SignBits:8 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 255
%1:_(i8) = G_CONSTANT i8 0
%2:_(i8) = G_ABDU %0, %1
@@ -30,9 +30,9 @@ name: ScalarZero
body: |
bb.0:
; CHECK-LABEL: name: @ScalarZero
- ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:00000000 SignBits:8
- ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:00000000 SignBits:8 IsKnownNeverZero:0
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
%0:_(i8) = COPY $b0
%1:_(i8) = G_CONSTANT i8 0
%2:_(i8) = G_ABDU %0, %1
@@ -43,11 +43,11 @@ body: |
bb.0:
; CHECK-LABEL: name: @PartialKnown
- ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4
- ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4
- ; CHECK-NEXT: %3:_ KnownBits:00000100 SignBits:5
- ; CHECK-NEXT: %4:_ KnownBits:0000???? SignBits:4
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4 IsKnownNeverZero:0
+ ; CHECK-NEXT: %3:_ KnownBits:00000100 SignBits:5 IsKnownNeverZero:1
+ ; CHECK-NEXT: %4:_ KnownBits:0000???? SignBits:4 IsKnownNeverZero:0
%0:_(i8) = G_IMPLICIT_DEF
%1:_(i8) = G_CONSTANT i8 15
%2:_(i8) = G_AND %0, %1
@@ -59,11 +59,11 @@ name: NoSignBitsPath
body: |
bb.0:
; CHECK-LABEL: name: @NoSignBitsPath
- ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1
- ; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:25
- ; CHECK-NEXT: %3:_ KnownBits:???????????????????????????????? SignBits:25
- ; CHECK-NEXT: %4:_ KnownBits:???????????????????????????????? SignBits:1
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:25 IsKnownNeverZero:0
+ ; CHECK-NEXT: %3:_ KnownBits:???????????????????????????????? SignBits:25 IsKnownNeverZero:0
+ ; CHECK-NEXT: %4:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
%0:_(i32) = COPY $w0
%1:_(i32) = COPY $w1
%2:_(i32) = G_SEXT_INREG %0, 8
@@ -75,11 +75,11 @@ name: VecCst
body: |
bb.0:
; CHECK-LABEL: name: @VecCst
- ; CHECK-NEXT: %0:_ KnownBits:00000101 SignBits:5
- ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
- ; CHECK-NEXT: %2:_ KnownBits:00000??1 SignBits:5
- ; CHECK-NEXT: %3:_ KnownBits:00000??1 SignBits:5
- ; CHECK-NEXT: %4:_ KnownBits:00000??0 SignBits:5
+ ; CHECK-NEXT: %0:_ KnownBits:00000101 SignBits:5 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:00000??1 SignBits:5 IsKnownNeverZero:1
+ ; CHECK-NEXT: %3:_ KnownBits:00000??1 SignBits:5 IsKnownNeverZero:1
+ ; CHECK-NEXT: %4:_ KnownBits:00000??0 SignBits:5 IsKnownNeverZero:0
%0:_(i8) = G_CONSTANT i8 5
%1:_(i8) = G_CONSTANT i8 3
%2:_(<2 x i8>) = G_BUILD_VECTOR %0, %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abs.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abs.mir
index 42937b62be963..1797c8d812522 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abs.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abs.mir
@@ -6,8 +6,8 @@ name: Cst
body: |
bb.0:
; CHECK-LABEL: name: @Cst
- ; CHECK-NEXT: %0:_ KnownBits:00010011 SignBits:3
- ; CHECK-NEXT: %1:_ KnownBits:00010011 SignBits:3
+ ; CHECK-NEXT: %0:_ KnownBits:00010011 SignBits:3 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:00010011 SignBits:3 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 19
%1:_(i8) = G_ABS %0
...
@@ -16,8 +16,8 @@ name: CstNeg
body: |
bb.0:
; CHECK-LABEL: name: @CstNeg
- ; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3
- ; CHECK-NEXT: %1:_ KnownBits:00010010 SignBits:3
+ ; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:00010010 SignBits:3 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 238
%1:_(i8) = G_ABS %0
...
@@ -26,9 +26,9 @@ name: SplatVecCst
body: |
bb.0:
; CHECK-LABEL: name: @SplatVecCst
- ; CHECK-NEXT: %0:_ KnownBits:11111010 SignBits:5
- ; CHECK-NEXT: %1:_ KnownBits:11111010 SignBits:5
- ; CHECK-NEXT: %2:_ KnownBits:00000110 SignBits:5
+ ; CHECK-NEXT: %0:_ KnownBits:11111010 SignBits:5 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:11111010 SignBits:5 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:00000110 SignBits:5 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 250
%1:_(<vscale x 16 x i8>) = G_SPLAT_VECTOR %0(i8)
%2:_(<vscale x 16 x i8>) = G_ABS %1
@@ -38,10 +38,10 @@ name: VecCst
body: |
bb.0:
; CHECK-LABEL: name: @VecCst
- ; CHECK-NEXT: %0:_ KnownBits:00011001 SignBits:3
- ; CHECK-NEXT: %1:_ KnownBits:11100001 SignBits:3
- ; CHECK-NEXT: %2:_ KnownBits:?????001 SignBits:3
- ; CHECK-NEXT: %3:_ KnownBits:00?????1 SignBits:2
+ ; CHECK-NEXT: %0:_ KnownBits:00011001 SignBits:3 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:11100001 SignBits:3 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:?????001 SignBits:3 IsKnownNeverZero:1
+ ; CHECK-NEXT: %3:_ KnownBits:00?????1 SignBits:2 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 25
%1:_(i8) = G_CONSTANT i8 225
%2:_(<2 x i8>) = G_BUILD_VECTOR %0:_(i8), %1:_(i8)
@@ -52,8 +52,8 @@ name: ImplicitDef
body: |
bb.0:
; CHECK-LABEL: name: @ImplicitDef
- ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
%0:_(i8) = G_IMPLICIT_DEF
%1:_(i8) = G_ABS %0
...
@@ -62,9 +62,9 @@ name: CstSext
body: |
bb.0:
; CHECK-LABEL: name: @CstSext
- ; CHECK-NEXT: %0:_ KnownBits:11000111 SignBits:2
- ; CHECK-NEXT: %1:_ KnownBits:1111111111000111 SignBits:10
- ; CHECK-NEXT: %2:_ KnownBits:0000000000111001 SignBits:10
+ ; CHECK-NEXT: %0:_ KnownBits:11000111 SignBits:2 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:1111111111000111 SignBits:10 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000111001 SignBits:10 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 199
%1:_(i16) = G_SEXT %0
%2:_(i16) = G_ABS %1
@@ -74,9 +74,9 @@ name: ImplicitDefSext
body: |
bb.0:
; CHECK-LABEL: name: @ImplicitDefSext
- ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
- ; CHECK-NEXT: %2:_ KnownBits:00000000???????? SignBits:8
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9 IsKnownNeverZero:0
+ ; CHECK-NEXT: %2:_ KnownBits:00000000???????? SignBits:8 IsKnownNeverZero:0
%0:_(i8) = G_IMPLICIT_DEF
%1:_(i16) = G_SEXT %0
%2:_(i16) = G_ABS %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-add.mir
index ca67dbbd701cd..a751e7c0b96ba 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-add.mir
@@ -6,9 +6,9 @@ name: Cst
body: |
bb.1:
; CHECK-LABEL: name: @Cst
- ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
- ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
- ; CHECK-NEXT: %2:_ KnownBits:00011010 SignBits:3
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:00011010 SignBits:3 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 2
%1:_(i8) = G_CONSTANT i8 24
%2:_(i8) = G_ADD %0, %1
@@ -18,9 +18,9 @@ name: CstZero
body: |
bb.1:
; CHECK-LABEL: name: @CstZero
- ; CHECK-NEXT: %0:_ KnownBits:00000001 SignBits:7
- ; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8
- ; CHECK-NEXT: %2:_ KnownBits:00000000 SignBits:8
+ ; CHECK-NEXT: %0:_ KnownBits:00000001 SignBits:7 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:00000000 SignBits:8 IsKnownNeverZero:0
%0:_(i8) = G_CONSTANT i8 1
%1:_(i8) = G_CONSTANT i8 255
%2:_(i8) = G_ADD %0, %1
@@ -30,9 +30,9 @@ name: CstNegOne
body: |
bb.1:
; CHECK-LABEL: name: @CstNegOne
- ; CHECK-NEXT: %0:_ KnownBits:00000000 SignBits:8
- ; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8
- ; CHECK-NEXT: %2:_ KnownBits:11111111 SignBits:8
+ ; CHECK-NEXT: %0:_ KnownBits:00000000 SignBits:8 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:11111111 SignBits:8 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 0
%1:_(i8) = G_CONSTANT i8 255
%2:_(i8) = G_ADD %0, %1
@@ -42,9 +42,9 @@ name: CstSeven
body: |
bb.1:
; CHECK-LABEL: name: @CstSeven
- ; CHECK-NEXT: %0:_ KnownBits:00001000 SignBits:4
- ; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8
- ; CHECK-NEXT: %2:_ KnownBits:00000111 SignBits:5
+ ; CHECK-NEXT: %0:_ KnownBits:00001000 SignBits:4 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:00000111 SignBits:5 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 8
%1:_(i8) = G_CONSTANT i8 255
%2:_(i8) = G_ADD %0, %1
@@ -54,9 +54,9 @@ name: CstNeg
body: |
bb.1:
; CHECK-LABEL: name: @CstNeg
- ; CHECK-NEXT: %0:_ KnownBits:11100000 SignBits:3
- ; CHECK-NEXT: %1:_ KnownBits:00000010 SignBits:6
- ; CHECK-NEXT: %2:_ KnownBits:11100010 SignBits:3
+ ; CHECK-NEXT: %0:_ KnownBits:11100000 SignBits:3 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000010 SignBits:6 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:11100010 SignBits:3 IsKnownNeverZero:1
%0:_(i8) = G_CONSTANT i8 224
%1:_(i8) = G_CONSTANT i8 2
%2:_(i8) = G_ADD %0, %1
@@ -66,9 +66,9 @@ name: ScalarVar
body: |
bb.1:
; CHECK-LABEL: name: @ScalarVar
- ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
%0:_(i8) = COPY $b0
%1:_(i8) = COPY $b1
%2:_(i8) = G_ADD %0, %1
@@ -78,9 +78,9 @@ name: ScalarRhsEarlyOut
body: |
bb.1:
; CHECK-LABEL: name: @ScalarRhsEarlyOut
- ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
- ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
%0:_(i8) = COPY $b0
%1:_(i8) = G_CONSTANT i8 3
%2:_(i8) = G_ADD %0, %1
@@ -90,11 +90,11 @@ name: ScalarNonNegative
body: |
bb.1:
; CHECK-LABEL: name: @ScalarNonNegative
- ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4
- ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4
- ; CHECK-NEXT: %3:_ KnownBits:11111111 SignBits:8
- ; CHECK-NEXT: %4:_ KnownBits:???????? SignBits:4
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4 IsKnownNeverZero:0
+ ; CHECK-NEXT: %3:_ KnownBits:11111111 SignBits:8 IsKnownNeverZero:1
+ ; CHECK-NEXT: %4:_ KnownBits:???????? SignBits:4 IsKnownNeverZero:0
%0:_(i8) = COPY $b0
%1:_(i8) = G_CONSTANT i8 15
%2:_(i8) = G_AND %0, %1
@@ -106,9 +106,9 @@ name: ScalarLhsEarlyOut
body: |
bb.1:
; CHECK-LABEL: name: @ScalarLhsEarlyOut
- ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
- ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
%0:_(i8) = COPY $b0
%1:_(i8) = G_CONSTANT i8 3
%2:_(i8) = G_ADD %1, %0
@@ -118,11 +118,11 @@ name: ScalarPartKnown
body: |
bb.1:
; CHECK-LABEL: name: @ScalarPartKnown
- ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4
- ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4
- ; CHECK-NEXT: %3:_ KnownBits:00000101 SignBits:5
- ; CHECK-NEXT: %4:_ KnownBits:000????? SignBits:3
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4 IsKnownNeverZero:0
+ ; CHECK-NEXT: %3:_ KnownBits:00000101 SignBits:5 IsKnownNeverZero:1
+ ; CHECK-NEXT: %4:_ KnownBits:000????? SignBits:3 IsKnownNeverZero:0
%0:_(i8) = COPY $b0
%1:_(i8) = G_CONSTANT i8 15
%2:_(i8) = G_AND %0, %1
@@ -134,11 +134,11 @@ name: VectorCstZero
body: |
bb.1:
; CHECK-LABEL: name: @VectorCstZero
- ; CHECK-NEXT: %0:_ KnownBits:0000000000000001 SignBits:15
- ; CHECK-NEXT: %1:_ KnownBits:1111111111111111 SignBits:16
- ; CHECK-NEXT: %2:_ KnownBits:0000000000000001 SignBits:15
- ; CHECK-NEXT: %3:_ KnownBits:1111111111111111 SignBits:16
- ; CHECK-NEXT: %4:_ KnownBits:0000000000000000 SignBits:16
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000001 SignBits:15 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:1111111111111111 SignBits:16 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000001 SignBits:15 IsKnownNeverZero:1
+ ; CHECK-NEXT: %3:_ KnownBits:1111111111111111 SignBits:16 IsKnownNeverZero:1
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000000000 SignBits:16 IsKnownNeverZero:0
%0:_(i16) = G_CONSTANT i16 1
%1:_(i16) = G_CONSTANT i16 65535
%2:_(<4 x i16>) = G_BUILD_VECTOR %0, %0, %0, %0
@@ -150,11 +150,11 @@ name: VectorCstNegOne
body: |
bb.1:
; CHECK-LABEL: name: @VectorCstNegOne
- ; CHECK-NEXT: %0:_ KnownBits:0000000000000000 SignBits:16
- ; CHECK-NEXT: %1:_ KnownBits:1111111111111111 SignBits:16
- ; CHECK-NEXT: %2:_ KnownBits:00000000000000...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/220200
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