[llvm] RISCV: Pass instruction and operand index to vectorPseudoHasAllNBitUsers (PR #219993)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Matt Arsenault (arsenm)

<details>
<summary>Changes</summary>

Take the user instruction and operand index directly instead of a
MachineOperand, so the helper no longer relies on getParent.

Co-authored-by: Claude (Claude-Opus-4.8)

---
Full diff: https://github.com/llvm/llvm-project/pull/219993.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp (+3-4) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 08d72f28b9e0b..45e119a1c03d5 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -98,9 +98,8 @@ FunctionPass *llvm::createRISCVOptWInstrsLegacyPass() {
   return new RISCVOptWInstrsLegacy();
 }
 
-static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp,
+static bool vectorPseudoHasAllNBitUsers(const MachineInstr &MI, unsigned OpIdx,
                                         unsigned Bits) {
-  const MachineInstr &MI = *UserOp.getParent();
   unsigned MCOpcode = RISCV::getRVVMCOpcode(MI.getOpcode());
 
   if (!MCOpcode)
@@ -113,7 +112,7 @@ static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp,
   assert(RISCVII::hasVLOp(TSFlags));
   const unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MCID)).getImm();
 
-  if (UserOp.getOperandNo() == RISCVII::getVLOpNum(MCID))
+  if (OpIdx == RISCVII::getVLOpNum(MCID))
     return false;
 
   auto NumDemandedBits =
@@ -155,7 +154,7 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
 
       switch (UserMI->getOpcode()) {
       default:
-        if (vectorPseudoHasAllNBitUsers(UserOp, Bits))
+        if (vectorPseudoHasAllNBitUsers(*UserMI, OpIdx, Bits))
           break;
         return false;
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/219993