[llvm] c600ef3 - [SLP][NFC]Add a test with non-best vectorization of copyables, extended with identity value, NFC
via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 31 07:43:42 PDT 2026
Author: Alexey Bataev
Date: 2026-08-31T10:43:36-04:00
New Revision: c600ef3e1cbf5358fc5bb7e4d16e6ebb9f7963d1
URL: https://github.com/llvm/llvm-project/commit/c600ef3e1cbf5358fc5bb7e4d16e6ebb9f7963d1
DIFF: https://github.com/llvm/llvm-project/commit/c600ef3e1cbf5358fc5bb7e4d16e6ebb9f7963d1.diff
LOG: [SLP][NFC]Add a test with non-best vectorization of copyables, extended with identity value, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/219986
Added:
llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll b/llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
new file mode 100644
index 0000000000000..80e7bdc4ea4e6
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
@@ -0,0 +1,282 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s
+
+; The store chain mixes and(x, sub(0, x)) lanes with bare power-of-two shl
+; lanes (and a constant lane). The copyable shl lanes are modeled as
+; and(V, -V)/sub(0, V), keeping the shl operand column a single full-width
+; node fed by a contiguous load and the sub operand column a plain negation
+; of it.
+
+define void @and_neg_pow2_copyable_16(ptr %out, ptr %y) {
+; CHECK-LABEL: define void @and_neg_pow2_copyable_16(
+; CHECK-SAME: ptr [[OUT:%.*]], ptr [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 4
+; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 12
+; CHECK-NEXT: [[P10:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 24
+; CHECK-NEXT: [[P9:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 36
+; CHECK-NEXT: [[Y9:%.*]] = load i32, ptr [[P9]], align 4
+; CHECK-NEXT: [[P11:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 40
+; CHECK-NEXT: [[P4:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 48
+; CHECK-NEXT: [[TMP0:%.*]] = call <3 x i32> @llvm.masked.load.v3i32.p0(ptr align 4 [[P3]], <3 x i1> <i1 true, i1 false, i1 true>, <3 x i32> poison)
+; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i32>, ptr [[P10]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0(ptr align 4 [[P1]], <8 x i1> <i1 true, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>, <8 x i32> poison)
+; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 3, i32 7>
+; CHECK-NEXT: [[TMP4:%.*]] = shl <4 x i32> <i32 1, i32 4, i32 16, i32 64>, [[TMP3]]
+; CHECK-NEXT: [[TMP16:%.*]] = load <2 x i32>, ptr [[P11]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P4]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <3 x i32> [[TMP0]], <3 x i32> poison, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 0, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <16 x i32> [[TMP7]], <16 x i32> <i32 0, i32 0, i32 0, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 5, i32 poison, i32 poison, i32 24, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i32> [[TMP8]], i32 [[Y9]], i64 9
+; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <16 x i32> [[TMP9]], <16 x i32> [[TMP6]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
+; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <16 x i32> [[TMP18]], <16 x i32> [[TMP21]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <2 x i32> [[TMP16]], <2 x i32> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <16 x i32> [[TMP19]], <16 x i32> [[TMP20]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 16, i32 17, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP10:%.*]] = shl <16 x i32> <i32 0, i32 -1, i32 -1, i32 9, i32 -1, i32 25, i32 36, i32 49, i32 -1, i32 81, i32 100, i32 121, i32 144, i32 169, i32 196, i32 225>, [[TMP15]]
+; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <16 x i32> [[TMP17]], <16 x i32> <i32 -1, i32 poison, i32 poison, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <16 x i32> <i32 16, i32 0, i32 1, i32 19, i32 2, i32 21, i32 22, i32 23, i32 3, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <16 x i32> [[TMP10]], <16 x i32> <i32 0, i32 0, i32 0, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP11:%.*]] = sub nsw <16 x i32> [[TMP13]], [[TMP14]]
+; CHECK-NEXT: [[TMP12:%.*]] = and <16 x i32> [[TMP10]], [[TMP11]]
+; CHECK-NEXT: store <16 x i32> [[TMP12]], ptr [[OUT]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %p1 = getelementptr inbounds nuw i8, ptr %y, i64 4
+ %y1 = load i32, ptr %p1, align 4
+ %shl1 = shl nuw i32 1, %y1
+ %p2 = getelementptr inbounds nuw i8, ptr %y, i64 8
+ %y2 = load i32, ptr %p2, align 4
+ %shl2 = shl i32 4, %y2
+ %p3 = getelementptr inbounds nuw i8, ptr %y, i64 12
+ %y3 = load i32, ptr %p3, align 4
+ %shl3 = shl i32 9, %y3
+ %sub3 = sub nsw i32 0, %shl3
+ %and3 = and i32 %shl3, %sub3
+ %p4 = getelementptr inbounds nuw i8, ptr %y, i64 16
+ %y4 = load i32, ptr %p4, align 4
+ %shl4 = shl i32 16, %y4
+ %p5 = getelementptr inbounds nuw i8, ptr %y, i64 20
+ %y5 = load i32, ptr %p5, align 4
+ %shl5 = shl i32 25, %y5
+ %sub5 = sub nsw i32 0, %shl5
+ %and5 = and i32 %shl5, %sub5
+ %p6 = getelementptr inbounds nuw i8, ptr %y, i64 24
+ %y6 = load i32, ptr %p6, align 4
+ %shl6 = shl i32 36, %y6
+ %sub6 = sub nsw i32 0, %shl6
+ %and6 = and i32 %shl6, %sub6
+ %p7 = getelementptr inbounds nuw i8, ptr %y, i64 28
+ %y7 = load i32, ptr %p7, align 4
+ %shl7 = shl i32 49, %y7
+ %sub7 = sub nsw i32 0, %shl7
+ %and7 = and i32 %shl7, %sub7
+ %p8 = getelementptr inbounds nuw i8, ptr %y, i64 32
+ %y8 = load i32, ptr %p8, align 4
+ %shl8 = shl i32 64, %y8
+ %p9 = getelementptr inbounds nuw i8, ptr %y, i64 36
+ %y9 = load i32, ptr %p9, align 4
+ %shl9 = shl i32 81, %y9
+ %sub9 = sub nsw i32 0, %shl9
+ %and9 = and i32 %shl9, %sub9
+ %p10 = getelementptr inbounds nuw i8, ptr %y, i64 40
+ %y10 = load i32, ptr %p10, align 4
+ %shl10 = shl i32 100, %y10
+ %sub10 = sub nsw i32 0, %shl10
+ %and10 = and i32 %shl10, %sub10
+ %p11 = getelementptr inbounds nuw i8, ptr %y, i64 44
+ %y11 = load i32, ptr %p11, align 4
+ %shl11 = shl i32 121, %y11
+ %sub11 = sub nsw i32 0, %shl11
+ %and11 = and i32 %shl11, %sub11
+ %p12 = getelementptr inbounds nuw i8, ptr %y, i64 48
+ %y12 = load i32, ptr %p12, align 4
+ %shl12 = shl i32 144, %y12
+ %sub12 = sub nsw i32 0, %shl12
+ %and12 = and i32 %shl12, %sub12
+ %p13 = getelementptr inbounds nuw i8, ptr %y, i64 52
+ %y13 = load i32, ptr %p13, align 4
+ %shl13 = shl i32 169, %y13
+ %sub13 = sub nsw i32 0, %shl13
+ %and13 = and i32 %shl13, %sub13
+ %p14 = getelementptr inbounds nuw i8, ptr %y, i64 56
+ %y14 = load i32, ptr %p14, align 4
+ %shl14 = shl i32 196, %y14
+ %sub14 = sub nsw i32 0, %shl14
+ %and14 = and i32 %shl14, %sub14
+ %p15 = getelementptr inbounds nuw i8, ptr %y, i64 60
+ %y15 = load i32, ptr %p15, align 4
+ %shl15 = shl i32 225, %y15
+ %sub15 = sub nsw i32 0, %shl15
+ %and15 = and i32 %shl15, %sub15
+ store i32 0, ptr %out, align 4
+ %o1 = getelementptr inbounds nuw i8, ptr %out, i64 4
+ store i32 %shl1, ptr %o1, align 4
+ %o2 = getelementptr inbounds nuw i8, ptr %out, i64 8
+ store i32 %shl2, ptr %o2, align 4
+ %o3 = getelementptr inbounds nuw i8, ptr %out, i64 12
+ store i32 %and3, ptr %o3, align 4
+ %o4 = getelementptr inbounds nuw i8, ptr %out, i64 16
+ store i32 %shl4, ptr %o4, align 4
+ %o5 = getelementptr inbounds nuw i8, ptr %out, i64 20
+ store i32 %and5, ptr %o5, align 4
+ %o6 = getelementptr inbounds nuw i8, ptr %out, i64 24
+ store i32 %and6, ptr %o6, align 4
+ %o7 = getelementptr inbounds nuw i8, ptr %out, i64 28
+ store i32 %and7, ptr %o7, align 4
+ %o8 = getelementptr inbounds nuw i8, ptr %out, i64 32
+ store i32 %shl8, ptr %o8, align 4
+ %o9 = getelementptr inbounds nuw i8, ptr %out, i64 36
+ store i32 %and9, ptr %o9, align 4
+ %o10 = getelementptr inbounds nuw i8, ptr %out, i64 40
+ store i32 %and10, ptr %o10, align 4
+ %o11 = getelementptr inbounds nuw i8, ptr %out, i64 44
+ store i32 %and11, ptr %o11, align 4
+ %o12 = getelementptr inbounds nuw i8, ptr %out, i64 48
+ store i32 %and12, ptr %o12, align 4
+ %o13 = getelementptr inbounds nuw i8, ptr %out, i64 52
+ store i32 %and13, ptr %o13, align 4
+ %o14 = getelementptr inbounds nuw i8, ptr %out, i64 56
+ store i32 %and14, ptr %o14, align 4
+ %o15 = getelementptr inbounds nuw i8, ptr %out, i64 60
+ store i32 %and15, ptr %o15, align 4
+ ret void
+}
+
+; Same, but the copyable lane sits first and there is no constant lane, so
+; the negation column is all instructions and would otherwise alt-shuffle.
+
+define void @and_neg_pow2_copyable_no_const_lane(ptr %out, ptr %y) {
+; CHECK-LABEL: define void @and_neg_pow2_copyable_no_const_lane(
+; CHECK-SAME: ptr [[OUT:%.*]], ptr [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr [[Y]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> <i32 256, i32 289, i32 324, i32 361, i32 400, i32 441, i32 484, i32 529>, [[TMP0]]
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> [[TMP0]], <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[TMP5:%.*]] = shl <8 x i32> <i32 0, i32 289, i32 324, i32 361, i32 400, i32 441, i32 484, i32 529>, [[TMP4]]
+; CHECK-NEXT: [[TMP2:%.*]] = sub nsw <8 x i32> <i32 -1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, [[TMP5]]
+; CHECK-NEXT: [[TMP3:%.*]] = and <8 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr [[OUT]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %y0 = load i32, ptr %y, align 4
+ %shl0 = shl i32 256, %y0
+ %p1 = getelementptr inbounds nuw i8, ptr %y, i64 4
+ %y1 = load i32, ptr %p1, align 4
+ %shl1 = shl i32 289, %y1
+ %sub1 = sub nsw i32 0, %shl1
+ %and1 = and i32 %shl1, %sub1
+ %p2 = getelementptr inbounds nuw i8, ptr %y, i64 8
+ %y2 = load i32, ptr %p2, align 4
+ %shl2 = shl i32 324, %y2
+ %sub2 = sub nsw i32 0, %shl2
+ %and2 = and i32 %shl2, %sub2
+ %p3 = getelementptr inbounds nuw i8, ptr %y, i64 12
+ %y3 = load i32, ptr %p3, align 4
+ %shl3 = shl i32 361, %y3
+ %sub3 = sub nsw i32 0, %shl3
+ %and3 = and i32 %shl3, %sub3
+ %p4 = getelementptr inbounds nuw i8, ptr %y, i64 16
+ %y4 = load i32, ptr %p4, align 4
+ %shl4 = shl i32 400, %y4
+ %sub4 = sub nsw i32 0, %shl4
+ %and4 = and i32 %shl4, %sub4
+ %p5 = getelementptr inbounds nuw i8, ptr %y, i64 20
+ %y5 = load i32, ptr %p5, align 4
+ %shl5 = shl i32 441, %y5
+ %sub5 = sub nsw i32 0, %shl5
+ %and5 = and i32 %shl5, %sub5
+ %p6 = getelementptr inbounds nuw i8, ptr %y, i64 24
+ %y6 = load i32, ptr %p6, align 4
+ %shl6 = shl i32 484, %y6
+ %sub6 = sub nsw i32 0, %shl6
+ %and6 = and i32 %shl6, %sub6
+ %p7 = getelementptr inbounds nuw i8, ptr %y, i64 28
+ %y7 = load i32, ptr %p7, align 4
+ %shl7 = shl i32 529, %y7
+ %sub7 = sub nsw i32 0, %shl7
+ %and7 = and i32 %shl7, %sub7
+ store i32 %shl0, ptr %out, align 4
+ %o1 = getelementptr inbounds nuw i8, ptr %out, i64 4
+ store i32 %and1, ptr %o1, align 4
+ %o2 = getelementptr inbounds nuw i8, ptr %out, i64 8
+ store i32 %and2, ptr %o2, align 4
+ %o3 = getelementptr inbounds nuw i8, ptr %out, i64 12
+ store i32 %and3, ptr %o3, align 4
+ %o4 = getelementptr inbounds nuw i8, ptr %out, i64 16
+ store i32 %and4, ptr %o4, align 4
+ %o5 = getelementptr inbounds nuw i8, ptr %out, i64 20
+ store i32 %and5, ptr %o5, align 4
+ %o6 = getelementptr inbounds nuw i8, ptr %out, i64 24
+ store i32 %and6, ptr %o6, align 4
+ %o7 = getelementptr inbounds nuw i8, ptr %out, i64 28
+ store i32 %and7, ptr %o7, align 4
+ ret void
+}
+
+; The buildvector mixes and(x, sub(0, x)) lanes with a bare argument lane
+; (and a constant lane). The argument is also an operand of one of the and
+; lanes, so it pairs with itself and is modeled as and(V, V), keeping the
+; lane inside the and node instead of and(V, -1).
+
+define <8 x i32> @and_arg_copyable(i32 %a, ptr %y) {
+; CHECK-LABEL: define <8 x i32> @and_arg_copyable(
+; CHECK-SAME: i32 [[A:%.*]], ptr [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 4
+; CHECK-NEXT: [[Y3:%.*]] = load i32, ptr [[P3]], align 4
+; CHECK-NEXT: [[P4:%.*]] = getelementptr inbounds nuw i8, ptr [[Y]], i64 8
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[P4]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> <i32 0, i32 -1, i32 poison, i32 9, i32 16, i32 25, i32 36, i32 49>, i32 [[A]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, i32 [[Y3]], i64 3
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[TMP3]], <8 x i32> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
+; CHECK-NEXT: [[TMP6:%.*]] = shl <8 x i32> [[TMP2]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> <i32 -1, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 [[A]], i64 1
+; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> [[TMP6]], <8 x i32> <i32 poison, i32 poison, i32 2, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> <i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[TMP10:%.*]] = sub nsw <8 x i32> [[TMP7]], [[TMP9]]
+; CHECK-NEXT: [[TMP11:%.*]] = and <8 x i32> [[TMP6]], [[TMP10]]
+; CHECK-NEXT: ret <8 x i32> [[TMP11]]
+;
+entry:
+ %sub2 = sub nsw i32 0, %a
+ %and2 = and i32 %a, %sub2
+ %p3 = getelementptr inbounds nuw i8, ptr %y, i64 4
+ %y3 = load i32, ptr %p3, align 4
+ %shl3 = shl i32 9, %y3
+ %sub3 = sub nsw i32 0, %shl3
+ %and3 = and i32 %shl3, %sub3
+ %p4 = getelementptr inbounds nuw i8, ptr %y, i64 8
+ %y4 = load i32, ptr %p4, align 4
+ %shl4 = shl i32 16, %y4
+ %sub4 = sub nsw i32 0, %shl4
+ %and4 = and i32 %shl4, %sub4
+ %p5 = getelementptr inbounds nuw i8, ptr %y, i64 12
+ %y5 = load i32, ptr %p5, align 4
+ %shl5 = shl i32 25, %y5
+ %sub5 = sub nsw i32 0, %shl5
+ %and5 = and i32 %shl5, %sub5
+ %p6 = getelementptr inbounds nuw i8, ptr %y, i64 16
+ %y6 = load i32, ptr %p6, align 4
+ %shl6 = shl i32 36, %y6
+ %sub6 = sub nsw i32 0, %shl6
+ %and6 = and i32 %shl6, %sub6
+ %p7 = getelementptr inbounds nuw i8, ptr %y, i64 20
+ %y7 = load i32, ptr %p7, align 4
+ %shl7 = shl i32 49, %y7
+ %sub7 = sub nsw i32 0, %shl7
+ %and7 = and i32 %shl7, %sub7
+ %ins0 = insertelement <8 x i32> poison, i32 0, i32 0
+ %ins1 = insertelement <8 x i32> %ins0, i32 %a, i32 1
+ %ins2 = insertelement <8 x i32> %ins1, i32 %and2, i32 2
+ %ins3 = insertelement <8 x i32> %ins2, i32 %and3, i32 3
+ %ins4 = insertelement <8 x i32> %ins3, i32 %and4, i32 4
+ %ins5 = insertelement <8 x i32> %ins4, i32 %and5, i32 5
+ %ins6 = insertelement <8 x i32> %ins5, i32 %and6, i32 6
+ %ins7 = insertelement <8 x i32> %ins6, i32 %and7, i32 7
+ ret <8 x i32> %ins7
+}
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