[llvm] CodeGen: Pass instruction and operand index to isIgnorableUse (PR #219967)
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Mon Aug 31 06:19:32 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
Replace the MachineOperand argument to the TargetInstrInfo::isIgnorableUse
hook with the containing instruction and operand index. The AMDGPU
implementation only used the operand to recover its parent instruction, so
this drops the dependence on MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply@<!-- -->anthropic.com>
---
Full diff: https://github.com/llvm/llvm-project/pull/219967.diff
9 Files Affected:
- (modified) llvm/include/llvm/CodeGen/TargetInstrInfo.h (+3-3)
- (modified) llvm/lib/CodeGen/CalcSpillWeights.cpp (+2-1)
- (modified) llvm/lib/CodeGen/MachineCSE.cpp (+7-4)
- (modified) llvm/lib/CodeGen/MachineCycleAnalysis.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MachineLoopInfo.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MachineSink.cpp (+7-4)
- (modified) llvm/lib/CodeGen/Rematerializer.cpp (+2-1)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+3-3)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+1-1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 4749d06501cb2..cb0394ce2e0c6 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -192,9 +192,9 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
(MI.getDesc().isRematerializable() && isReMaterializableImpl(MI));
}
- /// Given \p MO is a PhysReg use return if it can be ignored for the purpose
- /// of instruction rematerialization or sinking.
- virtual bool isIgnorableUse(const MachineOperand &MO) const {
+ /// Given operand \p OpIdx of \p MI is a PhysReg use, return if it can be
+ /// ignored for the purpose of instruction rematerialization or sinking.
+ virtual bool isIgnorableUse(const MachineInstr &MI, unsigned OpIdx) const {
return false;
}
diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp
index bcdecd6770dbd..e958acdcb064a 100644
--- a/llvm/lib/CodeGen/CalcSpillWeights.cpp
+++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp
@@ -167,7 +167,8 @@ bool VirtRegAuxInfo::allUsesAvailableAt(const MachineInstr *MI,
// We can't remat physreg uses, unless it is a constant or target wants
// to ignore this use.
if (MO.getReg().isPhysical()) {
- if (MRI.isConstantPhysReg(MO.getReg()) || TII.isIgnorableUse(MO))
+ if (MRI.isConstantPhysReg(MO.getReg()) ||
+ TII.isIgnorableUse(*MI, MI->getOperandNo(&MO)))
continue;
return false;
}
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 3d0ac171b9fe4..23ddccbdacd7a 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -256,7 +256,8 @@ bool MachineCSEImpl::isPhysDefTriviallyDead(
}
static bool isCallerPreservedOrConstPhysReg(MCRegister Reg,
- const MachineOperand &MO,
+ const MachineInstr &MI,
+ unsigned OpIdx,
const MachineFunction &MF,
const TargetRegisterInfo &TRI,
const TargetInstrInfo &TII) {
@@ -268,7 +269,8 @@ static bool isCallerPreservedOrConstPhysReg(MCRegister Reg,
// It does cause issues mid-GlobalISel, however, hence the additional
// reservedRegsFrozen check.
const MachineRegisterInfo &MRI = MF.getRegInfo();
- return TRI.isCallerPreservedPhysReg(Reg, MF) || TII.isIgnorableUse(MO) ||
+ return TRI.isCallerPreservedPhysReg(Reg, MF) ||
+ TII.isIgnorableUse(MI, OpIdx) ||
(MRI.reservedRegsFrozen() && MRI.isConstantPhysReg(Reg));
}
@@ -289,8 +291,9 @@ bool MachineCSEImpl::hasLivePhysRegDefUses(const MachineInstr *MI,
if (Reg.isVirtual())
continue;
// Reading either caller preserved or constant physregs is ok.
- if (!isCallerPreservedOrConstPhysReg(Reg.asMCReg(), MO, *MI->getMF(), *TRI,
- *TII))
+ if (!isCallerPreservedOrConstPhysReg(Reg.asMCReg(), *MI,
+ MI->getOperandNo(&MO), *MI->getMF(),
+ *TRI, *TII))
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
PhysRefs.insert(*AI);
}
diff --git a/llvm/lib/CodeGen/MachineCycleAnalysis.cpp b/llvm/lib/CodeGen/MachineCycleAnalysis.cpp
index 4754b6c3510da..21570d533b704 100644
--- a/llvm/lib/CodeGen/MachineCycleAnalysis.cpp
+++ b/llvm/lib/CodeGen/MachineCycleAnalysis.cpp
@@ -143,7 +143,7 @@ bool llvm::isCycleInvariant(const MachineCycleInfo &CI, CycleRef Cycle,
// then this use is safe to hoist.
if (!MRI->isConstantPhysReg(Reg) &&
!(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) &&
- !TII->isIgnorableUse(MO))
+ !TII->isIgnorableUse(I, I.getOperandNo(&MO)))
return false;
// Otherwise it's safe to move.
continue;
diff --git a/llvm/lib/CodeGen/MachineLoopInfo.cpp b/llvm/lib/CodeGen/MachineLoopInfo.cpp
index 943b8746f595f..9fe973bc58f00 100644
--- a/llvm/lib/CodeGen/MachineLoopInfo.cpp
+++ b/llvm/lib/CodeGen/MachineLoopInfo.cpp
@@ -269,7 +269,7 @@ bool MachineLoop::isLoopInvariant(MachineInstr &I,
// then this use is safe to hoist.
if (!isLoopInvariantImplicitPhysReg(Reg) &&
!(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) &&
- !TII->isIgnorableUse(MO))
+ !TII->isIgnorableUse(I, I.getOperandNo(&MO)))
return false;
// Otherwise it's safe to move.
continue;
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 161407cf2cd24..735f172033056 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -356,7 +356,8 @@ static bool blockPrologueInterferes(const MachineBasicBlock *BB,
continue;
if (MO.isUse()) {
if (Reg.isPhysical() &&
- (TII->isIgnorableUse(MO) || (MRI && MRI->isConstantPhysReg(Reg))))
+ (TII->isIgnorableUse(MI, MI.getOperandNo(&MO)) ||
+ (MRI && MRI->isConstantPhysReg(Reg))))
continue;
if (PI->modifiesRegister(Reg, TRI))
return true;
@@ -462,7 +463,8 @@ bool MachineSinking::PerformSinkAndFold(MachineInstr &MI,
}
if (Reg.isPhysical() && MO.isUse() &&
- (MRI->isConstantPhysReg(Reg) || TII->isIgnorableUse(MO)))
+ (MRI->isConstantPhysReg(Reg) ||
+ TII->isIgnorableUse(MI, MI.getOperandNo(&MO))))
continue;
return false;
@@ -1327,7 +1329,7 @@ bool MachineSinking::isProfitableToSinkTo(Register Reg, MachineInstr &MI,
if (Reg.isPhysical()) {
// Don't handle non-constant and non-ignorable physical register uses.
if (MO.isUse() && !MRI->isConstantPhysReg(Reg) &&
- !TII->isIgnorableUse(MO))
+ !TII->isIgnorableUse(MI, MI.getOperandNo(&MO)))
return false;
continue;
}
@@ -1438,7 +1440,8 @@ MachineSinking::FindSuccToSinkTo(MachineInstr &MI, MachineBasicBlock *MBB,
// If the physreg has no defs anywhere, it's just an ambient register
// and we can freely move its uses. Alternatively, if it's allocatable,
// it could get allocated to something with a def during allocation.
- if (!MRI->isConstantPhysReg(Reg) && !TII->isIgnorableUse(MO))
+ if (!MRI->isConstantPhysReg(Reg) &&
+ !TII->isIgnorableUse(MI, MI.getOperandNo(&MO)))
return nullptr;
} else if (!MO.isDead()) {
// A def that isn't dead. We can't move it.
diff --git a/llvm/lib/CodeGen/Rematerializer.cpp b/llvm/lib/CodeGen/Rematerializer.cpp
index c28c0bac6e04b..5d85098400f0d 100644
--- a/llvm/lib/CodeGen/Rematerializer.cpp
+++ b/llvm/lib/CodeGen/Rematerializer.cpp
@@ -655,7 +655,8 @@ bool Rematerializer::isMIRematerializable(const MachineInstr &MI) const {
// We can't remat physreg uses, unless it is a constant or an ignorable
// use (e.g. implicit exec use on VALU instructions)
if (MO.getReg().isPhysical()) {
- if (MRI.isConstantPhysReg(MO.getReg()) || TII.isIgnorableUse(MO))
+ if (MRI.isConstantPhysReg(MO.getReg()) ||
+ TII.isIgnorableUse(MI, MI.getOperandNo(&MO)))
continue;
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 687ca49f514f9..3094c1390e9cf 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -281,11 +281,11 @@ bool SIInstrInfo::resultDependsOnExec(const MachineInstr &MI) const {
return false;
}
-bool SIInstrInfo::isIgnorableUse(const MachineOperand &MO) const {
+bool SIInstrInfo::isIgnorableUse(const MachineInstr &MI, unsigned OpIdx) const {
+ const MachineOperand &MO = MI.getOperand(OpIdx);
// Any implicit use of exec by VALU is not a real register read.
return MO.getReg() == AMDGPU::EXEC && MO.isImplicit() &&
- isVALU(*MO.getParent(), /*AllowLDSDMA=*/true) &&
- !resultDependsOnExec(*MO.getParent());
+ isVALU(MI, /*AllowLDSDMA=*/true) && !resultDependsOnExec(MI);
}
bool SIInstrInfo::isSafeToSink(MachineInstr &MI,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index ab29f0d59d939..be31e17b8a160 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -278,7 +278,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
bool isReMaterializableImpl(const MachineInstr &MI) const override;
- bool isIgnorableUse(const MachineOperand &MO) const override;
+ bool isIgnorableUse(const MachineInstr &MI, unsigned OpIdx) const override;
bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
MachineCycleInfo *CI) const override;
``````````
</details>
https://github.com/llvm/llvm-project/pull/219967
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