[llvm] [X86] Enable preferZeroCompareBranch() (PR #219919)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 31 02:18:42 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Hans Wennborg (zmodem)
<details>
<summary>Changes</summary>
This makes CodeGenPrepare reorganize code such as:
```
%c = icmp eq i32 %x, 10
br %c, then, else
%a = add i32 %x, -10
```
into
```
%a = add i32 %x, -10
%cmp = icmp eq %a, 0
%br %cmp, then, else
```
so that the zero-compare and branch gets lowered to a JCC based on the flags from the arithmetic instruction.
This was already enabled for ARM, SystemZ and RISC-V, but seems a good fit for X86 too.
---
Full diff: https://github.com/llvm/llvm-project/pull/219919.diff
3 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+4)
- (modified) llvm/lib/Target/X86/X86ISelLowering.h (+2)
- (added) llvm/test/CodeGen/X86/branch-on-zero.ll (+601)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index fbebb55cb8c51..fcd9d2c9f6212 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3761,6 +3761,10 @@ bool X86TargetLowering::isCtlzFast() const {
return Subtarget.hasFastLZCNT();
}
+bool X86TargetLowering::preferZeroCompareBranch() const {
+ return true;
+}
+
bool X86TargetLowering::isMaskAndCmp0FoldingBeneficial(
const Instruction &AndI) const {
return true;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index b220c1bbe7bc7..5215bb0704dca 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -238,6 +238,8 @@ namespace llvm {
bool isCtlzFast() const override;
+ bool preferZeroCompareBranch() const override;
+
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
// If the pair to store is a mixture of float and int values, we will
// save two bitwise instructions and one float-to-int instruction and
diff --git a/llvm/test/CodeGen/X86/branch-on-zero.ll b/llvm/test/CodeGen/X86/branch-on-zero.ll
new file mode 100644
index 0000000000000..311ab027993c8
--- /dev/null
+++ b/llvm/test/CodeGen/X86/branch-on-zero.ll
@@ -0,0 +1,601 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple x86_64-unknown-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK64
+; RUN: llc -mtriple i686-unknown-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK32
+
+define i32 @lshr3_then(i32 %a) {
+; CHECK64-LABEL: lshr3_then:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: shrl $3, %edi
+; CHECK64-NEXT: je .LBB0_1
+; CHECK64-NEXT: # %bb.2: # %else
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB0_1: # %then
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: lshr3_then:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: shrl $3, %eax
+; CHECK32-NEXT: je .LBB0_1
+; CHECK32-NEXT: # %bb.2: # %else
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB0_1: # %then
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+entry:
+ %c = icmp ult i32 %a, 8
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 0
+
+else:
+ %l = lshr i32 %a, 3
+ ret i32 %l
+}
+
+define i32 @lshr5_else(i32 %a) {
+; CHECK64-LABEL: lshr5_else:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: shrl $5, %edi
+; CHECK64-NEXT: je .LBB1_1
+; CHECK64-NEXT: # %bb.2: # %else
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB1_1: # %then
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: lshr5_else:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: shrl $5, %eax
+; CHECK32-NEXT: je .LBB1_1
+; CHECK32-NEXT: # %bb.2: # %else
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB1_1: # %then
+; CHECK32-NEXT: retl
+entry:
+ %c = icmp ult i32 %a, 32
+ br i1 %c, label %then, label %else
+
+then:
+ %l = lshr i32 %a, 5
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @lshr2_entry(i32 %a) {
+; CHECK64-LABEL: lshr2_entry:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: shrl %edi
+; CHECK64-NEXT: je .LBB2_1
+; CHECK64-NEXT: # %bb.2: # %else
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB2_1: # %then
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: lshr2_entry:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: shrl %eax
+; CHECK32-NEXT: je .LBB2_1
+; CHECK32-NEXT: # %bb.2: # %else
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB2_1: # %then
+; CHECK32-NEXT: retl
+entry:
+ %l = lshr i32 %a, 1
+ %c = icmp ult i32 %a, 2
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @lshr5mismatch(i32 %a) {
+; CHECK64-LABEL: lshr5mismatch:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: cmpl $16, %edi
+; CHECK64-NEXT: ja .LBB3_2
+; CHECK64-NEXT: # %bb.1: # %then
+; CHECK64-NEXT: shrl $5, %edi
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB3_2: # %else
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: lshr5mismatch:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: cmpl $16, %eax
+; CHECK32-NEXT: ja .LBB3_2
+; CHECK32-NEXT: # %bb.1: # %then
+; CHECK32-NEXT: shrl $5, %eax
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB3_2: # %else
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+entry:
+ %c = icmp ult i32 %a, 17
+ br i1 %c, label %then, label %else
+
+then:
+ %l = lshr i32 %a, 5
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @ashr5_else(i32 %a) {
+; CHECK64-LABEL: ashr5_else:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: sarl $5, %edi
+; CHECK64-NEXT: je .LBB4_1
+; CHECK64-NEXT: # %bb.2: # %else
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB4_1: # %then
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: ashr5_else:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: sarl $5, %eax
+; CHECK32-NEXT: je .LBB4_1
+; CHECK32-NEXT: # %bb.2: # %else
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB4_1: # %then
+; CHECK32-NEXT: retl
+entry:
+ %c = icmp ult i32 %a, 32
+ br i1 %c, label %then, label %else
+
+then:
+ %l = ashr i32 %a, 5
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @add10_else(i32 %a) {
+; CHECK64-LABEL: add10_else:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: cmpl $10, %edi
+; CHECK64-NEXT: jne .LBB5_2
+; CHECK64-NEXT: # %bb.1: # %then
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB5_2: # %else
+; CHECK64-NEXT: addl $10, %edi
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: add10_else:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: cmpl $10, %eax
+; CHECK32-NEXT: jne .LBB5_2
+; CHECK32-NEXT: # %bb.1: # %then
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB5_2: # %else
+; CHECK32-NEXT: addl $10, %eax
+; CHECK32-NEXT: retl
+entry:
+ %c = icmp eq i32 %a, 10
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 0
+
+else:
+ %l = add i32 %a, 10
+ ret i32 %l
+}
+
+define i32 @addm10_then(i32 %a) {
+; CHECK64-LABEL: addm10_then:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: addl $-10, %edi
+; CHECK64-NEXT: je .LBB6_1
+; CHECK64-NEXT: # %bb.2: # %else
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB6_1: # %then
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: addm10_then:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: addl $-10, %eax
+; CHECK32-NEXT: je .LBB6_1
+; CHECK32-NEXT: # %bb.2: # %else
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB6_1: # %then
+; CHECK32-NEXT: retl
+entry:
+ %c = icmp eq i32 %a, 10
+ br i1 %c, label %then, label %else
+
+then:
+ %l = add i32 %a, -10
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @add_missmatch(i32 %a) {
+; CHECK64-LABEL: add_missmatch:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: cmpl $10, %edi
+; CHECK64-NEXT: jne .LBB7_2
+; CHECK64-NEXT: # %bb.1: # %then
+; CHECK64-NEXT: addl $10, %edi
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB7_2: # %else
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: add_missmatch:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: cmpl $10, %eax
+; CHECK32-NEXT: jne .LBB7_2
+; CHECK32-NEXT: # %bb.1: # %then
+; CHECK32-NEXT: addl $10, %eax
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB7_2: # %else
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+entry:
+ %c = icmp eq i32 %a, 10
+ br i1 %c, label %then, label %else
+
+then:
+ %l = add i32 %a, 10
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @sub10_else(i32 %a) {
+; CHECK64-LABEL: sub10_else:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: addl $-10, %edi
+; CHECK64-NEXT: je .LBB8_1
+; CHECK64-NEXT: # %bb.2: # %else
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB8_1: # %then
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: sub10_else:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: addl $-10, %eax
+; CHECK32-NEXT: je .LBB8_1
+; CHECK32-NEXT: # %bb.2: # %else
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB8_1: # %then
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+entry:
+ %c = icmp eq i32 %a, 10
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 0
+
+else:
+ %l = sub i32 %a, 10
+ ret i32 %l
+}
+
+define i32 @sub10_else_drop_nuw(i32 %a) {
+; CHECK64-LABEL: sub10_else_drop_nuw:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: addl $-10, %edi
+; CHECK64-NEXT: je .LBB9_1
+; CHECK64-NEXT: # %bb.2: # %else
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB9_1: # %then
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: sub10_else_drop_nuw:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: addl $-10, %eax
+; CHECK32-NEXT: je .LBB9_1
+; CHECK32-NEXT: # %bb.2: # %else
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB9_1: # %then
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+entry:
+ %c = icmp eq i32 %a, 10
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 0
+
+else:
+ %l = sub nuw i32 %a, 10
+ ret i32 %l
+}
+
+define i32 @subm10_then(i32 %a) {
+; CHECK64-LABEL: subm10_then:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: addl $10, %edi
+; CHECK64-NEXT: je .LBB10_1
+; CHECK64-NEXT: # %bb.2: # %else
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB10_1: # %then
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: subm10_then:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: addl $10, %eax
+; CHECK32-NEXT: je .LBB10_1
+; CHECK32-NEXT: # %bb.2: # %else
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB10_1: # %then
+; CHECK32-NEXT: retl
+entry:
+ %c = icmp eq i32 %a, -10
+ br i1 %c, label %then, label %else
+
+then:
+ %l = sub i32 %a, -10
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i64 @lshr64(i64 %a) {
+; CHECK64-LABEL: lshr64:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: shrq $40, %rdi
+; CHECK64-NEXT: je .LBB11_1
+; CHECK64-NEXT: # %bb.2: # %else
+; CHECK64-NEXT: movq %rdi, %rax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB11_1: # %then
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: lshr64:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: shrl $8, %eax
+; CHECK32-NEXT: je .LBB11_1
+; CHECK32-NEXT: # %bb.2: # %else
+; CHECK32-NEXT: xorl %edx, %edx
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB11_1: # %then
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: xorl %edx, %edx
+; CHECK32-NEXT: retl
+entry:
+ %c = icmp ult i64 %a, 1099511627776
+ br i1 %c, label %then, label %else
+
+then:
+ ret i64 0
+
+else:
+ %l = lshr i64 %a, 40
+ ret i64 %l
+}
+
+define i128 @lshr128(i128 %a) {
+; CHECK64-LABEL: lshr128:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: shrq %rsi
+; CHECK64-NEXT: je .LBB12_1
+; CHECK64-NEXT: # %bb.2: # %else
+; CHECK64-NEXT: movq %rsi, %rax
+; CHECK64-NEXT: xorl %edx, %edx
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB12_1: # %then
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: xorl %edx, %edx
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: lshr128:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: pushl %esi
+; CHECK32-NEXT: .cfi_def_cfa_offset 8
+; CHECK32-NEXT: subl $8, %esp
+; CHECK32-NEXT: .cfi_def_cfa_offset 16
+; CHECK32-NEXT: .cfi_offset %esi, -8
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
+; CHECK32-NEXT: shrdl $1, %edx, %ecx
+; CHECK32-NEXT: shrl %edx
+; CHECK32-NEXT: movl %ecx, %esi
+; CHECK32-NEXT: orl %edx, %esi
+; CHECK32-NEXT: je .LBB12_1
+; CHECK32-NEXT: # %bb.3: # %else
+; CHECK32-NEXT: movl %ecx, (%eax)
+; CHECK32-NEXT: movl %edx, 4(%eax)
+; CHECK32-NEXT: movl $0, 12(%eax)
+; CHECK32-NEXT: movl $0, 8(%eax)
+; CHECK32-NEXT: jmp .LBB12_2
+; CHECK32-NEXT: .LBB12_1: # %then
+; CHECK32-NEXT: movl $0, 12(%eax)
+; CHECK32-NEXT: movl $0, 8(%eax)
+; CHECK32-NEXT: movl $0, 4(%eax)
+; CHECK32-NEXT: movl $0, (%eax)
+; CHECK32-NEXT: .LBB12_2: # %then
+; CHECK32-NEXT: addl $8, %esp
+; CHECK32-NEXT: .cfi_def_cfa_offset 8
+; CHECK32-NEXT: popl %esi
+; CHECK32-NEXT: .cfi_def_cfa_offset 4
+; CHECK32-NEXT: retl $4
+entry:
+ %c = icmp ult i128 %a, 36893488147419103232
+ br i1 %c, label %then, label %else
+
+then:
+ ret i128 0
+
+else:
+ %l = lshr i128 %a, 65
+ ret i128 %l
+}
+
+define i32 @addm1_dom(i32 %a) {
+; CHECK64-LABEL: addm1_dom:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: cmpl $100, %edi
+; CHECK64-NEXT: jne .LBB13_3
+; CHECK64-NEXT: # %bb.1: # %if
+; CHECK64-NEXT: cmpl $-1, %edi
+; CHECK64-NEXT: je .LBB13_2
+; CHECK64-NEXT: .LBB13_3: # %else
+; CHECK64-NEXT: incl %edi
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB13_2: # %then
+; CHECK64-NEXT: xorl %eax, %eax
+; CHECK64-NEXT: retq
+;
+; CHECK32-LABEL: addm1_dom:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: cmpl $100, %eax
+; CHECK32-NEXT: jne .LBB13_3
+; CHECK32-NEXT: # %bb.1: # %if
+; CHECK32-NEXT: cmpl $-1, %eax
+; CHECK32-NEXT: je .LBB13_2
+; CHECK32-NEXT: .LBB13_3: # %else
+; CHECK32-NEXT: incl %eax
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB13_2: # %then
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: retl
+entry:
+ %c1 = icmp eq i32 %a, 100
+ br i1 %c1, label %if, label %else
+
+if:
+ %c = icmp eq i32 %a, -1
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 0
+
+else:
+ %l = add i32 %a, 1
+ ret i32 %l
+}
+
+define i32 @xor_branch_imm_ret(i32 %x) {
+; CHECK64-LABEL: xor_branch_imm_ret:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: xorl $-1365, %eax # imm = 0xFAAB
+; CHECK64-NEXT: je .LBB14_2
+; CHECK64-NEXT: # %bb.1: # %if.then
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB14_2: # %if.end
+; CHECK64-NEXT: pushq %rax
+; CHECK64-NEXT: .cfi_def_cfa_offset 16
+; CHECK64-NEXT: callq other at PLT
+;
+; CHECK32-LABEL: xor_branch_imm_ret:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: subl $12, %esp
+; CHECK32-NEXT: .cfi_def_cfa_offset 16
+; CHECK32-NEXT: movl $-1365, %eax # imm = 0xFAAB
+; CHECK32-NEXT: xorl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: je .LBB14_2
+; CHECK32-NEXT: # %bb.1: # %if.then
+; CHECK32-NEXT: addl $12, %esp
+; CHECK32-NEXT: .cfi_def_cfa_offset 4
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB14_2: # %if.end
+; CHECK32-NEXT: .cfi_def_cfa_offset 16
+; CHECK32-NEXT: calll other at PLT
+entry:
+ %cmp.not = icmp eq i32 %x, -1365
+ br i1 %cmp.not, label %if.end, label %if.then
+if.then:
+ %xor = xor i32 %x, -1365
+ ret i32 %xor
+if.end:
+ tail call void @other()
+ unreachable
+}
+
+define i32 @xor_branch_ret(i32 %x) {
+; CHECK64-LABEL: xor_branch_ret:
+; CHECK64: # %bb.0: # %entry
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: xorl $2048, %eax # imm = 0x800
+; CHECK64-NEXT: je .LBB15_2
+; CHECK64-NEXT: # %bb.1: # %if.then
+; CHECK64-NEXT: retq
+; CHECK64-NEXT: .LBB15_2: # %if.end
+; CHECK64-NEXT: pushq %rax
+; CHECK64-NEXT: .cfi_def_cfa_offset 16
+; CHECK64-NEXT: callq other at PLT
+;
+; CHECK32-LABEL: xor_branch_ret:
+; CHECK32: # %bb.0: # %entry
+; CHECK32-NEXT: subl $12, %esp
+; CHECK32-NEXT: .cfi_def_cfa_offset 16
+; CHECK32-NEXT: movl $2048, %eax # imm = 0x800
+; CHECK32-NEXT: xorl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: je .LBB15_2
+; CHECK32-NEXT: # %bb.1: # %if.then
+; CHECK32-NEXT: addl $12, %esp
+; CHECK32-NEXT: .cfi_def_cfa_offset 4
+; CHECK32-NEXT: retl
+; CHECK32-NEXT: .LBB15_2: # %if.end
+; CHECK32-NEXT: .cfi_def_cfa_offset 16
+; CHECK32-NEXT: calll other at PLT
+entry:
+ %cmp.not = icmp eq i32 %x, 2048
+ br i1 %cmp.not, label %if.end, label %if.then
+if.then:
+ %xor = xor i32 %x, 2048
+ ret i32 %xor
+if.end:
+ tail call void @other()
+ unreachable
+}
+
+declare void @other()
``````````
</details>
https://github.com/llvm/llvm-project/pull/219919
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