[llvm] [LV] Auto generate RISCV analysis tests. NFC (PR #219879)
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llvm-commits at lists.llvm.org
Sun Aug 30 22:13:35 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-backend-risc-v
Author: Elvis Wang (ElvisWang123)
<details>
<summary>Changes</summary>
This patch re-generate some analysis RISCV tests by automatic update scripts to make tests easier to update when changes.
---
Patch is 37.82 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/219879.diff
4 Files Affected:
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-maxbandwidth.ll (+1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll (+75-77)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction-cost.ll (+14-11)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll (+205-167)
``````````diff
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-maxbandwidth.ll b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-maxbandwidth.ll
index e16555a4c23ac..41f1a9b45b7ff 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-maxbandwidth.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-maxbandwidth.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "LV\(REG\): (?!At)" --filter "LV: Selecting VF" --version 6
; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v -vectorizer-maximize-bandwidth -debug-only=loop-vectorize,vplan -disable-output -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-REGS-VP
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
index ccf989d80efde..31ccd43911139 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
@@ -1,62 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "LV\(REG\): (?!At)" --version 6
; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
; RUN: -mattr=+v,+d -debug-only=loop-vectorize,vplan --disable-output \
-; RUN: -force-vector-width=1 -tail-folding-policy=dont-fold-tail \
-; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-SCALAR
-; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
-; RUN: -mattr=+v,+d -debug-only=loop-vectorize,vplan --disable-output \
-; RUN: -riscv-v-register-bit-width-lmul=1 \
-; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL1
-; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
-; RUN: -mattr=+v,+d -debug-only=loop-vectorize,vplan --disable-output \
-; RUN: -riscv-v-register-bit-width-lmul=2 \
-; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL2
-; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
-; RUN: -mattr=+v,+d -debug-only=loop-vectorize,vplan --disable-output \
-; RUN: -riscv-v-register-bit-width-lmul=4 \
-; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL4
-; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
-; RUN: -mattr=+v,+d -debug-only=loop-vectorize,vplan --disable-output \
; RUN: -riscv-v-register-bit-width-lmul=8 \
-; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL8
+; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK
define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) {
-; CHECK-SCALAR-LABEL: add
-; CHECK-SCALAR: LV(REG): VF = 1
-; CHECK-SCALAR-NEXT: LV(REG): Found max usage: 2 item
-; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
-; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::FPRRC, 2 registers
-; CHECK-SCALAR-NEXT: LV(REG): Found invariant usage: 1 item
-; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
-; CHECK-LMUL1-LABEL: add
-; CHECK-LMUL1: LV(REG): VF = vscale x 2
-; CHECK-LMUL1-NEXT: LV(REG): Found max usage: 2 item
-; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers
-; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
-; CHECK-LMUL1-NEXT: LV(REG): Found invariant usage: 1 item
-; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
-; CHECK-LMUL2-LABEL: add
-; CHECK-LMUL2: LV(REG): VF = vscale x 4
-; CHECK-LMUL2-NEXT: LV(REG): Found max usage: 2 item
-; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers
-; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
-; CHECK-LMUL2-NEXT: LV(REG): Found invariant usage: 1 item
-; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
-; CHECK-LMUL4-LABEL: add
-; CHECK-LMUL4: LV(REG): VF = vscale x 8
-; CHECK-LMUL4-NEXT: LV(REG): Found max usage: 2 item
-; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers
-; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 8 registers
-; CHECK-LMUL4-NEXT: LV(REG): Found invariant usage: 1 item
-; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
-; CHECK-LMUL8-LABEL: add
-; CHECK-LMUL8: LV(REG): VF = vscale x 16
-; CHECK-LMUL8-NEXT: LV(REG): Found max usage: 2 item
-; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers
-; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 16 registers
-; CHECK-LMUL8-NEXT: LV(REG): Found invariant usage: 1 item
-; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
-
+; CHECK-LABEL: 'add'
+; CHECK: LV(REG): Calculating max register usage:
+; CHECK: LV(REG): VF = 1
+; CHECK: LV(REG): Found max usage: 2 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
+; CHECK: LV(REG): RegisterClass: RISCV::FPRRC, 2 registers
+; CHECK: LV(REG): Found invariant usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
+; CHECK: LV(REG): Calculating max register usage:
+; CHECK: LV(REG): VF = vscale x 1
+; CHECK: LV(REG): Found max usage: 2 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers
+; CHECK: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
+; CHECK: LV(REG): Found invariant usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
+; CHECK: LV(REG): VF = vscale x 2
+; CHECK: LV(REG): Found max usage: 2 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers
+; CHECK: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
+; CHECK: LV(REG): Found invariant usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
+; CHECK: LV(REG): VF = vscale x 4
+; CHECK: LV(REG): Found max usage: 2 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers
+; CHECK: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
+; CHECK: LV(REG): Found invariant usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
+; CHECK: LV(REG): VF = vscale x 8
+; CHECK: LV(REG): Found max usage: 2 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers
+; CHECK: LV(REG): RegisterClass: RISCV::VRRC, 8 registers
+; CHECK: LV(REG): Found invariant usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
+; CHECK: LV(REG): VF = vscale x 16
+; CHECK: LV(REG): Found max usage: 2 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers
+; CHECK: LV(REG): RegisterClass: RISCV::VRRC, 16 registers
+; CHECK: LV(REG): Found invariant usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
+;
entry:
%conv = zext i32 %size to i64
%cmp10.not = icmp eq i32 %size, 0
@@ -80,30 +69,39 @@ for.body:
}
define void @goo(ptr nocapture noundef %a, i32 noundef signext %n) {
-; CHECK-SCALAR-LABEL: goo
-; CHECK-SCALAR: LV(REG): VF = 1
-; CHECK-SCALAR-NEXT: LV(REG): Found max usage: 1 item
-; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
-; CHECK-LMUL1-LABEL: goo
-; CHECK-LMUL1: LV(REG): VF = vscale x 1
-; CHECK-LMUL1-NEXT: LV(REG): Found max usage: 2 item
-; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 5 registers
-; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 1 registers
-; CHECK-LMUL2-LABEL: goo
-; CHECK-LMUL2: LV(REG): VF = vscale x 2
-; CHECK-LMUL2-NEXT: LV(REG): Found max usage: 2 item
-; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 5 registers
-; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
-; CHECK-LMUL4-LABEL: goo
-; CHECK-LMUL4: LV(REG): VF = vscale x 4
-; CHECK-LMUL4-NEXT: LV(REG): Found max usage: 2 item
-; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 5 registers
-; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
-; CHECK-LMUL8-LABEL: goo
-; CHECK-LMUL8: LV(REG): VF = vscale x 8
-; CHECK-LMUL8-NEXT: LV(REG): Found max usage: 2 item
-; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 5 registers
-; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 8 registers
+; CHECK-LABEL: 'goo'
+; CHECK: LV(REG): Calculating max register usage:
+; CHECK: LV(REG): VF = 1
+; CHECK: LV(REG): Found max usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
+; CHECK: LV(REG): Found invariant usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
+; CHECK: LV(REG): Calculating max register usage:
+; CHECK: LV(REG): VF = vscale x 1
+; CHECK: LV(REG): Found max usage: 2 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 5 registers
+; CHECK: LV(REG): RegisterClass: RISCV::VRRC, 1 registers
+; CHECK: LV(REG): Found invariant usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
+; CHECK: LV(REG): VF = vscale x 2
+; CHECK: LV(REG): Found max usage: 2 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 5 registers
+; CHECK: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
+; CHECK: LV(REG): Found invariant usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
+; CHECK: LV(REG): VF = vscale x 4
+; CHECK: LV(REG): Found max usage: 2 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 5 registers
+; CHECK: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
+; CHECK: LV(REG): Found invariant usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
+; CHECK: LV(REG): VF = vscale x 8
+; CHECK: LV(REG): Found max usage: 2 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 5 registers
+; CHECK: LV(REG): RegisterClass: RISCV::VRRC, 8 registers
+; CHECK: LV(REG): Found invariant usage: 1 item
+; CHECK: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
+;
entry:
%cmp3 = icmp sgt i32 %n, 0
br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction-cost.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction-cost.ll
index 99445ce6c0d04..1c644aadfd8ad 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction-cost.ll
@@ -1,20 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "Cost of.*(WIDEN-REDUCTION-PHI|WIDEN-INTRINSIC)" --version 6
; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize --disable-output \
; RUN: -tail-folding-policy=prefer-fold-tail -vectorizer-maximize-bandwidth \
; RUN: -mtriple=riscv64 -mattr=+v -S < %s 2>&1 | FileCheck %s
-; CHECK: Cost of 0 for VF vscale x 4: WIDEN-REDUCTION-PHI ir<%rdx> = phi
-; CHECK: Cost of 0 for VF vscale x 4: WIDEN-INTRINSIC vp<%{{.+}}> = call llvm.vp.merge(ir<true>, ir<%add>, ir<%rdx>, vp<%{{.+}}>)
-
-; CHECK: Cost of 0 for VF vscale x 8: WIDEN-REDUCTION-PHI ir<%rdx> = phi
-; CHECK: Cost of 0 for VF vscale x 8: WIDEN-INTRINSIC vp<%{{.+}}> = call llvm.vp.merge(ir<true>, ir<%add>, ir<%rdx>, vp<%{{.+}}>)
-
-; Type needs split, won't be folded:
-
-; CHECK: Cost of 0 for VF vscale x 16: WIDEN-REDUCTION-PHI ir<%rdx> = phi
-; CHECK: Cost of 16 for VF vscale x 16: WIDEN-INTRINSIC vp<%{{.+}}> = call llvm.vp.merge(ir<true>, ir<%add>, ir<%rdx>, vp<%{{.+}}>)
-
+; When the type needs split, vp.merge won't be folded.
define i64 @add(ptr %a, i64 %n, i64 %start) {
+; CHECK-LABEL: 'add'
+; CHECK: Cost of 0 for VF vscale x 1: WIDEN-REDUCTION-PHI ir<%rdx> = phi (add) vp<[[VP2:%[0-9]+]]>, vp<[[VP9:%[0-9]+]]>
+; CHECK: Cost of 0 for VF vscale x 1: WIDEN-INTRINSIC vp<[[VP9]]> = call llvm.vp.merge(ir<true>, ir<%add>, ir<%rdx>, vp<%evl>)
+; CHECK: Cost of 0 for VF vscale x 2: WIDEN-REDUCTION-PHI ir<%rdx> = phi (add) vp<[[VP2]]>, vp<[[VP9]]>
+; CHECK: Cost of 0 for VF vscale x 2: WIDEN-INTRINSIC vp<[[VP9]]> = call llvm.vp.merge(ir<true>, ir<%add>, ir<%rdx>, vp<%evl>)
+; CHECK: Cost of 0 for VF vscale x 4: WIDEN-REDUCTION-PHI ir<%rdx> = phi (add) vp<[[VP2]]>, vp<[[VP9]]>
+; CHECK: Cost of 0 for VF vscale x 4: WIDEN-INTRINSIC vp<[[VP9]]> = call llvm.vp.merge(ir<true>, ir<%add>, ir<%rdx>, vp<%evl>)
+; CHECK: Cost of 0 for VF vscale x 8: WIDEN-REDUCTION-PHI ir<%rdx> = phi (add) vp<[[VP2]]>, vp<[[VP9]]>
+; CHECK: Cost of 0 for VF vscale x 8: WIDEN-INTRINSIC vp<[[VP9]]> = call llvm.vp.merge(ir<true>, ir<%add>, ir<%rdx>, vp<%evl>)
+; CHECK: Cost of 0 for VF vscale x 16: WIDEN-REDUCTION-PHI ir<%rdx> = phi (add) vp<[[VP2]]>, vp<[[VP9]]>
+; CHECK: Cost of 16 for VF vscale x 16: WIDEN-INTRINSIC vp<[[VP9]]> = call llvm.vp.merge(ir<true>, ir<%add>, ir<%rdx>, vp<%evl>)
+;
entry:
br label %loop
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll
index 23f5de1399d52..4b84e9bcb687f 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll
@@ -1,208 +1,246 @@
-; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize \
-; RUN: -tail-folding-policy=prefer-fold-tail \
-; RUN: -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -disable-output < %s 2>&1 | FileCheck --check-prefixes=IF-EVL-OUTLOOP,IF-EVL %s
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter-out-after "^scalar.ph" --version 6
+; RUN: opt -passes=loop-vectorize --vplan-print-after=printOptimizedVPlan \
+; RUN: -tail-folding-policy=prefer-fold-tail -force-vector-width=1 \
+; RUN: -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -disable-output < %s 2>&1 | FileCheck --check-prefixes=IF-EVL %s
-; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize \
+; RUN: opt -passes=loop-vectorize --vplan-print-after=printOptimizedVPlan \
+; RUN: -tail-folding-policy=prefer-fold-tail -force-vector-width="vscale x 4" \
+; RUN: -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -disable-output < %s 2>&1 | FileCheck --check-prefixes=IF-EVL-OUTLOOP %s
+
+; RUN: opt -passes=loop-vectorize --vplan-print-after=printOptimizedVPlan \
; RUN: -prefer-inloop-reductions \
-; RUN: -tail-folding-policy=prefer-fold-tail \
-; RUN: -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -disable-output < %s 2>&1 | FileCheck --check-prefixes=IF-EVL-INLOOP,IF-EVL %s
+; RUN: -tail-folding-policy=prefer-fold-tail -force-vector-width="vscale x 4" \
+; RUN: -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -disable-output < %s 2>&1 | FileCheck --check-prefixes=IF-EVL-INLOOP %s
-; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize \
-; RUN: -tail-folding-policy=dont-fold-tail \
+; RUN: opt -passes=loop-vectorize --vplan-print-after=printOptimizedVPlan \
+; RUN: -tail-folding-policy=dont-fold-tail -force-vector-width="vscale x 4" \
; RUN: -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -disable-output < %s 2>&1 | FileCheck --check-prefixes=NO-VP-OUTLOOP %s
-; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize \
+; RUN: opt -passes=loop-vectorize --vplan-print-after=printOptimizedVPlan \
; RUN: -prefer-inloop-reductions \
-; RUN: -tail-folding-policy=dont-fold-tail \
+; RUN: -tail-folding-policy=dont-fold-tail -force-vector-width="vscale x 4" \
; RUN: -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -disable-output < %s 2>&1 | FileCheck --check-prefixes=NO-VP-INLOOP %s
+; Check not generate CURRENT-ITERSTION-PHI when VF=1.
define i32 @reduction(ptr %a, i64 %n, i32 %start) {
-; IF-EVL: VPlan 'Initial VPlan for VF={1},UF>=1'
-; IF-EVL-NOT: CURRENT-ITERATION-PHI
-
-; IF-EVL-OUTLOOP: VPlan 'Initial VPlan for VF={vscale x 1,vscale x 2,vscale x 4},UF={1}' {
-; IF-EVL-OUTLOOP-NEXT: Live-in vp<[[VFUF:%[0-9]+]]> = VF * UF
-; IF-EVL-OUTLOOP-NEXT: Live-in vp<[[VTC:%[0-9]+]]> = vector-trip-count
-; IF-EVL-OUTLOOP-NEXT: Live-in ir<%n> = original trip-count
+; IF-EVL-LABEL: VPlan for loop in 'reduction'
+; IF-EVL: VPlan 'Initial VPlan for VF={1},UF>=1' {
+; IF-EVL-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; IF-EVL-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; IF-EVL-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; IF-EVL-NEXT: Live-in ir<%n> = original trip-count
+; IF-EVL-EMPTY:
+; IF-EVL-NEXT: ir-bb<entry>:
+; IF-EVL-NEXT: Successor(s): scalar.ph, vector.ph
+; IF-EVL-EMPTY:
+; IF-EVL-NEXT: vector.ph:
+; IF-EVL-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<%start>, ir<0>, ir<1>
+; IF-EVL-NEXT: Successor(s): vector loop
+; IF-EVL-EMPTY:
+; IF-EVL-NEXT: <x1> vector loop: {
+; IF-EVL-NEXT: vp<[[VP4:%[0-9]+]]> = CANONICAL-IV
+; IF-EVL-EMPTY:
+; IF-EVL-NEXT: vector.body:
+; IF-EVL-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi (add) vp<[[VP3]]>, ir<%add>
+; IF-EVL-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
+; IF-EVL-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%a>, vp<[[VP5]]>
+; IF-EVL-NEXT: CLONE ir<%0> = load ir<%arrayidx>
+; IF-EVL-NEXT: CLONE ir<%add> = add ir<%0>, ir<%rdx>
+; IF-EVL-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
+; IF-EVL-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; IF-EVL-NEXT: No successors
+; IF-EVL-NEXT: }
+; IF-EVL-NEXT: Successor(s): middle.block
+; IF-EVL-EMPTY:
+; IF-EVL-NEXT: middle.block:
+; IF-EVL-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (add) ir<%add>
+; IF-EVL-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]>
+; IF-EVL-NEXT: EMIT branch-on-cond vp<%cmp.n>
+; IF-EVL-NEXT: Successor(s): ir-bb<for.end>, scalar.ph
+; IF-EVL-EMPTY:
+; IF-EVL-NEXT: ir-bb<for.end>:
+; IF-EVL-NEXT: IR %add.lcssa = phi i32 [ %add, %for.body ] (extra operand: vp<[[VP7]]> from middle.block)
+; IF-EVL-NEXT: No successors
+; IF-EVL-EMPTY:
+; IF-EVL-NEXT: scalar.ph:
+;
+; IF-EVL-OUTLOOP-LABEL: VPlan for loop in 'reduction'
+; IF-EVL-OUTLOOP: VPlan 'Initial VPlan for VF={vscale x 4},UF={1}' {
+; IF-EVL-OUTLOOP-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF * UF
+; IF-EVL-OUTLOOP-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = vector-trip-count
+; IF-EVL-OUTLOOP-NEXT: Live-in ir<%n> = original trip-count
; IF-EVL-OUTLOOP-EMPTY:
-; IF-EVL-OUTLOOP-NEXT: ir-bb<entry>:
-; IF-EVL-OUTLOOP-NEXT: Successor(s): scalar.ph, vector.ph
+; IF-EVL-OUTLOOP-NEXT: ir-bb<entry>:
+; IF-EVL-OUTLOOP-NEXT: Successor(s): scalar.ph, vector.ph
; IF-EVL-OUTLOOP-EMPTY:
-; IF-EVL-OUTLOOP-NEXT: vector.ph:
-; IF-EVL-OUTLOOP-NEXT: EMIT vp<[[RDX_START:%.]]> = reduction-start-vector ir<%start>, ir<0>, ir<1>
-; IF-EVL-OUTLOOP-NEXT: Successor(s): vector loop
+; IF-EVL-OUTLOOP-NEXT: vector.ph:
+; IF-EVL-OUTLOOP-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = reduction-start-vector ir<%start>, ir<0>, ir<1>
+; IF-EVL-OUTLOOP-NEXT: Successor(s): vector loop
; IF-EVL-OUTLOOP-EMPTY:
-; IF-EVL-OUTLOOP-NEXT: <x1> vector loop: {
-; IF-EVL-OUTLOOP-NEXT: vp<[[IV:%[0-9]+]]> = CANONICAL-IV
+; IF-EVL-OUTLOOP-NEXT: <x1> vector loop: {
+; IF-EVL-OUTLOOP-NEXT: vp<[[VP3:%[0-9]+]]> = CANONICAL-IV
; IF-EVL-OUTLOOP-EMPTY:
-; IF-EVL-OUTLOOP-NEXT: vector.body:
-; IF-EVL-OUTLOOP-NEXT: CURRENT-ITERATION-PHI vp<[[EVL_PHI:%[0-9]+]]> = phi ir<0>, vp<[[IV_NEXT:%.+]]>
-; IF-EVL-OUTLOOP-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX_PHI:%.+]]> = phi (add) vp<[[RDX_START]]>, vp<[[RDX_SELECT:%.+]]>
-; IF-EVL-OUTLOOP-NEXT: EMIT-SCALAR vp<[[AVL:%.+]]> = phi [ ir<%n>, vector.ph ], [ vp<[[AVL_NEXT:%.+]]>, vector.body ]
-; IF-EVL-OUTLOOP-NEXT: EMIT-SCALAR vp<[[EVL:%.+]]> = EXPLICIT-VECTOR-LENGTH vp<[[AVL]]>
-; IF-EVL-OUTLOOP-NEXT: EMIT-SCALAR vp<[[CAST:%[0-9]+]]> = zext vp<[[EVL]]> to i64
-; IF-EVL-OUTLOOP-NEXT: vp<[[ST:%[0-9]+]]> = SCALAR-STEPS vp<[[EVL_PHI]]>, ir<1>, vp<[[CAST]]>
-; IF-EVL-OUTLOOP-NEXT: CLONE ir<[[GEP1:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
-; IF-EVL-OUTLOOP-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer inbounds i32, ir<[[GEP1]]>
-; IF-EVL-OUTLOOP-NEXT: WIDEN ir<[[LD1:%.+]]> = vp.load vp<[[PTR1]]>, vp<[[EVL]]>
-; IF-EVL-OUTLOOP-NEXT: WIDEN ir<[[ADD:%.+]]> = add ir<[[LD1]]>, ir<[[RDX_PHI]]>
-; IF-EVL-OUTLOOP-NEXT: WIDEN-INTRINSIC vp<[[RDX_SELECT]]> = call llvm.vp.merge(ir<true>, ir<[[ADD]]>, ir<[[RDX_PHI]]>, vp<[[EVL]]>)
-; IF-EVL-OUTLOOP-NEXT: EMIT-SCALAR vp<[[CAST2:%[0-9]+]]> = zext vp<[[EVL]]> to i64
-; IF-EVL-OUTLOOP-NEXT: EMIT vp<[[IV_NEXT]]> = add vp<[[CAST2]]>, vp<[[EVL_PHI]]>
-; IF-EVL-OUTLOOP-NEXT: EMIT vp<[[AVL_NEX...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/219879
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