[llvm] e971feb - [SLP][NFC]Add an extra test for gathered splats, NFC
via llvm-commits
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Sun Aug 30 07:07:13 PDT 2026
Author: Alexey Bataev
Date: 2026-08-30T10:07:09-04:00
New Revision: e971feb7909bd5527367298321d2839a2ec0020f
URL: https://github.com/llvm/llvm-project/commit/e971feb7909bd5527367298321d2839a2ec0020f
DIFF: https://github.com/llvm/llvm-project/commit/e971feb7909bd5527367298321d2839a2ec0020f.diff
LOG: [SLP][NFC]Add an extra test for gathered splats, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/219805
Added:
llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-extracts.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-extracts.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-extracts.ll
new file mode 100644
index 0000000000000..7de43dab6e480
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-extracts.ll
@@ -0,0 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -passes=slp-vectorizer -S -mtriple=riscv64 --mattr=+v,+zvl256b -slp-threshold=-7 < %s | FileCheck %s
+
+define void @splat_trim(ptr %A, ptr %C, ptr %D, ptr %F, ptr %S, ptr %E, ptr %B) {
+; CHECK-LABEL: define void @splat_trim(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], ptr [[F:%.*]], ptr [[S:%.*]], ptr [[E:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[A0:%.*]] = load i64, ptr [[A]], align 8
+; CHECK-NEXT: [[B0:%.*]] = load i64, ptr [[B]], align 8
+; CHECK-NEXT: [[C0:%.*]] = load i64, ptr [[C]], align 8
+; CHECK-NEXT: [[D0:%.*]] = load i64, ptr [[D]], align 8
+; CHECK-NEXT: [[E0:%.*]] = load i64, ptr [[E]], align 8
+; CHECK-NEXT: [[F0:%.*]] = load i64, ptr [[F]], align 8
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B0]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i64> splat (i64 1), [[TMP1]]
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP2]], i64 1
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> poison, i64 [[E0]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[B0]], i64 1
+; CHECK-NEXT: [[TMP6:%.*]] = add <2 x i64> splat (i64 1), [[TMP5]]
+; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 0>
+; CHECK-NEXT: [[AS2:%.*]] = add i64 [[TMP8]], [[TMP7]]
+; CHECK-NEXT: [[AS3:%.*]] = sub i64 [[TMP8]], [[TMP7]]
+; CHECK-NEXT: [[SH2:%.*]] = lshr i64 [[AS2]], [[E0]]
+; CHECK-NEXT: [[SH3:%.*]] = shl i64 [[AS3]], [[F0]]
+; CHECK-NEXT: [[AS13:%.*]] = sub i64 [[SH2]], [[E0]]
+; CHECK-NEXT: [[AS12:%.*]] = add i64 [[SH3]], [[F0]]
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <2 x i64> poison, i64 [[TMP8]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i64> [[TMP23]], <2 x i64> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP24:%.*]] = insertelement <2 x i64> poison, i64 [[TMP7]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[TMP24]], <2 x i64> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[TMP9]], [[TMP10]]
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i64> poison, i64 [[C0]], i64 0
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i64> [[TMP12]], i64 [[D0]], i64 1
+; CHECK-NEXT: [[TMP14:%.*]] = shl <2 x i64> [[TMP11]], [[TMP13]]
+; CHECK-NEXT: [[TMP15:%.*]] = lshr <2 x i64> [[TMP11]], [[TMP13]]
+; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x i64> [[TMP14]], <2 x i64> [[TMP15]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT: [[TMP17:%.*]] = add <2 x i64> [[TMP16]], [[TMP13]]
+; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <2 x i64> [[TMP17]], <2 x i64> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i64> [[TMP18]], i64 [[AS12]], i64 2
+; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i64> [[TMP19]], i64 [[AS13]], i64 3
+; CHECK-NEXT: [[TMP21:%.*]] = add <4 x i64> [[TMP20]], splat (i64 1)
+; CHECK-NEXT: [[TMP22:%.*]] = add <4 x i64> [[TMP21]], [[TMP3]]
+; CHECK-NEXT: store <4 x i64> [[TMP22]], ptr [[S]], align 8
+; CHECK-NEXT: ret void
+;
+entry:
+ %A0 = load i64, ptr %A, align 8
+ %B0 = load i64, ptr %B, align 8
+ %C0 = load i64, ptr %C, align 8
+ %D0 = load i64, ptr %D, align 8
+ %E0 = load i64, ptr %E, align 8
+ %F0 = load i64, ptr %F, align 8
+
+ %v1 = add i64 1, %A0
+ %v2 = add i64 1, %B0
+ %v3 = add i64 1, %E0
+
+ %AS0 = add i64 %v1, %v2
+ %AS1 = add i64 %v1, %v2
+ %AS2 = add i64 %v1, %v2
+ %AS3 = sub i64 %v1, %v2
+
+ %Sh0 = shl i64 %AS0, %C0
+ %Sh1 = lshr i64 %AS1, %D0
+ %Sh2 = lshr i64 %AS2, %E0
+ %Sh3 = shl i64 %AS3, %F0
+
+ %AS10 = add i64 %Sh0, %C0
+ %AS11 = add i64 %Sh1, %D0
+ %AS12 = add i64 %Sh3, %F0
+ %AS13 = sub i64 %Sh2, %E0
+
+ %AS20 = add i64 %AS10, 1
+ %AS21 = add i64 %AS11, 1
+ %AS22 = add i64 %AS12, 1
+ %AS23 = add i64 %AS13, 1
+
+ %Add0 = add i64 %AS20, %v3
+ %Add1 = add i64 %AS21, %v2
+ %Add2 = add i64 %AS22, %v3
+ %Add3 = add i64 %AS23, %v3
+
+ %idxS1 = getelementptr inbounds i64, ptr %S, i64 1
+ %idxS2 = getelementptr inbounds i64, ptr %S, i64 2
+ %idxS3 = getelementptr inbounds i64, ptr %S, i64 3
+
+ store i64 %Add0, ptr %S, align 8
+ store i64 %Add1, ptr %idxS1, align 8
+ store i64 %Add2, ptr %idxS2, align 8
+ store i64 %Add3, ptr %idxS3, align 8
+ ret void
+}
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