[llvm] [AMDGPU] Follow up for Split OPERAND_REG_IMM_INT64 into signed and unsigned variants (PR #219755)
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llvm-commits at lists.llvm.org
Sat Aug 29 20:58:04 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Addmisol (addmisol)
<details>
<summary>Changes</summary>
followup for #<!-- -->186575
---
Patch is 193.88 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/219755.diff
35 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+13-6)
- (modified) llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (+4-2)
- (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp (+2-1)
- (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp (+23-10)
- (modified) llvm/lib/Target/AMDGPU/SIDefines.h (+2-1)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+26-6)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+2-2)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.td (+17-3)
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+26-26)
- (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.td (+4-2)
- (modified) llvm/lib/Target/AMDGPU/SOPInstructions.td (+43-25)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (+2-1)
- (modified) llvm/lib/Target/AMDGPU/VOP3Instructions.td (+39-9)
- (modified) llvm/lib/Target/AMDGPU/VOPCInstructions.td (+37-17)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll (+5-11)
- (modified) llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir (+2-10)
- (modified) llvm/test/CodeGen/AMDGPU/clmul.ll (+76-80)
- (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll (+43-69)
- (modified) llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir (+2-4)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll (+20-27)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll (+2-6)
- (modified) llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll (+7-9)
- (modified) llvm/test/CodeGen/AMDGPU/mad_64_32.ll (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/mul.ll (+45-48)
- (modified) llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll (+2-4)
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s (+1-1)
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s (+4-3)
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_vop2.s (+3-6)
- (modified) llvm/test/MC/AMDGPU/gfx12_asm_sop1.s (+31-93)
- (modified) llvm/test/MC/AMDGPU/gfx12_asm_sop2.s (+32-96)
- (modified) llvm/test/MC/AMDGPU/gfx12_asm_sopc.s (+6-6)
- (modified) llvm/test/MC/AMDGPU/gfx12_asm_vopc.s (+54-96)
- (modified) llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s (+15-24)
- (modified) llvm/test/MC/AMDGPU/literals.s (+2-4)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 9ae621fdc6b71..14b5ac3a61184 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -463,7 +463,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isSSrc_b16();
}
- bool isSSrc_b64() const {
+ bool isSSrc_u64() const {
// TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.
// See isVSrc64().
return isSCSrc_b64() || isLiteralImm(MVT::i64) ||
@@ -472,6 +472,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
isExpr());
}
+ bool isSSrc_i64() const { return isSSrc_u64(); }
+
bool isSSrc_f32() const {
return isSCSrc_b32() || isLiteralImm(MVT::f32) || isExpr();
}
@@ -598,7 +600,9 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isVCSrc_f32() || isLiteralImm(MVT::i32) || isExpr();
}
- bool isVSrc_b64() const { return isVCSrc_f64() || isLiteralImm(MVT::i64); }
+ bool isVSrc_u64() const { return isVCSrc_f64() || isLiteralImm(MVT::i64); }
+
+ bool isVSrc_i64() const { return isVSrc_u64(); }
bool isVSrc_v2b64() const {
return isRegOrInlineNoMods(AMDGPU::VS_128RegClassID, MVT::i64) ||
@@ -630,7 +634,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isVCSrc_v2b32() const { return isVCSrc_b64(); }
- bool isVSrc_v2b32() const { return isVSrc_b64() || isLiteralImm(MVT::v2i32); }
+ bool isVSrc_v2b32() const { return isVSrc_u64() || isLiteralImm(MVT::v2i32); }
bool isVSrc_f32() const {
return isVCSrc_f32() || isLiteralImm(MVT::f32) || isExpr();
@@ -2040,7 +2044,8 @@ static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {
case AMDGPU::OPERAND_KIMM32:
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
return &APFloat::IEEEsingle();
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
@@ -2363,7 +2368,8 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val,
if (Imm.IsFPImm) { // We got fp literal token
switch (OpTy) {
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
@@ -2501,7 +2507,8 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val,
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
break;
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_IMM_V2INT64:
if (Lit == LitModifier::None &&
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 45c1350c146da..173c4df17d43f 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -631,7 +631,8 @@ bool AMDGPUDisassembler::decodeImmOperands(MCInst &MI,
break;
}
case AMDGPU::OPERAND_REG_IMM_FP64:
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
@@ -1779,7 +1780,8 @@ AMDGPUDisassembler::decodeLiteralConstant(const MCInstrDesc &Desc,
if (!UseLit)
Val <<= 32;
break;
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_IMM_V2INT64:
UseLit = AMDGPU::isInlinableLiteral64(Val, HasInv2Pi);
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 2764ff2d68ce0..e6151288bcece 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -864,7 +864,8 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
printImmediate32(Op.getImm(), STI, O);
break;
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_IMM_V2INT64:
printImmediate64(Op.getImm(), STI, O, false);
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index 0fd174bcde297..bfdc6dddbe894 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -227,7 +227,8 @@ static uint32_t getLit16IntEncoding(uint32_t Val, const MCSubtargetInfo &STI) {
}
static uint32_t getLit64Encoding(const MCInstrDesc &Desc, uint64_t Val,
- const MCSubtargetInfo &STI, bool IsFP) {
+ const MCSubtargetInfo &STI, bool IsFP,
+ std::optional<bool> IsSigned = std::nullopt) {
uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
if (IntImm != 0)
return IntImm;
@@ -262,14 +263,21 @@ static uint32_t getLit64Encoding(const MCInstrDesc &Desc, uint64_t Val,
// The rest part needs to align with AMDGPUInstPrinter::printLiteral64.
- bool CanUse64BitLiterals = STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
- !SIInstrFlags::isVOP3Like(Desc);
- if (IsFP) {
- return CanUse64BitLiterals && Lo_32(Val) ? 254 : 255;
- }
-
- return CanUse64BitLiterals && (!isInt<32>(Val) || !isUInt<32>(Val)) ? 254
- : 255;
+ auto Needs64BitLiteral = [&]() {
+ if (!STI.hasFeature(AMDGPU::Feature64BitLiterals) ||
+ SIInstrFlags::isVOP3Like(Desc))
+ return false;
+ if (IsFP)
+ return Lo_32(Val) != 0;
+ // For signed operands, check if value fits in signed 32-bit range.
+ // For unsigned operands, check if value fits in unsigned 32-bit range.
+ // If signedness is unknown, conservatively require both.
+ if (IsSigned.has_value())
+ return *IsSigned ? !isInt<32>(Val) : !isUInt<32>(Val);
+ return !isInt<32>(Val) && !isUInt<32>(Val);
+ };
+
+ return Needs64BitLiteral() ? 254 : 255;
}
std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
@@ -311,7 +319,12 @@ std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ return getLit64Encoding(Desc, static_cast<uint64_t>(Imm), STI, false,
+ /*IsSigned=*/true);
+ case AMDGPU::OPERAND_REG_IMM_U64:
+ return getLit64Encoding(Desc, static_cast<uint64_t>(Imm), STI, false,
+ /*IsSigned=*/false);
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_IMM_V2INT64:
return getLit64Encoding(Desc, static_cast<uint64_t>(Imm), STI, false);
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 9f2446072bf0b..41c33bc1e2ac8 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -429,7 +429,8 @@ namespace AMDGPU {
enum OperandType : unsigned {
/// Operands with register, 32-bit, or 64-bit immediate
OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
- OPERAND_REG_IMM_INT64,
+ OPERAND_REG_IMM_I64,
+ OPERAND_REG_IMM_U64,
OPERAND_REG_IMM_INT16,
OPERAND_REG_IMM_FP32,
OPERAND_REG_IMM_FP64,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 687ca49f514f9..eb1b264b4191c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4868,7 +4868,8 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
int32_t Trunc = static_cast<int32_t>(Imm);
return AMDGPU::isInlinableLiteral32(Trunc, ST.hasInv2PiInlineImm());
}
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
@@ -5412,7 +5413,8 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
break;
}
case AMDGPU::OPERAND_REG_IMM_FP64:
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_IMM_V2INT32:
case AMDGPU::OPERAND_REG_IMM_V2FP32:
if (ST.has64BitLiterals() && Desc.getSize() != 4 && MO.isImm() &&
@@ -6747,8 +6749,9 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
uint64_t Imm = MO->getImm();
bool Is64BitFPOp = OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_FP64 ||
OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP64;
- bool Is64BitOp = Is64BitFPOp ||
- OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_INT64 ||
+ bool Is64BitSignedOp = OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_I64;
+ bool Is64BitUnsignedOp = OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_U64;
+ bool Is64BitOp = Is64BitFPOp || Is64BitSignedOp || Is64BitUnsignedOp ||
OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2INT32 ||
OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP32 ||
OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2INT64;
@@ -6758,13 +6761,23 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
(!ST.has64BitLiterals() || InstDesc.getSize() != 4))
return false;
+ // For signed 64-bit operands, the literal will be sign-extended.
+ // For unsigned 64-bit operands, the literal will be zero-extended.
+ // Check if the 32-bit encoding matches the expected 64-bit value.
+ if (Is64BitSignedOp && !isInt<32>(Imm) &&
+ (!ST.has64BitLiterals() || InstDesc.getSize() != 4))
+ return false;
+ if (Is64BitUnsignedOp && !isUInt<32>(Imm) &&
+ (!ST.has64BitLiterals() || InstDesc.getSize() != 4))
+ return false;
+
// FIXME: We can use sign extended 64-bit literals, but only for signed
// operands. At the moment we do not know if an operand is signed.
// Such operand will be encoded as its low 32 bits and then either
// correctly sign extended or incorrectly zero extended by HW.
// If 64-bit literals are supported and the literal will be encoded
// as full 64 bit we still can use it.
- if (!Is64BitFPOp && (int32_t)Imm < 0 &&
+ if (!Is64BitFPOp && !Is64BitSignedOp && !Is64BitUnsignedOp && (int32_t)Imm < 0 &&
(!ST.has64BitLiterals() || AMDGPU::isValid32BitLiteral(Imm, false)))
return false;
}
@@ -10227,7 +10240,14 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
if (!AMDGPU::isValid32BitLiteral(Op.getImm(), true))
LiteralSize = 8;
break;
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ if (!Op.isImm() || !isInt<32>(Op.getImm()))
+ LiteralSize = 8;
+ break;
+ case AMDGPU::OPERAND_REG_IMM_U64:
+ if (!Op.isImm() || !isUInt<32>(Op.getImm()))
+ LiteralSize = 8;
+ break;
case AMDGPU::OPERAND_REG_IMM_V2INT64:
// A 32-bit literal is only valid when the value fits in BOTH signed
// and unsigned 32-bit ranges [0, 2^31-1], matching the MC code
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index ab29f0d59d939..ea45c450495ac 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1342,8 +1342,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
unsigned Size = getOpSize(MI, OpIdx);
assert(Size == 8 || Size == 4);
- uint8_t OpType = (Size == 8) ?
- AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
+ uint8_t OpType = (Size == 8) ? AMDGPU::OPERAND_REG_IMM_I64
+ : AMDGPU::OPERAND_REG_IMM_INT32;
return isInlineConstant(ImmVal, OpType);
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 00e81b699be72..6ed7b90f70c59 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1926,7 +1926,7 @@ class getSDWADstForVT<ValueType VT> {
// instructions for the given VT.
class getVOPSrc0ForVT<ValueType VT, bit IsTrue16, bit IsFake16 = 1> {
RegisterOperand ret =
- !cond(!eq(VT, i64) : VSrc_b64,
+ !cond(!eq(VT, i64) : VSrc_u64,
!eq(VT, f64) : VSrc_f64,
!eq(VT, i32) : VSrc_b32,
!eq(VT, f32) : VSrc_f32,
@@ -1974,7 +1974,7 @@ class getVCSrcForVT<ValueType VT> {
}
class getSOPSrcForVT<ValueType VT> {
- RegisterOperand ret = !if(!eq(VT.Size, 64), SSrc_b64, SSrc_b32);
+ RegisterOperand ret = !if(!eq(VT.Size, 64), SSrc_u64, SSrc_b32);
}
// Returns the vreg register operand to use for source operand given VT.
@@ -2039,7 +2039,7 @@ class getVOP3SrcForVT<ValueType VT, bit IsTrue16 = 0> {
!eq(VT.Size, 192) : VRegSrc_192,
!eq(VT.Size, 128) : VRegSrc_128,
!eq(VT.Size, 96) : VRegSrc_96,
- !eq(VT.Size, 64) : VSrc_b64,
+ !eq(VT.Size, 64) : VSrc_u64,
1 : VSrc_b32);
}
@@ -3210,6 +3210,20 @@ def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
+// Signed 64-bit operand variants for arithmetic shift operations
+def VOP_I64_I64_I32_Signed : VOPProfile <[i64, i64, i32, untyped]> {
+ let Src0RC64 = VSrc_i64;
+}
+
+def VOP_I64_I32_I64_Signed : VOPProfile <[i64, i32, i64, untyped]> {
+ let Src1RC64 = VSrc_i64;
+}
+
+def VOP_I64_I64_I64_Signed : VOPProfile <[i64, i64, i64, untyped]> {
+ let Src0RC64 = VSrc_i64;
+ let Src1RC64 = VSrc_i64;
+}
+
def VOP_F16_F32_F16_F32 : VOPProfile <[f16, f32, f16, f32]>;
def VOP_F32_F32_F16_F16 : VOPProfile <[f32, f32, f16, f16]>;
def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index eb23b6fea26b3..0a00349f4b8a4 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -123,7 +123,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
// No align needed as it will be decomposed anyway
// TODO: Remove alignment requirement from sources
def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
- (ins VSrc_b64:$src0, VSrc_b64:$src1, SSrc_b64:$src2), "", []> {
+ (ins VSrc_u64:$src0, VSrc_u64:$src1, SSrc_u64:$src2), "", []> {
let isPseudo = 1;
let isCodeGenOnly = 1;
let usesCustomInserter = 1;
@@ -132,7 +132,7 @@ def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
// 64-bit vector move instruction. This is mainly used by the
// SIFoldOperands pass to enable folding of inline immediates.
def V_MOV_B64_PSEUDO : VPseudoInstSI <(outs VReg_64:$vdst),
- (ins VSrc_b64:$src0)> {
+ (ins VSrc_u64:$src0)> {
let isReMaterializable = 1;
let isAsCheapAsAMove = 1;
let isMoveImm = 1;
@@ -261,7 +261,7 @@ def S_INVERSE_BALLOT_U32 : SPseudoInstSI<
let WaveSizePredicate = isWave64 in
def S_INVERSE_BALLOT_U64 : SPseudoInstSI<
- (outs SReg_64:$sdst), (ins SSrc_b64:$mask),
+ (outs SReg_64:$sdst), (ins SSrc_u64:$mask),
[(set i1:$sdst, (int_amdgcn_inverse_ballot i64:$mask))]
>;
} // End usesCustomInserter = 1, hasSideEffects = 0
@@ -397,24 +397,24 @@ defvar Operations = [
WaveReduceOp<"or", "B32", i32, SGPR_32, VSrc_b32>,
WaveReduceOp<"xor", "B32", i32, SGPR_32, VSrc_b32>,
- WaveReduceOp<"umin", "U64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"min", "I64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"umax", "U64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"max", "I64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"add", "U64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"sub", "U64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"and", "B64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"or", "B64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"xor", "B64", i64, SGPR_64, VSrc_b64>,
+ WaveReduceOp<"umin", "U64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"min", "I64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"umax", "U64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"max", "I64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"add", "U64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"sub", "U64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"and", "B64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"or", "B64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"xor", "B64", i64, SGPR_64, VSrc_u64>,
WaveReduceOp<"fmin", "F32", f32, SGPR_32, VSrc_b32>,
- WaveReduceOp<"fmin", "F64", f64, SGPR_64, VSrc_b64>,
+ WaveReduceOp<"fmin", "F64", f64, SGPR_64, VSrc_u64>,
WaveReduceOp<"fmax", "F32", f32, SGPR_32, VSrc_b32>,
- WaveReduceOp<"fmax", "F64", f64, SGPR_64, VSrc_b64>,
+ WaveReduceOp<"fmax", "F64", f64, SGPR_64, VSrc_u64>,
WaveReduceOp<"fadd", "F32", f32, SGPR_32, VSrc_b32>,
- WaveReduceOp<"fadd", "F64", f64, SGPR_64, VSrc_b64>,
+ WaveReduceOp<"fadd", "F64", f64, SGPR_64, VSrc_u64>,
WaveReduceOp<"fsub", "F32", f32, SGPR_32, VSrc_b32>,
- WaveReduceOp<"fsub", "F64", f64, SGPR_64, VSrc_b64>,
+ WaveReduceOp<"fsub", "F64", f64, SGPR_64, VSrc_u64>,
];
foreach Op = Operations in {
@@ -424,24 +424,24 @@ foreach Op = Operations in {
let usesCustomInserter = 1, Defs = [VCC] in {
def V_ADD_U64_PSEUDO : VPseudoInstSI <
- (outs VReg_64_AlignTarget:$vdst), (ins VSrc_b64:$src0, VSrc_b64:$src1),
+ (outs VReg_64_AlignTarget:$vdst), (ins VSrc_u64:$src0, VSrc_u64:$src1),
[(set VReg_64_AlignTarget:$vdst, (DivergentBinFrag<add> i64:$src0, i64:$src1))]
>;
def V_SUB_U64_PSEUDO : VPseudoInstSI <
- (outs VReg_64_AlignTarget:$vdst), (ins VSrc_b64:$src0, VSrc_b64:$src1),
+ (outs VReg_64_AlignTarget:$vdst), (ins VSrc_u64:$src0, VSrc_u64:$src1),
[(set VReg_64_AlignTarget:$vdst, (DivergentBinFrag<sub> i64:$src0, i64:$src1))]
>;
} // End usesCustomInserter = 1, Defs = [VCC]
let usesCustomInserter = 1, Defs = [SCC] in {
def S_ADD_U64_PSEUDO : SPseudoInstSI <
- (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),
+ (outs SReg_64:$sdst), (ins SSrc_u64:$src0, SSrc_u64:$src1),
[(set SReg_64:$sdst, (UniformBinFrag<add> i64:$src0, i64:$src1))]
>;
def S_SUB_U64_PSEUDO : SPseudoInstSI <
- (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),
+ (outs SReg_64:$sdst), (ins SSrc_u64:$src0, SSrc_u64:$src1),
[(set SReg_64:$sdst, (UniformBinFrag<sub> i64:$src0, i64:$src1))]
>;
@@ -836,7 +836,7 @@ def SI_RETURN : SPseudoInstSI <
// This version is only needed so we can fill in the output register
// in the custom inserter.
def SI_CALL_ISEL : SPseudoInstSI <
- (outs), (ins SSrc_b64:$src0, unknown:$callee),
+ (outs), (ins SSrc_u64:$src0, unknown:$callee),
[(AMDGPUcall i64:$src0, tglobaladdr:$callee)]> {
let Size = 4;
let isCall = 1;
@@ -865,7 +865,7 @@ def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:
// Wrapper around s_swappc_b64 with extra $callee parameter to track
// the called function after regalloc.
def SI_CALL : SPseudoInstSI <
- (outs SReg_64:$dst), (ins SSrc_b64:$src0, unknown:$callee)> {
+ (outs SReg_64:$dst), (ins SSrc_u64:$src0, unknown:$callee)> {
let Size = 4;
let FixedSize = 1;
let isCall = 1;
@@ -1089,7 +1089,7 @@ class ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/219755
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