[llvm] [AMDGPU] Split OPERAND_REG_IMM_INT64 into signed and unsigned variants (PR #186575)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 29 20:03:34 PDT 2026
https://github.com/addmisol updated https://github.com/llvm/llvm-project/pull/186575
>From dc93a8fc88d8752489cfdf3e1883aba4a50727fb Mon Sep 17 00:00:00 2001
From: addmisol <addmisol9 at gmail.com>
Date: Sat, 29 Aug 2026 20:10:18 +0530
Subject: [PATCH 1/5] Fix : resolve conflicts
Signed-off-by: addmisol <addmisol9 at gmail.com>
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 19 ++-
.../Disassembler/AMDGPUDisassembler.cpp | 6 +-
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 3 +-
.../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 3 +-
llvm/lib/Target/AMDGPU/SIDefines.h | 3 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 32 +++-
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 4 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 20 ++-
llvm/lib/Target/AMDGPU/SIInstructions.td | 52 +++---
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 6 +-
llvm/lib/Target/AMDGPU/SOPInstructions.td | 30 ++--
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 3 +-
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 44 ++++-
llvm/lib/Target/AMDGPU/VOPCInstructions.td | 12 ++
.../branch-relaxation-inst-size-gfx1250.mir | 12 +-
llvm/test/CodeGen/AMDGPU/clmul.ll | 156 +++++++++---------
.../test/CodeGen/AMDGPU/flat-saddr-atomics.ll | 112 +++++--------
.../AMDGPU/fold-short-64-bit-literals.mir | 3 +-
.../CodeGen/AMDGPU/folding-of-i32-as-i64.mir | 9 +-
.../CodeGen/AMDGPU/global-atomicrmw-fadd.ll | 47 +++---
llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll | 8 +-
.../test/CodeGen/AMDGPU/loop-prefetch-data.ll | 16 +-
llvm/test/CodeGen/AMDGPU/mad_64_32.ll | 3 +-
llvm/test/CodeGen/AMDGPU/mul.ll | 93 +++++------
.../promote-constOffset-to-imm-gfx12.ll | 6 +-
25 files changed, 366 insertions(+), 336 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 9ae621fdc6b71..14b5ac3a61184 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -463,7 +463,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isSSrc_b16();
}
- bool isSSrc_b64() const {
+ bool isSSrc_u64() const {
// TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.
// See isVSrc64().
return isSCSrc_b64() || isLiteralImm(MVT::i64) ||
@@ -472,6 +472,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
isExpr());
}
+ bool isSSrc_i64() const { return isSSrc_u64(); }
+
bool isSSrc_f32() const {
return isSCSrc_b32() || isLiteralImm(MVT::f32) || isExpr();
}
@@ -598,7 +600,9 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isVCSrc_f32() || isLiteralImm(MVT::i32) || isExpr();
}
- bool isVSrc_b64() const { return isVCSrc_f64() || isLiteralImm(MVT::i64); }
+ bool isVSrc_u64() const { return isVCSrc_f64() || isLiteralImm(MVT::i64); }
+
+ bool isVSrc_i64() const { return isVSrc_u64(); }
bool isVSrc_v2b64() const {
return isRegOrInlineNoMods(AMDGPU::VS_128RegClassID, MVT::i64) ||
@@ -630,7 +634,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isVCSrc_v2b32() const { return isVCSrc_b64(); }
- bool isVSrc_v2b32() const { return isVSrc_b64() || isLiteralImm(MVT::v2i32); }
+ bool isVSrc_v2b32() const { return isVSrc_u64() || isLiteralImm(MVT::v2i32); }
bool isVSrc_f32() const {
return isVCSrc_f32() || isLiteralImm(MVT::f32) || isExpr();
@@ -2040,7 +2044,8 @@ static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {
case AMDGPU::OPERAND_KIMM32:
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
return &APFloat::IEEEsingle();
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
@@ -2363,7 +2368,8 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val,
if (Imm.IsFPImm) { // We got fp literal token
switch (OpTy) {
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
@@ -2501,7 +2507,8 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val,
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
break;
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_IMM_V2INT64:
if (Lit == LitModifier::None &&
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 45c1350c146da..173c4df17d43f 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -631,7 +631,8 @@ bool AMDGPUDisassembler::decodeImmOperands(MCInst &MI,
break;
}
case AMDGPU::OPERAND_REG_IMM_FP64:
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
@@ -1779,7 +1780,8 @@ AMDGPUDisassembler::decodeLiteralConstant(const MCInstrDesc &Desc,
if (!UseLit)
Val <<= 32;
break;
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_IMM_V2INT64:
UseLit = AMDGPU::isInlinableLiteral64(Val, HasInv2Pi);
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 2764ff2d68ce0..e6151288bcece 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -864,7 +864,8 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
printImmediate32(Op.getImm(), STI, O);
break;
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_IMM_V2INT64:
printImmediate64(Op.getImm(), STI, O, false);
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index 0fd174bcde297..dff92b2a57360 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -311,7 +311,8 @@ std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_IMM_V2INT64:
return getLit64Encoding(Desc, static_cast<uint64_t>(Imm), STI, false);
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 9f2446072bf0b..41c33bc1e2ac8 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -429,7 +429,8 @@ namespace AMDGPU {
enum OperandType : unsigned {
/// Operands with register, 32-bit, or 64-bit immediate
OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
- OPERAND_REG_IMM_INT64,
+ OPERAND_REG_IMM_I64,
+ OPERAND_REG_IMM_U64,
OPERAND_REG_IMM_INT16,
OPERAND_REG_IMM_FP32,
OPERAND_REG_IMM_FP64,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 687ca49f514f9..eb1b264b4191c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4868,7 +4868,8 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
int32_t Trunc = static_cast<int32_t>(Imm);
return AMDGPU::isInlinableLiteral32(Trunc, ST.hasInv2PiInlineImm());
}
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
@@ -5412,7 +5413,8 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
break;
}
case AMDGPU::OPERAND_REG_IMM_FP64:
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_IMM_V2INT32:
case AMDGPU::OPERAND_REG_IMM_V2FP32:
if (ST.has64BitLiterals() && Desc.getSize() != 4 && MO.isImm() &&
@@ -6747,8 +6749,9 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
uint64_t Imm = MO->getImm();
bool Is64BitFPOp = OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_FP64 ||
OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP64;
- bool Is64BitOp = Is64BitFPOp ||
- OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_INT64 ||
+ bool Is64BitSignedOp = OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_I64;
+ bool Is64BitUnsignedOp = OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_U64;
+ bool Is64BitOp = Is64BitFPOp || Is64BitSignedOp || Is64BitUnsignedOp ||
OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2INT32 ||
OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP32 ||
OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2INT64;
@@ -6758,13 +6761,23 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
(!ST.has64BitLiterals() || InstDesc.getSize() != 4))
return false;
+ // For signed 64-bit operands, the literal will be sign-extended.
+ // For unsigned 64-bit operands, the literal will be zero-extended.
+ // Check if the 32-bit encoding matches the expected 64-bit value.
+ if (Is64BitSignedOp && !isInt<32>(Imm) &&
+ (!ST.has64BitLiterals() || InstDesc.getSize() != 4))
+ return false;
+ if (Is64BitUnsignedOp && !isUInt<32>(Imm) &&
+ (!ST.has64BitLiterals() || InstDesc.getSize() != 4))
+ return false;
+
// FIXME: We can use sign extended 64-bit literals, but only for signed
// operands. At the moment we do not know if an operand is signed.
// Such operand will be encoded as its low 32 bits and then either
// correctly sign extended or incorrectly zero extended by HW.
// If 64-bit literals are supported and the literal will be encoded
// as full 64 bit we still can use it.
- if (!Is64BitFPOp && (int32_t)Imm < 0 &&
+ if (!Is64BitFPOp && !Is64BitSignedOp && !Is64BitUnsignedOp && (int32_t)Imm < 0 &&
(!ST.has64BitLiterals() || AMDGPU::isValid32BitLiteral(Imm, false)))
return false;
}
@@ -10227,7 +10240,14 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
if (!AMDGPU::isValid32BitLiteral(Op.getImm(), true))
LiteralSize = 8;
break;
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ if (!Op.isImm() || !isInt<32>(Op.getImm()))
+ LiteralSize = 8;
+ break;
+ case AMDGPU::OPERAND_REG_IMM_U64:
+ if (!Op.isImm() || !isUInt<32>(Op.getImm()))
+ LiteralSize = 8;
+ break;
case AMDGPU::OPERAND_REG_IMM_V2INT64:
// A 32-bit literal is only valid when the value fits in BOTH signed
// and unsigned 32-bit ranges [0, 2^31-1], matching the MC code
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 2a608b6991b1c..2bc50fc408815 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1342,8 +1342,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
unsigned Size = getOpSize(MI, OpIdx);
assert(Size == 8 || Size == 4);
- uint8_t OpType = (Size == 8) ?
- AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
+ uint8_t OpType = (Size == 8) ? AMDGPU::OPERAND_REG_IMM_I64
+ : AMDGPU::OPERAND_REG_IMM_INT32;
return isInlineConstant(ImmVal, OpType);
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 00e81b699be72..6ed7b90f70c59 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1926,7 +1926,7 @@ class getSDWADstForVT<ValueType VT> {
// instructions for the given VT.
class getVOPSrc0ForVT<ValueType VT, bit IsTrue16, bit IsFake16 = 1> {
RegisterOperand ret =
- !cond(!eq(VT, i64) : VSrc_b64,
+ !cond(!eq(VT, i64) : VSrc_u64,
!eq(VT, f64) : VSrc_f64,
!eq(VT, i32) : VSrc_b32,
!eq(VT, f32) : VSrc_f32,
@@ -1974,7 +1974,7 @@ class getVCSrcForVT<ValueType VT> {
}
class getSOPSrcForVT<ValueType VT> {
- RegisterOperand ret = !if(!eq(VT.Size, 64), SSrc_b64, SSrc_b32);
+ RegisterOperand ret = !if(!eq(VT.Size, 64), SSrc_u64, SSrc_b32);
}
// Returns the vreg register operand to use for source operand given VT.
@@ -2039,7 +2039,7 @@ class getVOP3SrcForVT<ValueType VT, bit IsTrue16 = 0> {
!eq(VT.Size, 192) : VRegSrc_192,
!eq(VT.Size, 128) : VRegSrc_128,
!eq(VT.Size, 96) : VRegSrc_96,
- !eq(VT.Size, 64) : VSrc_b64,
+ !eq(VT.Size, 64) : VSrc_u64,
1 : VSrc_b32);
}
@@ -3210,6 +3210,20 @@ def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
+// Signed 64-bit operand variants for arithmetic shift operations
+def VOP_I64_I64_I32_Signed : VOPProfile <[i64, i64, i32, untyped]> {
+ let Src0RC64 = VSrc_i64;
+}
+
+def VOP_I64_I32_I64_Signed : VOPProfile <[i64, i32, i64, untyped]> {
+ let Src1RC64 = VSrc_i64;
+}
+
+def VOP_I64_I64_I64_Signed : VOPProfile <[i64, i64, i64, untyped]> {
+ let Src0RC64 = VSrc_i64;
+ let Src1RC64 = VSrc_i64;
+}
+
def VOP_F16_F32_F16_F32 : VOPProfile <[f16, f32, f16, f32]>;
def VOP_F32_F32_F16_F16 : VOPProfile <[f32, f32, f16, f16]>;
def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index eb23b6fea26b3..0a00349f4b8a4 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -123,7 +123,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
// No align needed as it will be decomposed anyway
// TODO: Remove alignment requirement from sources
def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
- (ins VSrc_b64:$src0, VSrc_b64:$src1, SSrc_b64:$src2), "", []> {
+ (ins VSrc_u64:$src0, VSrc_u64:$src1, SSrc_u64:$src2), "", []> {
let isPseudo = 1;
let isCodeGenOnly = 1;
let usesCustomInserter = 1;
@@ -132,7 +132,7 @@ def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
// 64-bit vector move instruction. This is mainly used by the
// SIFoldOperands pass to enable folding of inline immediates.
def V_MOV_B64_PSEUDO : VPseudoInstSI <(outs VReg_64:$vdst),
- (ins VSrc_b64:$src0)> {
+ (ins VSrc_u64:$src0)> {
let isReMaterializable = 1;
let isAsCheapAsAMove = 1;
let isMoveImm = 1;
@@ -261,7 +261,7 @@ def S_INVERSE_BALLOT_U32 : SPseudoInstSI<
let WaveSizePredicate = isWave64 in
def S_INVERSE_BALLOT_U64 : SPseudoInstSI<
- (outs SReg_64:$sdst), (ins SSrc_b64:$mask),
+ (outs SReg_64:$sdst), (ins SSrc_u64:$mask),
[(set i1:$sdst, (int_amdgcn_inverse_ballot i64:$mask))]
>;
} // End usesCustomInserter = 1, hasSideEffects = 0
@@ -397,24 +397,24 @@ defvar Operations = [
WaveReduceOp<"or", "B32", i32, SGPR_32, VSrc_b32>,
WaveReduceOp<"xor", "B32", i32, SGPR_32, VSrc_b32>,
- WaveReduceOp<"umin", "U64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"min", "I64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"umax", "U64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"max", "I64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"add", "U64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"sub", "U64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"and", "B64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"or", "B64", i64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"xor", "B64", i64, SGPR_64, VSrc_b64>,
+ WaveReduceOp<"umin", "U64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"min", "I64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"umax", "U64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"max", "I64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"add", "U64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"sub", "U64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"and", "B64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"or", "B64", i64, SGPR_64, VSrc_u64>,
+ WaveReduceOp<"xor", "B64", i64, SGPR_64, VSrc_u64>,
WaveReduceOp<"fmin", "F32", f32, SGPR_32, VSrc_b32>,
- WaveReduceOp<"fmin", "F64", f64, SGPR_64, VSrc_b64>,
+ WaveReduceOp<"fmin", "F64", f64, SGPR_64, VSrc_u64>,
WaveReduceOp<"fmax", "F32", f32, SGPR_32, VSrc_b32>,
- WaveReduceOp<"fmax", "F64", f64, SGPR_64, VSrc_b64>,
+ WaveReduceOp<"fmax", "F64", f64, SGPR_64, VSrc_u64>,
WaveReduceOp<"fadd", "F32", f32, SGPR_32, VSrc_b32>,
- WaveReduceOp<"fadd", "F64", f64, SGPR_64, VSrc_b64>,
+ WaveReduceOp<"fadd", "F64", f64, SGPR_64, VSrc_u64>,
WaveReduceOp<"fsub", "F32", f32, SGPR_32, VSrc_b32>,
- WaveReduceOp<"fsub", "F64", f64, SGPR_64, VSrc_b64>,
+ WaveReduceOp<"fsub", "F64", f64, SGPR_64, VSrc_u64>,
];
foreach Op = Operations in {
@@ -424,24 +424,24 @@ foreach Op = Operations in {
let usesCustomInserter = 1, Defs = [VCC] in {
def V_ADD_U64_PSEUDO : VPseudoInstSI <
- (outs VReg_64_AlignTarget:$vdst), (ins VSrc_b64:$src0, VSrc_b64:$src1),
+ (outs VReg_64_AlignTarget:$vdst), (ins VSrc_u64:$src0, VSrc_u64:$src1),
[(set VReg_64_AlignTarget:$vdst, (DivergentBinFrag<add> i64:$src0, i64:$src1))]
>;
def V_SUB_U64_PSEUDO : VPseudoInstSI <
- (outs VReg_64_AlignTarget:$vdst), (ins VSrc_b64:$src0, VSrc_b64:$src1),
+ (outs VReg_64_AlignTarget:$vdst), (ins VSrc_u64:$src0, VSrc_u64:$src1),
[(set VReg_64_AlignTarget:$vdst, (DivergentBinFrag<sub> i64:$src0, i64:$src1))]
>;
} // End usesCustomInserter = 1, Defs = [VCC]
let usesCustomInserter = 1, Defs = [SCC] in {
def S_ADD_U64_PSEUDO : SPseudoInstSI <
- (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),
+ (outs SReg_64:$sdst), (ins SSrc_u64:$src0, SSrc_u64:$src1),
[(set SReg_64:$sdst, (UniformBinFrag<add> i64:$src0, i64:$src1))]
>;
def S_SUB_U64_PSEUDO : SPseudoInstSI <
- (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),
+ (outs SReg_64:$sdst), (ins SSrc_u64:$src0, SSrc_u64:$src1),
[(set SReg_64:$sdst, (UniformBinFrag<sub> i64:$src0, i64:$src1))]
>;
@@ -836,7 +836,7 @@ def SI_RETURN : SPseudoInstSI <
// This version is only needed so we can fill in the output register
// in the custom inserter.
def SI_CALL_ISEL : SPseudoInstSI <
- (outs), (ins SSrc_b64:$src0, unknown:$callee),
+ (outs), (ins SSrc_u64:$src0, unknown:$callee),
[(AMDGPUcall i64:$src0, tglobaladdr:$callee)]> {
let Size = 4;
let isCall = 1;
@@ -865,7 +865,7 @@ def : GCNPat<(UniformTernaryFrag<fshr> i32:$src0, i32:$src1, (i32 ShiftAmt32Imm:
// Wrapper around s_swappc_b64 with extra $callee parameter to track
// the called function after regalloc.
def SI_CALL : SPseudoInstSI <
- (outs SReg_64:$dst), (ins SSrc_b64:$src0, unknown:$callee)> {
+ (outs SReg_64:$dst), (ins SSrc_u64:$src0, unknown:$callee)> {
let Size = 4;
let FixedSize = 1;
let isCall = 1;
@@ -1089,7 +1089,7 @@ class S_INDIRECT_REG_WRITE_MOVREL_pseudo<RegisterClass rc,
class S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<RegisterClass rc> :
S_INDIRECT_REG_WRITE_MOVREL_pseudo<rc, SSrc_b32>;
class S_INDIRECT_REG_WRITE_MOVREL_B64_pseudo<RegisterClass rc> :
- S_INDIRECT_REG_WRITE_MOVREL_pseudo<rc, SSrc_b64>;
+ S_INDIRECT_REG_WRITE_MOVREL_pseudo<rc, SSrc_u64>;
def V_INDIRECT_REG_WRITE_MOVREL_B32_V1 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<VGPR_32>;
def V_INDIRECT_REG_WRITE_MOVREL_B32_V2 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<VReg_64>;
@@ -4687,13 +4687,13 @@ def fpimm_neg_pow2_prefer_ldexp_f64 : FPImmLeaf<f64, [{
def : GCNPat<
(any_fmul (f64 (VOP3Mods f64:$src0, i32:$src0_mods)),
fpimm_pos_pow2_prefer_ldexp_f64:$src1),
- (V_LDEXP_F64_e64 i32:$src0_mods, VSrc_b64:$src0,
+ (V_LDEXP_F64_e64 i32:$src0_mods, VSrc_u64:$src0,
0, (S_MOV_B32 (i32 (FPPow2ToExponentXForm $src1))))
>;
def : GCNPat<
(any_fmul f64:$src0, fpimm_neg_pow2_prefer_ldexp_f64:$src1),
- (V_LDEXP_F64_e64 SRCMODS.NEG, VSrc_b64:$src0,
+ (V_LDEXP_F64_e64 SRCMODS.NEG, VSrc_u64:$src0,
0, (S_MOV_B32 (i32 (FPPow2ToExponentXForm $src1))))
>;
@@ -4703,7 +4703,7 @@ def : GCNPat<
// for a second operand.
def : GCNPat<
(any_fmul (fabs f64:$src0), fpimm_neg_pow2_prefer_ldexp_f64:$src1),
- (V_LDEXP_F64_e64 SRCMODS.NEG_ABS, VSrc_b64:$src0,
+ (V_LDEXP_F64_e64 SRCMODS.NEG_ABS, VSrc_u64:$src0,
0, (S_MOV_B32 (i32 (FPPow2ToExponentXForm $src1))))
>;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index a410ffedc784d..78df38af8fca5 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1397,7 +1397,8 @@ def SSrc_bf16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_BF16">;
def SSrc_f16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_FP16">;
def SSrc_b32 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_INT32">;
def SSrc_f32 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_FP32">;
-def SSrc_b64 : SrcRegOrImm9 <SReg_64_Encodable, "OPERAND_REG_IMM_INT64">;
+def SSrc_u64 : SrcRegOrImm9 <SReg_64_Encodable, "OPERAND_REG_IMM_U64">;
+def SSrc_i64 : SrcRegOrImm9 <SReg_64_Encodable, "OPERAND_REG_IMM_I64">;
def SSrcOrLds_b32 : SrcRegOrImm9 <SRegOrLds_32, "OPERAND_REG_IMM_INT32">;
@@ -1440,7 +1441,8 @@ def VSrc_f32 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_FP32">;
def VSrc_v2b16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_V2INT16">;
def VSrc_v2bf16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_V2BF16">;
def VSrc_v2f16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_V2FP16">;
-def VSrc_b64 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_IMM_INT64">;
+def VSrc_u64 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_IMM_U64">;
+def VSrc_i64 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_IMM_I64">;
def VSrc_f64 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_IMM_FP64"> {
let DecoderMethod = "decodeOperand_VSrc_f64";
}
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 2c5a2b1f7d0d7..8962a42601909 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -106,7 +106,7 @@ class SOP1_32_movreld <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
// Special case for movreld where sdst is treated as a use operand.
class SOP1_64_movreld <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
- opName, (outs), (ins SReg_64:$sdst, SSrc_b64:$src0),
+ opName, (outs), (ins SReg_64:$sdst, SSrc_u64:$src0),
"$sdst, $src0", pattern
>;
@@ -117,7 +117,7 @@ class SOP1_0_32R <string opName, list<dag> pattern = []> : SOP1_Pseudo <
}
class SOP1_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
- opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0),
+ opName, (outs SReg_64:$sdst), (ins SSrc_u64:$src0),
"$sdst, $src0", pattern
>;
@@ -129,7 +129,7 @@ class SOP1_64R <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
// 64-bit input, 32-bit output.
class SOP1_32_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
- opName, (outs SReg_32:$sdst), (ins SSrc_b64:$src0),
+ opName, (outs SReg_32:$sdst), (ins SSrc_u64:$src0),
"$sdst, $src0", pattern
>;
@@ -155,7 +155,7 @@ class SOP1_1 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
}
class SOP1_1_REGIMM64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
- opName, (outs), (ins SSrc_b64:$src0), "$src0", pattern> {
+ opName, (outs), (ins SSrc_u64:$src0), "$src0", pattern> {
let has_sdst = 0;
}
@@ -250,7 +250,7 @@ def : GCNPat <
let WaveSizePredicate = isWave64 in {
def : GCNPat <
(int_amdgcn_wqm_vote i1:$src0),
- (S_WQM_B64 SSrc_b64:$src0)
+ (S_WQM_B64 SSrc_u64:$src0)
>;
}
@@ -660,12 +660,12 @@ class SOP2_F32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
>;
class SOP2_64 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
- opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),
+ opName, (outs SReg_64:$sdst), (ins SSrc_u64:$src0, SSrc_u64:$src1),
"$sdst, $src0, $src1", pattern
>;
class SOP2_64_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
- opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b32:$src1),
+ opName, (outs SReg_64:$sdst), (ins SSrc_u64:$src0, SSrc_b32:$src1),
"$sdst, $src0, $src1", pattern
>;
@@ -742,12 +742,12 @@ let SubtargetPredicate = isGFX12Plus in {
// The higher 32-bits of the inputs contain the sign extension bits.
let hasSideEffects = 0 in {
def S_MUL_I64_I32_PSEUDO : SPseudoInstSI <
- (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)
+ (outs SReg_64:$sdst), (ins SSrc_u64:$src0, SSrc_u64:$src1)
>;
// The higher 32-bits of the inputs are zero.
def S_MUL_U64_U32_PSEUDO : SPseudoInstSI <
- (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)
+ (outs SReg_64:$sdst), (ins SSrc_u64:$src0, SSrc_u64:$src1)
>;
}
@@ -836,19 +836,19 @@ def S_LSHL_B32 : SOP2_32 <"s_lshl_b32",
[(set SReg_32:$sdst, (UniformBinFrag<cshl_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
>;
def S_LSHL_B64 : SOP2_64_32 <"s_lshl_b64",
- [(set SReg_64:$sdst, (UniformBinFrag<cshl_64> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
+ [(set SReg_64:$sdst, (UniformBinFrag<cshl_64> (i64 SSrc_u64:$src0), (i32 SSrc_b32:$src1)))]
>;
def S_LSHR_B32 : SOP2_32 <"s_lshr_b32",
[(set SReg_32:$sdst, (UniformBinFrag<csrl_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
>;
def S_LSHR_B64 : SOP2_64_32 <"s_lshr_b64",
- [(set SReg_64:$sdst, (UniformBinFrag<csrl_64> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
+ [(set SReg_64:$sdst, (UniformBinFrag<csrl_64> (i64 SSrc_u64:$src0), (i32 SSrc_b32:$src1)))]
>;
def S_ASHR_I32 : SOP2_32 <"s_ashr_i32",
[(set SReg_32:$sdst, (UniformBinFrag<csra_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
>;
def S_ASHR_I64 : SOP2_64_32 <"s_ashr_i64",
- [(set SReg_64:$sdst, (UniformBinFrag<csra_64> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
+ [(set SReg_64:$sdst, (UniformBinFrag<csra_64> (i64 SSrc_u64:$src0), (i32 SSrc_b32:$src1)))]
>;
} // End Defs = [SCC]
@@ -887,7 +887,7 @@ def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32",
let SubtargetPredicate = isGFX8GFX9 in {
def S_RFE_RESTORE_B64 : SOP2_Pseudo <
"s_rfe_restore_b64", (outs),
- (ins SSrc_b64:$src0, SSrc_b32:$src1),
+ (ins SSrc_u64:$src0, SSrc_b32:$src1),
"$src0, $src1"
> {
let hasSideEffects = 1;
@@ -1380,7 +1380,7 @@ class SOPC_CMP_F16<string opName,
class SOPC_CMP_64<string opName,
SDPatternOperator cond = COND_NULL, string revOp = opName>
- : SOPC_Helper<SSrc_b64, i64, opName, cond>,
+ : SOPC_Helper<SSrc_u64, i64, opName, cond>,
Commutable_REV<revOp, !eq(revOp, opName)> {
let isCompare = 1;
let isCommutable = 1;
@@ -1390,7 +1390,7 @@ class SOPC_32<string opName, list<dag> pattern = []>
: SOPC_Base<SSrc_b32, SSrc_b32, opName, pattern>;
class SOPC_64_32<string opName, list<dag> pattern = []>
- : SOPC_Base<SSrc_b64, SSrc_b32, opName, pattern>;
+ : SOPC_Base<SSrc_u64, SSrc_b32, opName, pattern>;
def S_CMP_EQ_I32 : SOPC_CMP_32 <"s_cmp_eq_i32">;
def S_CMP_LG_I32 : SOPC_CMP_32 <"s_cmp_lg_i32">;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index d429584b00999..cc79fc66172c0 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -1591,7 +1591,8 @@ inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
return 4;
- case AMDGPU::OPERAND_REG_IMM_INT64:
+ case AMDGPU::OPERAND_REG_IMM_I64:
+ case AMDGPU::OPERAND_REG_IMM_U64:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 05f47f696393b..d5fc82a3227ac 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -50,6 +50,16 @@ def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {
let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
}
+// Signed variant for V_MAD_I64_I32 - src2 uses signed 64-bit operand
+def VOP3b_I64_I1_I32_I32_I64_Signed : VOPProfile<[i64, i32, i32, i64]> {
+ let HasClamp = 1;
+
+ let IsSingle = 1;
+ let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
+ let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
+ let Src2RC64 = VSrc_i64;
+}
+
let HasExt64BitDPP = 1 in {
def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32>;
def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
@@ -71,6 +81,20 @@ def VOP3b_I64_I1_I32_I32_I64_DPP : VOPProfile<[i64, i32, i32, i64]> {
let AsmVOP3DPP8 = getAsmVOP3DPP8<Asm64>.ret;
}
+// Signed DPP variant for V_MAD_I64_I32 - src2 uses signed 64-bit operand
+def VOP3b_I64_I1_I32_I32_I64_Signed_DPP : VOPProfile<[i64, i32, i32, i64]> {
+ let HasClamp = 1;
+
+ let IsSingle = 1;
+ let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
+ let OutsVOP3DPP = Outs64;
+ let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
+ let AsmVOP3DPP = getAsmVOP3DPP<Asm64>.ret;
+ let AsmVOP3DPP16 = getAsmVOP3DPP16<Asm64>.ret;
+ let AsmVOP3DPP8 = getAsmVOP3DPP8<Asm64>.ret;
+ let Src2RC64 = VSrc_i64;
+}
+
class V_MUL_PROF<VOPProfile P> : VOP3_Profile<P> {
let HasExtVOP3DPP = 0;
let HasExtDPP = 0;
@@ -84,9 +108,15 @@ def V_MAD_U32_PROF: VOP3_Profile<VOP_I32_I32_I32_I32> {
let HasExt64BitDPP = 1;
}
def VOP_I64_I64_I64_DPP : VOP3_Profile<VOP_I64_I64_I64>;
+def VOP_I64_I64_I64_Signed_DPP : VOP3_Profile<VOP_I64_I64_I64_Signed>;
def VOP_I32_I32_I64_DPP : VOP3_Profile<VOPProfile<[i64, i32, i32, i64]>> {
let HasClamp = 1;
}
+// Signed variant for V_MAD_NC_I64_I32 - src2 uses signed 64-bit operand
+def VOP_I32_I32_I64_Signed_DPP : VOP3_Profile<VOPProfile<[i64, i32, i32, i64]>> {
+ let HasClamp = 1;
+ let Src2RC64 = VSrc_i64;
+}
} // End HasExt64BitDPP = 1;
//===----------------------------------------------------------------------===//
@@ -193,7 +223,7 @@ let SchedRW = [WriteIntMul] in {
defm V_MAD_U32 : VOP3Inst <"v_mad_u32", V_MAD_U32_PROF>;
let SubtargetPredicate = HasMadNC64_32Insts in {
defm V_MAD_NC_U64_U32 : VOP3Inst<"v_mad_nc_u64_u32", VOP_I32_I32_I64_DPP>;
- defm V_MAD_NC_I64_I32 : VOP3Inst<"v_mad_nc_i64_i32", VOP_I32_I32_I64_DPP>;
+ defm V_MAD_NC_I64_I32 : VOP3Inst<"v_mad_nc_i64_i32", VOP_I32_I32_I64_Signed_DPP>;
}
}
@@ -233,9 +263,9 @@ defm V_MAXIMUM_F64 : VOP3Inst <"v_maximum_f64", VOP3_Profile<VOP_F64_F64_F64>, f
} // End SubtargetPredicate = HasIEEEMinimumMaximumInsts, ReadsModeReg = 0, AddedComplexity = 1
let SubtargetPredicate = HasMinMaxI64Insts, SchedRW = [WriteDoubleAdd] in {
-defm V_MAX_I64 : VOP3Inst <"v_max_i64", VOP_I64_I64_I64_DPP, smax>;
+defm V_MAX_I64 : VOP3Inst <"v_max_i64", VOP_I64_I64_I64_Signed_DPP, smax>;
defm V_MAX_U64 : VOP3Inst <"v_max_u64", VOP_I64_I64_I64_DPP, umax>;
-defm V_MIN_I64 : VOP3Inst <"v_min_i64", VOP_I64_I64_I64_DPP, smin>;
+defm V_MIN_I64 : VOP3Inst <"v_min_i64", VOP_I64_I64_I64_Signed_DPP, smin>;
defm V_MIN_U64 : VOP3Inst <"v_min_u64", VOP_I64_I64_I64_DPP, umin>;
} // End SubtargetPredicate = HasMinMaxI64Insts, SchedRW = [WriteDoubleAdd]
@@ -434,12 +464,12 @@ let SubtargetPredicate = HasMqsadInsts in
let isCommutable = 1, SchedRW = [WriteIntMul, WriteSALUDummy] in {
let SubtargetPredicate = isGFX7Plus in {
defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64_DPP, null_frag, [NotHasMADIntraFwdBug]>;
- defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64_DPP, null_frag, [NotHasMADIntraFwdBug]>;
+ defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64_Signed_DPP, null_frag, [NotHasMADIntraFwdBug]>;
}
let SubtargetPredicate = isGFX11Only, OtherPredicates = [HasMADIntraFwdBug],
Constraints = "@earlyclobber $vdst" in {
defm V_MAD_U64_U32_gfx11 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
- defm V_MAD_I64_I32_gfx11 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
+ defm V_MAD_I64_I32_gfx11 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64_Signed>;
}
} // End isCommutable = 1, SchedRW = [WriteIntMul, WriteSALU]
@@ -983,13 +1013,13 @@ def : GCNPat<
let SubtargetPredicate = HasLshlAddU64Inst in {
def : GCNPat<
(ThreeOpFrag<shl_0_to_4, add> i64:$src0, i32:$src1, i64:$src2),
- (V_LSHL_ADD_U64_e64 VSrc_b64:$src0, VSrc_b32:$src1, VSrc_b64:$src2)
+ (V_LSHL_ADD_U64_e64 VSrc_u64:$src0, VSrc_b32:$src1, VSrc_u64:$src2)
>;
def : GCNPat <
// (ptradd z, (shl x, y)) or (ptradd (shl x, y), z) -> ((x << y) + z)
(ThreeOpFrag<shl_0_to_4, ptradd_commutative> i64:$src0, i32:$src1, i64:$src2),
- (V_LSHL_ADD_U64_e64 VSrc_b64:$src0, VSrc_b32:$src1, VSrc_b64:$src2)>;
+ (V_LSHL_ADD_U64_e64 VSrc_u64:$src0, VSrc_b32:$src1, VSrc_u64:$src2)>;
} // End SubtargetPredicate = HasLshlAddU64Inst
let SubtargetPredicate = HasAddMinMaxInsts in {
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index aae00bdcb03f2..fb05aad39d975 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -492,6 +492,12 @@ defm VOPC_I1_I16_I16 : VOPC_Profile_t16<[Write32Bit], i16>;
def VOPC_I1_I32_I32 : VOPC_Profile<[Write32Bit], i32>;
def VOPC_I1_I64_I64 : VOPC_Profile<[Write64Bit], i64>;
+// Signed 64-bit operand variants for signed integer comparisons
+def VOPC_I1_I64_I64_Signed : VOPC_Profile<[Write64Bit], i64> {
+ let Src0RC64 = VSrc_i64;
+ let Src1RC64 = VSrc_i64;
+}
+
defm VOPC_F16_F16 : VOPC_NoSdst_Profile_t16<[Write32Bit], f16>;
def VOPC_F32_F32 : VOPC_NoSdst_Profile<[Write32Bit], f32>;
def VOPC_F64_F64 : VOPC_NoSdst_Profile<[Write64Bit], f64>;
@@ -499,6 +505,12 @@ defm VOPC_I16_I16 : VOPC_NoSdst_Profile_t16<[Write32Bit], i16>;
def VOPC_I32_I32 : VOPC_NoSdst_Profile<[Write32Bit], i32>;
def VOPC_I64_I64 : VOPC_NoSdst_Profile<[Write64Bit], i64>;
+// Signed 64-bit operand variant for signed integer comparisons (NoSdst)
+def VOPC_I64_I64_Signed : VOPC_NoSdst_Profile<[Write64Bit], i64> {
+ let Src0RC64 = VSrc_i64;
+ let Src1RC64 = VSrc_i64;
+}
+
multiclass VOPC_F16 <string opName, SDPatternOperator cond = COND_NULL,
string revOp = opName> {
let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in {
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir
index 503119e82b4fb..1f1de4ad86f17 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir
+++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir
@@ -30,19 +30,11 @@ machineFunctionInfo:
body: |
; CHECK-LABEL: name: s_mov_b64_64bit_literal_size
; CHECK: bb.0:
- ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: liveins: $sgpr8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S_CMP_EQ_U32 $sgpr8, 0, implicit-def $scc
- ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3:
- ; CHECK-NEXT: successors: %bb.2(0x80000000)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $sgpr4_sgpr5 = S_GETPC_B64 post-instr-symbol <mcsymbol >
- ; CHECK-NEXT: $sgpr4 = S_ADD_U32 $sgpr4, target-flags(<unknown target flag>) <mcsymbol >, implicit-def $scc
- ; CHECK-NEXT: $sgpr5 = S_ADDC_U32 $sgpr5, target-flags(<unknown target flag>) <mcsymbol >, implicit-def $scc, implicit $scc
- ; CHECK-NEXT: S_SETPC_B64 $sgpr4_sgpr5
+ ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit $scc
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
diff --git a/llvm/test/CodeGen/AMDGPU/clmul.ll b/llvm/test/CodeGen/AMDGPU/clmul.ll
index 3b04923ea0794..6a5b6d8589f1f 100644
--- a/llvm/test/CodeGen/AMDGPU/clmul.ll
+++ b/llvm/test/CodeGen/AMDGPU/clmul.ll
@@ -1773,62 +1773,60 @@ define amdgpu_kernel void @test_clmulr_i32(ptr addrspace(1) %out, ptr addrspace(
; GFX1250-NEXT: s_mov_b32 s7, 0x31016000
; GFX1250-NEXT: s_mov_b32 s10, s6
; GFX1250-NEXT: s_mov_b32 s11, s7
-; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: s_mov_b64 s[4:5], 0x88888888
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_mov_b32 s8, s2
; GFX1250-NEXT: s_mov_b32 s9, s3
; GFX1250-NEXT: s_mov_b32 s3, 0
; GFX1250-NEXT: buffer_load_b64 v[0:1], off, s[8:11], null
+; GFX1250-NEXT: s_mov_b32 s5, s3
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: s_mov_b32 s9, s3
-; GFX1250-NEXT: s_mov_b32 s13, s3
-; GFX1250-NEXT: s_mov_b32 s15, s3
; GFX1250-NEXT: s_mov_b32 s11, s3
+; GFX1250-NEXT: s_mov_b32 s13, s3
+; GFX1250-NEXT: s_mov_b32 s9, s3
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_readfirstlane_b32 s2, v1
-; GFX1250-NEXT: v_readfirstlane_b32 s10, v0
-; GFX1250-NEXT: s_and_b64 s[16:17], s[2:3], 0x11111111
-; GFX1250-NEXT: s_and_b32 s8, s10, 0x22222222
-; GFX1250-NEXT: s_and_b64 s[18:19], s[2:3], 0x22222222
-; GFX1250-NEXT: s_and_b32 s12, s10, 0x11111111
-; GFX1250-NEXT: s_and_b32 s14, s2, 0x88888888
-; GFX1250-NEXT: s_and_b64 s[20:21], s[10:11], 0x44444444
+; GFX1250-NEXT: v_readfirstlane_b32 s8, v0
+; GFX1250-NEXT: s_and_b64 s[14:15], s[2:3], 0x11111111
+; GFX1250-NEXT: s_and_b32 s4, s8, 0x22222222
+; GFX1250-NEXT: s_and_b64 s[16:17], s[2:3], 0x22222222
+; GFX1250-NEXT: s_and_b32 s10, s8, 0x11111111
+; GFX1250-NEXT: s_and_b32 s12, s2, 0x88888888
+; GFX1250-NEXT: s_and_b64 s[18:19], s[8:9], 0x44444444
; GFX1250-NEXT: s_and_b32 s2, s2, 0x44444444
-; GFX1250-NEXT: s_and_b64 s[4:5], s[10:11], s[4:5]
-; GFX1250-NEXT: s_mul_u64 s[10:11], s[8:9], s[16:17]
-; GFX1250-NEXT: s_mul_u64 s[22:23], s[12:13], s[18:19]
-; GFX1250-NEXT: s_mul_u64 s[28:29], s[8:9], s[14:15]
-; GFX1250-NEXT: s_mul_u64 s[30:31], s[12:13], s[16:17]
-; GFX1250-NEXT: s_mul_u64 s[24:25], s[20:21], s[14:15]
-; GFX1250-NEXT: s_mul_u64 s[26:27], s[4:5], s[2:3]
-; GFX1250-NEXT: s_mul_u64 s[34:35], s[20:21], s[2:3]
-; GFX1250-NEXT: s_mul_u64 s[38:39], s[8:9], s[18:19]
-; GFX1250-NEXT: s_mul_u64 s[40:41], s[12:13], s[2:3]
-; GFX1250-NEXT: s_mul_u64 s[44:45], s[4:5], s[14:15]
-; GFX1250-NEXT: s_mul_u64 s[2:3], s[8:9], s[2:3]
-; GFX1250-NEXT: s_mul_u64 s[8:9], s[12:13], s[14:15]
-; GFX1250-NEXT: s_xor_b64 s[10:11], s[22:23], s[10:11]
+; GFX1250-NEXT: s_and_b64 s[8:9], s[8:9], 0x88888888
+; GFX1250-NEXT: s_mul_u64 s[20:21], s[4:5], s[14:15]
+; GFX1250-NEXT: s_mul_u64 s[22:23], s[10:11], s[16:17]
+; GFX1250-NEXT: s_mul_u64 s[28:29], s[4:5], s[12:13]
+; GFX1250-NEXT: s_mul_u64 s[30:31], s[10:11], s[14:15]
+; GFX1250-NEXT: s_mul_u64 s[24:25], s[18:19], s[12:13]
+; GFX1250-NEXT: s_mul_u64 s[26:27], s[8:9], s[2:3]
+; GFX1250-NEXT: s_mul_u64 s[34:35], s[18:19], s[2:3]
+; GFX1250-NEXT: s_mul_u64 s[36:37], s[8:9], s[16:17]
+; GFX1250-NEXT: s_mul_u64 s[38:39], s[4:5], s[16:17]
+; GFX1250-NEXT: s_mul_u64 s[40:41], s[10:11], s[2:3]
+; GFX1250-NEXT: s_mul_u64 s[42:43], s[18:19], s[14:15]
+; GFX1250-NEXT: s_mul_u64 s[44:45], s[8:9], s[12:13]
+; GFX1250-NEXT: s_mul_u64 s[2:3], s[4:5], s[2:3]
+; GFX1250-NEXT: s_mul_u64 s[4:5], s[10:11], s[12:13]
+; GFX1250-NEXT: s_mul_u64 s[8:9], s[8:9], s[14:15]
+; GFX1250-NEXT: s_xor_b64 s[12:13], s[22:23], s[20:21]
; GFX1250-NEXT: s_xor_b64 s[14:15], s[30:31], s[28:29]
-; GFX1250-NEXT: s_mul_u64 s[36:37], s[4:5], s[18:19]
-; GFX1250-NEXT: s_mul_u64 s[42:43], s[20:21], s[16:17]
-; GFX1250-NEXT: s_mul_u64 s[4:5], s[4:5], s[16:17]
+; GFX1250-NEXT: s_mul_u64 s[10:11], s[18:19], s[16:17]
; GFX1250-NEXT: s_xor_b64 s[16:17], s[40:41], s[38:39]
-; GFX1250-NEXT: s_xor_b64 s[2:3], s[8:9], s[2:3]
-; GFX1250-NEXT: s_xor_b64 s[8:9], s[10:11], s[24:25]
-; GFX1250-NEXT: s_xor_b64 s[10:11], s[14:15], s[34:35]
-; GFX1250-NEXT: s_mul_u64 s[12:13], s[20:21], s[18:19]
+; GFX1250-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
+; GFX1250-NEXT: s_xor_b64 s[4:5], s[12:13], s[24:25]
+; GFX1250-NEXT: s_xor_b64 s[12:13], s[14:15], s[34:35]
; GFX1250-NEXT: s_xor_b64 s[14:15], s[16:17], s[42:43]
-; GFX1250-NEXT: s_xor_b64 s[8:9], s[8:9], s[26:27]
-; GFX1250-NEXT: s_xor_b64 s[10:11], s[10:11], s[36:37]
-; GFX1250-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13]
+; GFX1250-NEXT: s_xor_b64 s[2:3], s[2:3], s[10:11]
+; GFX1250-NEXT: s_xor_b64 s[4:5], s[4:5], s[26:27]
+; GFX1250-NEXT: s_xor_b64 s[10:11], s[12:13], s[36:37]
; GFX1250-NEXT: s_xor_b64 s[12:13], s[14:15], s[44:45]
-; GFX1250-NEXT: s_and_b64 s[8:9], s[8:9], 0x2222222200000000
+; GFX1250-NEXT: s_and_b64 s[4:5], s[4:5], 0x2222222200000000
; GFX1250-NEXT: s_and_b64 s[10:11], s[10:11], 0x1111111100000000
; GFX1250-NEXT: s_and_b64 s[12:13], s[12:13], 0x4444444400000000
-; GFX1250-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
-; GFX1250-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
-; GFX1250-NEXT: s_or_b64 s[4:5], s[8:9], s[12:13]
+; GFX1250-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
+; GFX1250-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9]
+; GFX1250-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13]
; GFX1250-NEXT: s_and_b64 s[2:3], s[2:3], 0x888888880000000
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
@@ -3248,62 +3246,60 @@ define amdgpu_kernel void @test_clmulh_i32(ptr addrspace(1) %out, ptr addrspace(
; GFX1250-NEXT: s_mov_b32 s7, 0x31016000
; GFX1250-NEXT: s_mov_b32 s10, s6
; GFX1250-NEXT: s_mov_b32 s11, s7
-; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: s_mov_b64 s[4:5], 0x88888888
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_mov_b32 s8, s2
; GFX1250-NEXT: s_mov_b32 s9, s3
; GFX1250-NEXT: s_mov_b32 s3, 0
; GFX1250-NEXT: buffer_load_b64 v[0:1], off, s[8:11], null
+; GFX1250-NEXT: s_mov_b32 s5, s3
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: s_mov_b32 s9, s3
-; GFX1250-NEXT: s_mov_b32 s13, s3
-; GFX1250-NEXT: s_mov_b32 s15, s3
; GFX1250-NEXT: s_mov_b32 s11, s3
+; GFX1250-NEXT: s_mov_b32 s13, s3
+; GFX1250-NEXT: s_mov_b32 s9, s3
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_readfirstlane_b32 s2, v1
-; GFX1250-NEXT: v_readfirstlane_b32 s10, v0
-; GFX1250-NEXT: s_and_b64 s[16:17], s[2:3], 0x11111111
-; GFX1250-NEXT: s_and_b32 s8, s10, 0x22222222
-; GFX1250-NEXT: s_and_b64 s[18:19], s[2:3], 0x22222222
-; GFX1250-NEXT: s_and_b32 s12, s10, 0x11111111
-; GFX1250-NEXT: s_and_b32 s14, s2, 0x88888888
-; GFX1250-NEXT: s_and_b64 s[20:21], s[10:11], 0x44444444
+; GFX1250-NEXT: v_readfirstlane_b32 s8, v0
+; GFX1250-NEXT: s_and_b64 s[14:15], s[2:3], 0x11111111
+; GFX1250-NEXT: s_and_b32 s4, s8, 0x22222222
+; GFX1250-NEXT: s_and_b64 s[16:17], s[2:3], 0x22222222
+; GFX1250-NEXT: s_and_b32 s10, s8, 0x11111111
+; GFX1250-NEXT: s_and_b32 s12, s2, 0x88888888
+; GFX1250-NEXT: s_and_b64 s[18:19], s[8:9], 0x44444444
; GFX1250-NEXT: s_and_b32 s2, s2, 0x44444444
-; GFX1250-NEXT: s_and_b64 s[4:5], s[10:11], s[4:5]
-; GFX1250-NEXT: s_mul_u64 s[10:11], s[8:9], s[16:17]
-; GFX1250-NEXT: s_mul_u64 s[22:23], s[12:13], s[18:19]
-; GFX1250-NEXT: s_mul_u64 s[28:29], s[8:9], s[14:15]
-; GFX1250-NEXT: s_mul_u64 s[30:31], s[12:13], s[16:17]
-; GFX1250-NEXT: s_mul_u64 s[24:25], s[20:21], s[14:15]
-; GFX1250-NEXT: s_mul_u64 s[26:27], s[4:5], s[2:3]
-; GFX1250-NEXT: s_mul_u64 s[34:35], s[20:21], s[2:3]
-; GFX1250-NEXT: s_mul_u64 s[38:39], s[8:9], s[18:19]
-; GFX1250-NEXT: s_mul_u64 s[40:41], s[12:13], s[2:3]
-; GFX1250-NEXT: s_mul_u64 s[44:45], s[4:5], s[14:15]
-; GFX1250-NEXT: s_mul_u64 s[2:3], s[8:9], s[2:3]
-; GFX1250-NEXT: s_mul_u64 s[8:9], s[12:13], s[14:15]
-; GFX1250-NEXT: s_xor_b64 s[10:11], s[22:23], s[10:11]
+; GFX1250-NEXT: s_and_b64 s[8:9], s[8:9], 0x88888888
+; GFX1250-NEXT: s_mul_u64 s[20:21], s[4:5], s[14:15]
+; GFX1250-NEXT: s_mul_u64 s[22:23], s[10:11], s[16:17]
+; GFX1250-NEXT: s_mul_u64 s[28:29], s[4:5], s[12:13]
+; GFX1250-NEXT: s_mul_u64 s[30:31], s[10:11], s[14:15]
+; GFX1250-NEXT: s_mul_u64 s[24:25], s[18:19], s[12:13]
+; GFX1250-NEXT: s_mul_u64 s[26:27], s[8:9], s[2:3]
+; GFX1250-NEXT: s_mul_u64 s[34:35], s[18:19], s[2:3]
+; GFX1250-NEXT: s_mul_u64 s[36:37], s[8:9], s[16:17]
+; GFX1250-NEXT: s_mul_u64 s[38:39], s[4:5], s[16:17]
+; GFX1250-NEXT: s_mul_u64 s[40:41], s[10:11], s[2:3]
+; GFX1250-NEXT: s_mul_u64 s[42:43], s[18:19], s[14:15]
+; GFX1250-NEXT: s_mul_u64 s[44:45], s[8:9], s[12:13]
+; GFX1250-NEXT: s_mul_u64 s[2:3], s[4:5], s[2:3]
+; GFX1250-NEXT: s_mul_u64 s[4:5], s[10:11], s[12:13]
+; GFX1250-NEXT: s_mul_u64 s[8:9], s[8:9], s[14:15]
+; GFX1250-NEXT: s_xor_b64 s[12:13], s[22:23], s[20:21]
; GFX1250-NEXT: s_xor_b64 s[14:15], s[30:31], s[28:29]
-; GFX1250-NEXT: s_mul_u64 s[36:37], s[4:5], s[18:19]
-; GFX1250-NEXT: s_mul_u64 s[42:43], s[20:21], s[16:17]
-; GFX1250-NEXT: s_mul_u64 s[4:5], s[4:5], s[16:17]
+; GFX1250-NEXT: s_mul_u64 s[10:11], s[18:19], s[16:17]
; GFX1250-NEXT: s_xor_b64 s[16:17], s[40:41], s[38:39]
-; GFX1250-NEXT: s_xor_b64 s[2:3], s[8:9], s[2:3]
-; GFX1250-NEXT: s_xor_b64 s[8:9], s[10:11], s[24:25]
-; GFX1250-NEXT: s_xor_b64 s[10:11], s[14:15], s[34:35]
-; GFX1250-NEXT: s_mul_u64 s[12:13], s[20:21], s[18:19]
+; GFX1250-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
+; GFX1250-NEXT: s_xor_b64 s[4:5], s[12:13], s[24:25]
+; GFX1250-NEXT: s_xor_b64 s[12:13], s[14:15], s[34:35]
; GFX1250-NEXT: s_xor_b64 s[14:15], s[16:17], s[42:43]
-; GFX1250-NEXT: s_xor_b64 s[8:9], s[8:9], s[26:27]
-; GFX1250-NEXT: s_xor_b64 s[10:11], s[10:11], s[36:37]
-; GFX1250-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13]
+; GFX1250-NEXT: s_xor_b64 s[2:3], s[2:3], s[10:11]
+; GFX1250-NEXT: s_xor_b64 s[4:5], s[4:5], s[26:27]
+; GFX1250-NEXT: s_xor_b64 s[10:11], s[12:13], s[36:37]
; GFX1250-NEXT: s_xor_b64 s[12:13], s[14:15], s[44:45]
-; GFX1250-NEXT: s_and_b64 s[8:9], s[8:9], 0x2222222200000000
+; GFX1250-NEXT: s_and_b64 s[4:5], s[4:5], 0x2222222200000000
; GFX1250-NEXT: s_and_b64 s[10:11], s[10:11], 0x1111111100000000
; GFX1250-NEXT: s_and_b64 s[12:13], s[12:13], 0x4444444400000000
-; GFX1250-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
-; GFX1250-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
-; GFX1250-NEXT: s_or_b64 s[4:5], s[8:9], s[12:13]
+; GFX1250-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
+; GFX1250-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9]
+; GFX1250-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13]
; GFX1250-NEXT: s_and_b64 s[2:3], s[2:3], 0x888888800000000
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
index 1c7da39fbccc6..f6d5b1b3950ec 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
@@ -816,10 +816,9 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn_neg128(ptr inreg %sbase, i
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -1170,11 +1169,10 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
@@ -1728,10 +1726,9 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -2100,11 +2097,10 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
@@ -2674,10 +2670,9 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -3050,11 +3045,10 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
@@ -3626,10 +3620,9 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -4002,11 +3995,10 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
@@ -4578,10 +4570,9 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn_neg128(ptr inreg %sbase, i32
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -4954,11 +4945,10 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vof
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
@@ -5530,10 +5520,9 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -5906,11 +5895,10 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
@@ -6432,10 +6420,9 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -6788,11 +6775,10 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
@@ -7304,10 +7290,9 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -7660,11 +7645,10 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
@@ -8176,10 +8160,9 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn_neg128(ptr inreg %sbase, i
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -8532,11 +8515,10 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
@@ -9048,10 +9030,9 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn_neg128(ptr inreg %sbase, i
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -9404,11 +9385,10 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
@@ -9990,12 +9970,11 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn_neg128(ptr inreg %sbase
; GFX1250-SDAG-NEXT: v_nop
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v6, v1
-; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
-; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v5, v4
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v4, v3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v3
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -10387,13 +10366,12 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32
; GFX1250-SDAG-NEXT: v_nop
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v6, v1
-; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
-; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v5, v4
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v4, v3
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v2, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v2
@@ -10932,10 +10910,9 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -11308,11 +11285,10 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
@@ -11845,10 +11821,9 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5
; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0
@@ -12233,11 +12208,10 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80
+; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
-; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0xffffffffffffff80, v[0:1]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1
; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4
diff --git a/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir b/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
index 1eca409bbed86..e88b44a733743 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
@@ -102,8 +102,7 @@ body: |
; GCN-LABEL: name: fold_uint_32bit_literal_sgpr
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
- ; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 4294967295
- ; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[DEF]], [[S_MOV_B64_]], implicit-def $scc
+ ; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[DEF]], 4294967295, implicit-def $scc
; GCN-NEXT: SI_RETURN_TO_EPILOG [[S_AND_B64_]]
%0:sreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64 4294967295
diff --git a/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir b/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
index d9cd90e95c257..781678e9e94ae 100644
--- a/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
+++ b/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
@@ -24,8 +24,7 @@ name: imm64_shift_int32_const_0xffffffff
body: |
bb.0:
; GCN-LABEL: name: imm64_shift_int32_const_0xffffffff
- ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
- ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
+ ; GCN: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 4294967295, 1, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
%1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
@@ -38,8 +37,7 @@ name: imm64_shift_int32_const_0x80000000
body: |
bb.0:
; GCN-LABEL: name: imm64_shift_int32_const_0x80000000
- ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483648
- ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
+ ; GCN: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 2147483648, 1, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483648
%1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
@@ -92,8 +90,7 @@ name: imm64_ashr_int32_const_0xffffffff
body: |
bb.0:
; GCN-LABEL: name: imm64_ashr_int32_const_0xffffffff
- ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
- ; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[S_MOV_B]], 1, implicit-def $scc
+ ; GCN: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 4294967295, 1, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
%1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
index c1089c70368be..088d9d634d2f0 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
@@ -9862,16 +9862,15 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: s_mov_b64 s[0:1], 0xfffffffffffff800
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], 0xfffffffffffff800, v[0:1]
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v3, 3, v4
; GFX1250-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_not_b32_e32 v4, v4
; GFX1250-TRUE16-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9907,16 +9906,15 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: s_mov_b64 s[0:1], 0xfffffffffffff800
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], 0xfffffffffffff800, v[0:1]
; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 3, v4
; GFX1250-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_not_b32_e32 v4, v4
; GFX1250-FAKE16-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX1250-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -11377,16 +11375,15 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: s_mov_b64 s[0:1], 0xfffffffffffff800
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], 0xfffffffffffff800, v[0:1]
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v3, 3, v4
; GFX1250-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_not_b32_e32 v6, v4
; GFX1250-TRUE16-NEXT: .LBB49_1: ; %atomicrmw.start
; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -11420,16 +11417,15 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: s_mov_b64 s[0:1], 0xfffffffffffff800
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], 0xfffffffffffff800, v[0:1]
; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 3, v4
; GFX1250-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_not_b32_e32 v6, v4
; GFX1250-FAKE16-NEXT: .LBB49_1: ; %atomicrmw.start
; GFX1250-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -14566,16 +14562,15 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_mov_b64 s[0:1], 0xfffffffffffff800
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-NEXT: v_add_nc_u64_e32 v[4:5], 0xfffffffffffff800, v[0:1]
; GFX1250-NEXT: s_mov_b32 s0, 0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-NEXT: v_and_b32_e32 v3, 3, v4
; GFX1250-NEXT: global_load_b32 v5, v[0:1], off
; GFX1250-NEXT: v_lshlrev_b32_e32 v3, 3, v3
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_not_b32_e32 v4, v4
; GFX1250-NEXT: .LBB56_1: ; %atomicrmw.start
; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -15928,11 +15923,10 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: s_mov_b64 s[0:1], 0xfffffffffffff800
+; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], 0xfffffffffffff800, v[0:1]
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
-; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX1250-TRUE16-NEXT: global_load_b32 v3, v[0:1], off
@@ -15972,16 +15966,15 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: s_mov_b64 s[0:1], 0xfffffffffffff800
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
+; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], 0xfffffffffffff800, v[0:1]
; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 3, v4
; GFX1250-FAKE16-NEXT: global_load_b32 v5, v[0:1], off
; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_not_b32_e32 v6, v4
; GFX1250-FAKE16-NEXT: .LBB59_1: ; %atomicrmw.start
; GFX1250-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll b/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
index 24915e073208c..a134c672f3e7b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
@@ -134,9 +134,7 @@ define amdgpu_ps void @prefetch_data_sgpr_min_offset(ptr addrspace(4) inreg %ptr
; GFX1250-SPREFETCH-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-SPREFETCH-SDAG-NEXT: v_nop
; GFX1250-SPREFETCH-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-SPREFETCH-SDAG-NEXT: s_mov_b64 s[2:3], 0xffffffffff800000
-; GFX1250-SPREFETCH-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-SPREFETCH-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX1250-SPREFETCH-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0xffffffffff800000
; GFX1250-SPREFETCH-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GFX1250-SPREFETCH-SDAG-NEXT: s_endpgm
;
@@ -646,9 +644,7 @@ define amdgpu_ps void @prefetch_inst_sgpr_min_offset(ptr addrspace(4) inreg %ptr
; GFX1250-SPREFETCH-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-SPREFETCH-SDAG-NEXT: v_nop
; GFX1250-SPREFETCH-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-SPREFETCH-SDAG-NEXT: s_mov_b64 s[2:3], 0xffffffffff800000
-; GFX1250-SPREFETCH-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-SPREFETCH-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX1250-SPREFETCH-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0xffffffffff800000
; GFX1250-SPREFETCH-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
; GFX1250-SPREFETCH-SDAG-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll b/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
index 4ef9df249c41c..860a52b9075d5 100644
--- a/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
@@ -666,17 +666,15 @@ define amdgpu_kernel void @copy_flat_divergent(ptr nocapture %d, ptr nocapture r
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x34 nv
+; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x34 nv
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_cmp_eq_u32 s2, 0
+; GFX1250-NEXT: s_cmp_eq_u32 s0, 0
; GFX1250-NEXT: s_cbranch_scc1 .LBB4_3
; GFX1250-NEXT: ; %bb.1: ; %for.body.preheader
; GFX1250-NEXT: s_load_b128 s[8:11], s[4:5], 0x24 nv
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1250-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff50
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 4, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], s[10:11], v[0:1]
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], s[8:9], v[0:1]
@@ -685,11 +683,11 @@ define amdgpu_kernel void @copy_flat_divergent(ptr nocapture %d, ptr nocapture r
; GFX1250-NEXT: .LBB4_2: ; %for.body
; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[2:3]
+; GFX1250-NEXT: v_add_nc_u64_e32 v[4:5], 0xffffffffffffff50, v[2:3]
; GFX1250-NEXT: flat_prefetch_b8 v[2:3] scope:SCOPE_SE
; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], 16, v[2:3]
-; GFX1250-NEXT: s_add_co_i32 s2, s2, -1
-; GFX1250-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1250-NEXT: s_add_co_i32 s0, s0, -1
+; GFX1250-NEXT: s_cmp_lg_u32 s0, 0
; GFX1250-NEXT: flat_load_b128 v[4:7], v[4:5]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_store_b128 v[0:1], v[4:7]
diff --git a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
index bbc7f6cce50b0..b2215891f4d89 100644
--- a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
@@ -2237,9 +2237,8 @@ define amdgpu_ps i64 @lshr_mad_i64_sgpr(i64 inreg %arg0) #0 {
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: s_mov_b32 s3, 0
; GFX1250-NEXT: s_mov_b32 s2, s1
-; GFX1250-NEXT: s_mov_b64 s[4:5], 0xffffffffffff1c18
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_mul_u64 s[2:3], s[2:3], s[4:5]
+; GFX1250-NEXT: s_mul_u64 s[2:3], s[2:3], 0xffffffffffff1c18
; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1]
; GFX1250-NEXT: ; return to shader part epilog
%lsh = lshr i64 %arg0, 32
diff --git a/llvm/test/CodeGen/AMDGPU/mul.ll b/llvm/test/CodeGen/AMDGPU/mul.ll
index 1fad5619a628c..bf1a931c3f44b 100644
--- a/llvm/test/CodeGen/AMDGPU/mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul.ll
@@ -3693,43 +3693,41 @@ define amdgpu_kernel void @s_mul_i128(ptr addrspace(1) %out, [8 x i32], i128 %a,
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: s_clause 0x2
+; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[8:11], s[4:5], 0x7c nv
; GFX1250-NEXT: s_load_b128 s[12:15], s[4:5], 0x4c nv
+; GFX1250-NEXT: s_mov_b32 s3, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: s_mov_b64 s[4:5], 0xffffffff
-; GFX1250-NEXT: s_mov_b32 s3, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_mov_b32 s5, s3
; GFX1250-NEXT: s_mov_b32 s7, s3
; GFX1250-NEXT: s_mov_b32 s17, s3
-; GFX1250-NEXT: s_mov_b32 s19, s3
-; GFX1250-NEXT: s_mov_b32 s20, s3
+; GFX1250-NEXT: s_mov_b32 s18, s3
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_mov_b32 s2, s8
-; GFX1250-NEXT: s_and_b64 s[4:5], s[12:13], s[4:5]
-; GFX1250-NEXT: s_mov_b32 s6, s13
+; GFX1250-NEXT: s_and_b64 s[20:21], s[12:13], 0xffffffff
+; GFX1250-NEXT: s_mov_b32 s4, s13
; GFX1250-NEXT: s_mul_u64 s[10:11], s[10:11], s[12:13]
-; GFX1250-NEXT: s_mul_u64 s[12:13], s[4:5], s[2:3]
-; GFX1250-NEXT: s_mov_b32 s16, s9
+; GFX1250-NEXT: s_mul_u64 s[12:13], s[20:21], s[2:3]
+; GFX1250-NEXT: s_mov_b32 s6, s9
; GFX1250-NEXT: s_mul_u64 s[8:9], s[8:9], s[14:15]
-; GFX1250-NEXT: s_mul_u64 s[14:15], s[6:7], s[2:3]
+; GFX1250-NEXT: s_mul_u64 s[14:15], s[4:5], s[2:3]
; GFX1250-NEXT: s_mov_b32 s2, s13
-; GFX1250-NEXT: s_mul_u64 s[4:5], s[4:5], s[16:17]
+; GFX1250-NEXT: s_mul_u64 s[20:21], s[20:21], s[6:7]
; GFX1250-NEXT: s_add_nc_u64 s[14:15], s[14:15], s[2:3]
-; GFX1250-NEXT: s_mul_u64 s[6:7], s[6:7], s[16:17]
+; GFX1250-NEXT: s_mul_u64 s[4:5], s[4:5], s[6:7]
; GFX1250-NEXT: s_mov_b32 s2, s15
; GFX1250-NEXT: s_mov_b32 s15, s3
+; GFX1250-NEXT: s_add_nc_u64 s[6:7], s[10:11], s[8:9]
+; GFX1250-NEXT: s_add_nc_u64 s[8:9], s[20:21], s[14:15]
; GFX1250-NEXT: s_mov_b32 s13, s3
-; GFX1250-NEXT: s_add_nc_u64 s[4:5], s[4:5], s[14:15]
-; GFX1250-NEXT: s_add_nc_u64 s[8:9], s[10:11], s[8:9]
-; GFX1250-NEXT: s_mov_b32 s18, s5
-; GFX1250-NEXT: s_mov_b32 s21, s4
-; GFX1250-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[18:19]
-; GFX1250-NEXT: s_or_b64 s[4:5], s[12:13], s[20:21]
-; GFX1250-NEXT: s_add_nc_u64 s[2:3], s[6:7], s[2:3]
-; GFX1250-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX1250-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[8:9]
+; GFX1250-NEXT: s_mov_b32 s16, s9
+; GFX1250-NEXT: s_mov_b32 s19, s8
+; GFX1250-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[16:17]
+; GFX1250-NEXT: s_or_b64 s[8:9], s[12:13], s[18:19]
+; GFX1250-NEXT: s_add_nc_u64 s[2:3], s[4:5], s[2:3]
+; GFX1250-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX1250-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[6:7]
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX1250-NEXT: s_mov_b32 s3, 0x31016000
@@ -3739,42 +3737,41 @@ define amdgpu_kernel void @s_mul_i128(ptr addrspace(1) %out, [8 x i32], i128 %a,
;
; GFX13-LABEL: s_mul_i128:
; GFX13: ; %bb.0: ; %entry
-; GFX13-NEXT: s_clause 0x2
+; GFX13-NEXT: s_clause 0x1
; GFX13-NEXT: s_load_b128 s[8:11], s[4:5], 0x7c nv
; GFX13-NEXT: s_load_b128 s[12:15], s[4:5], 0x4c nv
-; GFX13-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; GFX13-NEXT: s_mov_b64 s[4:5], 0xffffffff
; GFX13-NEXT: s_mov_b32 s3, 0
-; GFX13-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13-NEXT: s_mov_b32 s5, s3
; GFX13-NEXT: s_mov_b32 s7, s3
; GFX13-NEXT: s_mov_b32 s17, s3
-; GFX13-NEXT: s_mov_b32 s19, s3
-; GFX13-NEXT: s_mov_b32 s20, s3
+; GFX13-NEXT: s_mov_b32 s18, s3
; GFX13-NEXT: s_wait_kmcnt 0x0
; GFX13-NEXT: s_mov_b32 s2, s8
-; GFX13-NEXT: s_and_b64 s[4:5], s[12:13], s[4:5]
-; GFX13-NEXT: s_mov_b32 s6, s13
-; GFX13-NEXT: s_mul_u64 s[22:23], s[4:5], s[2:3]
-; GFX13-NEXT: s_mul_u64 s[24:25], s[6:7], s[2:3]
+; GFX13-NEXT: s_and_b64 s[20:21], s[12:13], 0xffffffff
+; GFX13-NEXT: s_mov_b32 s4, s13
+; GFX13-NEXT: s_mul_u64 s[22:23], s[20:21], s[2:3]
+; GFX13-NEXT: s_mul_u64 s[24:25], s[4:5], s[2:3]
; GFX13-NEXT: s_mov_b32 s2, s23
-; GFX13-NEXT: s_mov_b32 s16, s9
-; GFX13-NEXT: s_mul_u64 s[10:11], s[10:11], s[12:13]
-; GFX13-NEXT: s_add_nc_u64 s[12:13], s[24:25], s[2:3]
-; GFX13-NEXT: s_mul_u64 s[4:5], s[4:5], s[16:17]
-; GFX13-NEXT: s_mov_b32 s2, s13
-; GFX13-NEXT: s_mov_b32 s13, s3
+; GFX13-NEXT: s_mov_b32 s6, s9
; GFX13-NEXT: s_mul_u64 s[8:9], s[8:9], s[14:15]
-; GFX13-NEXT: s_add_nc_u64 s[4:5], s[4:5], s[12:13]
-; GFX13-NEXT: s_mul_u64 s[6:7], s[6:7], s[16:17]
-; GFX13-NEXT: s_mov_b32 s18, s5
+; GFX13-NEXT: s_add_nc_u64 s[14:15], s[24:25], s[2:3]
+; GFX13-NEXT: s_mul_u64 s[10:11], s[10:11], s[12:13]
+; GFX13-NEXT: s_mul_u64 s[12:13], s[20:21], s[6:7]
+; GFX13-NEXT: s_mov_b32 s2, s15
+; GFX13-NEXT: s_mov_b32 s15, s3
+; GFX13-NEXT: s_mul_u64 s[4:5], s[4:5], s[6:7]
+; GFX13-NEXT: s_add_nc_u64 s[6:7], s[10:11], s[8:9]
+; GFX13-NEXT: s_add_nc_u64 s[8:9], s[12:13], s[14:15]
; GFX13-NEXT: s_mov_b32 s23, s3
-; GFX13-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[18:19]
-; GFX13-NEXT: s_add_nc_u64 s[8:9], s[10:11], s[8:9]
-; GFX13-NEXT: s_mov_b32 s21, s4
-; GFX13-NEXT: s_add_nc_u64 s[2:3], s[6:7], s[2:3]
-; GFX13-NEXT: s_or_b64 s[4:5], s[22:23], s[20:21]
-; GFX13-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[8:9]
-; GFX13-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX13-NEXT: s_mov_b32 s16, s9
+; GFX13-NEXT: s_mov_b32 s19, s8
+; GFX13-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[16:17]
+; GFX13-NEXT: s_or_b64 s[8:9], s[22:23], s[18:19]
+; GFX13-NEXT: s_add_nc_u64 s[2:3], s[4:5], s[2:3]
+; GFX13-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX13-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[6:7]
+; GFX13-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX13-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX13-NEXT: s_mov_b32 s3, 0x31016000
; GFX13-NEXT: s_mov_b32 s2, -1
diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
index 1a04889eba18e..484d1dd8216b6 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
@@ -17,14 +17,13 @@ define amdgpu_kernel void @promote_async_load_offset_negative(ptr addrspace(1) %
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NEXT: s_mov_b64 s[2:3], 0xffffffffffffff00
; GFX1250-NEXT: v_add_nc_u32_e64 v4, 0xfffffe00, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_add_nc_u32_e32 v0, 0x100, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[2:3]
+; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], 0xffffffffffffff00, v[2:3]
; GFX1250-NEXT: global_load_async_to_lds_b128 v1, v0, s[0:1]
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: global_load_async_to_lds_b128 v4, v[2:3], off offset:512
@@ -116,14 +115,13 @@ define amdgpu_kernel void @promote_async_store_offset_negative(ptr addrspace(1)
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NEXT: s_mov_b64 s[2:3], 0xffffffffffffff00
; GFX1250-NEXT: v_add_nc_u32_e64 v4, 0xfffffe00, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_add_nc_u32_e32 v0, 0x100, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[2:3]
+; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], 0xffffffffffffff00, v[2:3]
; GFX1250-NEXT: global_store_async_from_lds_b128 v0, v1, s[0:1]
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: global_store_async_from_lds_b128 v[2:3], v4, off offset:512
>From fa233cab85a3f2d2ea97a3e823865bb9fe7edb39 Mon Sep 17 00:00:00 2001
From: addmisol <addmisol9 at gmail.com>
Date: Sat, 29 Aug 2026 21:46:17 +0530
Subject: [PATCH 2/5] Fix issues
Signed-off-by: addmisol <addmisol9 at gmail.com>
---
llvm/lib/Target/AMDGPU/SOPInstructions.td | 40 +++++++++++++-----
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 4 +-
llvm/lib/Target/AMDGPU/VOPCInstructions.td | 42 +++++++++++--------
.../AMDGPU/GlobalISel/combine-short-clamp.ll | 16 +++----
4 files changed, 61 insertions(+), 41 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 8962a42601909..4a7eb28436bdd 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -133,6 +133,12 @@ class SOP1_32_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
"$sdst, $src0", pattern
>;
+// 64-bit signed input, 32-bit output (for S_FLBIT_I32_I64).
+class SOP1_32_64_Signed <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
+ opName, (outs SReg_32:$sdst), (ins SSrc_i64:$src0),
+ "$sdst, $src0", pattern
+>;
+
// 32-bit input, 64-bit output.
class SOP1_64_32 <string opName, list<dag> pattern=[], bit tied_in = 0> : SOP1_Pseudo <
opName, (outs SReg_64:$sdst),
@@ -159,6 +165,12 @@ class SOP1_1_REGIMM64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
let has_sdst = 0;
}
+// Signed 64-bit input, no output (for S_ADD_PC_I64).
+class SOP1_1_REGIMM64_Signed <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
+ opName, (outs), (ins SSrc_i64:$src0), "$src0", pattern> {
+ let has_sdst = 0;
+}
+
class UniformUnaryFrag<SDPatternOperator Op> : PatFrag <
(ops node:$src0),
(Op $src0),
@@ -297,7 +309,7 @@ def S_FLBIT_I32_B64 : SOP1_32_64 <"s_flbit_i32_b64",
def S_FLBIT_I32 : SOP1_32 <"s_flbit_i32",
[(set i32:$sdst, (UniformUnaryFrag<int_amdgcn_sffbh> i32:$src0))]
>;
-def S_FLBIT_I32_I64 : SOP1_32_64 <"s_flbit_i32_i64">;
+def S_FLBIT_I32_I64 : SOP1_32_64_Signed <"s_flbit_i32_i64">;
def S_SEXT_I32_I8 : SOP1_32 <"s_sext_i32_i8",
[(set i32:$sdst, (UniformSextInreg<i8> i32:$src0))]
>;
@@ -325,7 +337,7 @@ let isBranch = 1, isIndirectBranch = 1 in {
def S_SETPC_B64 : SOP1_1 <"s_setpc_b64">;
let SubtargetPredicate = HasAddPC64Inst in
-def S_ADD_PC_I64 : SOP1_1_REGIMM64 <"s_add_pc_i64">;
+def S_ADD_PC_I64 : SOP1_1_REGIMM64_Signed <"s_add_pc_i64">;
} // End isBranch = 1, isIndirectBranch = 1
let isReturn = 1 in {
@@ -664,12 +676,18 @@ class SOP2_64 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
"$sdst, $src0, $src1", pattern
>;
-class SOP2_64_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
+class SOP2_U64_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
opName, (outs SReg_64:$sdst), (ins SSrc_u64:$src0, SSrc_b32:$src1),
"$sdst, $src0, $src1", pattern
>;
-class SOP2_64_32_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
+// Signed variant for arithmetic shift right (S_ASHR_I64)
+class SOP2_U64_32_Signed <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
+ opName, (outs SReg_64:$sdst), (ins SSrc_i64:$src0, SSrc_b32:$src1),
+ "$sdst, $src0, $src1", pattern
+>;
+
+class SOP2_U64_32_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
opName, (outs SReg_64:$sdst), (ins SSrc_b32:$src0, SSrc_b32:$src1),
"$sdst, $src0, $src1", pattern
>;
@@ -835,26 +853,26 @@ let Defs = [SCC] in {
def S_LSHL_B32 : SOP2_32 <"s_lshl_b32",
[(set SReg_32:$sdst, (UniformBinFrag<cshl_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
>;
-def S_LSHL_B64 : SOP2_64_32 <"s_lshl_b64",
+def S_LSHL_B64 : SOP2_U64_32 <"s_lshl_b64",
[(set SReg_64:$sdst, (UniformBinFrag<cshl_64> (i64 SSrc_u64:$src0), (i32 SSrc_b32:$src1)))]
>;
def S_LSHR_B32 : SOP2_32 <"s_lshr_b32",
[(set SReg_32:$sdst, (UniformBinFrag<csrl_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
>;
-def S_LSHR_B64 : SOP2_64_32 <"s_lshr_b64",
+def S_LSHR_B64 : SOP2_U64_32 <"s_lshr_b64",
[(set SReg_64:$sdst, (UniformBinFrag<csrl_64> (i64 SSrc_u64:$src0), (i32 SSrc_b32:$src1)))]
>;
def S_ASHR_I32 : SOP2_32 <"s_ashr_i32",
[(set SReg_32:$sdst, (UniformBinFrag<csra_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
>;
-def S_ASHR_I64 : SOP2_64_32 <"s_ashr_i64",
- [(set SReg_64:$sdst, (UniformBinFrag<csra_64> (i64 SSrc_u64:$src0), (i32 SSrc_b32:$src1)))]
+def S_ASHR_I64 : SOP2_U64_32_Signed <"s_ashr_i64",
+ [(set SReg_64:$sdst, (UniformBinFrag<csra_64> (i64 SSrc_i64:$src0), (i32 SSrc_b32:$src1)))]
>;
} // End Defs = [SCC]
let isReMaterializable = 1 in {
def S_BFM_B32 : SOP2_32 <"s_bfm_b32">;
-def S_BFM_B64 : SOP2_64_32_32 <"s_bfm_b64">;
+def S_BFM_B64 : SOP2_U64_32_32 <"s_bfm_b64">;
def S_MUL_I32 : SOP2_32 <"s_mul_i32",
[(set i32:$sdst, (UniformBinFrag<mul> i32:$src0, i32:$src1))]> {
@@ -866,8 +884,8 @@ def S_MUL_I32 : SOP2_32 <"s_mul_i32",
let Defs = [SCC] in {
def S_BFE_U32 : SOP2_32 <"s_bfe_u32">;
def S_BFE_I32 : SOP2_32 <"s_bfe_i32">;
-def S_BFE_U64 : SOP2_64_32 <"s_bfe_u64">;
-def S_BFE_I64 : SOP2_64_32 <"s_bfe_i64">;
+def S_BFE_U64 : SOP2_U64_32 <"s_bfe_u64">;
+def S_BFE_I64 : SOP2_U64_32 <"s_bfe_i64">;
} // End Defs = [SCC]
def S_CBRANCH_G_FORK : SOP2_Pseudo <
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index d5fc82a3227ac..d8aebb06c2234 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -410,12 +410,12 @@ let SchedRW = [Write64Bit] in {
let SubtargetPredicate = isGFX6GFX7, IsDPMACCInstruction = 1 in {
defm V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, cshl_64>;
defm V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, csrl_64>;
- defm V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, csra_64>;
+ defm V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32_Signed>, csra_64>;
} // End SubtargetPredicate = isGFX6GFX7
let SubtargetPredicate = isGFX8Plus in {
defm V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, clshr_rev_64>;
- defm V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, cashr_rev_64>;
+ defm V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64_Signed>, cashr_rev_64>;
} // End SubtargetPredicate = isGFX8Plus
let SubtargetPredicate = isGFX8GFX9GFX10GFX11 in {
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index fb05aad39d975..2d555c5e1713d 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -551,6 +551,10 @@ multiclass VOPC_I32 <string opName, SDPatternOperator cond = COND_NULL, string r
let IsDPMACCInstruction = 1 in {
multiclass VOPC_I64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
VOPC_Pseudos <opName, VOPC_I1_I64_I64, cond, revOp, 0>;
+
+ // Signed variant for signed integer comparisons (V_CMP_*_I64)
+ multiclass VOPC_I64_Signed <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
+ VOPC_Pseudos <opName, VOPC_I1_I64_I64_Signed, cond, revOp, 0>;
}
multiclass VOPCX_F16<string opName, string revOp = opName> {
@@ -591,6 +595,10 @@ multiclass VOPCX_I32 <string opName, string revOp = opName> :
let IsDPMACCInstruction = 1 in {
multiclass VOPCX_I64 <string opName, string revOp = opName> :
VOPCX_Pseudos <opName, VOPC_I1_I64_I64, VOPC_I64_I64, COND_NULL, revOp>;
+
+ // Signed variant for signed integer comparisons (V_CMPX_*_I64)
+ multiclass VOPCX_I64_Signed <string opName, string revOp = opName> :
+ VOPCX_Pseudos <opName, VOPC_I1_I64_I64_Signed, VOPC_I64_I64_Signed, COND_NULL, revOp>;
}
@@ -830,23 +838,23 @@ defm V_CMPX_NE_I32 : VOPCX_I32 <"v_cmpx_ne_i32">;
defm V_CMPX_GE_I32 : VOPCX_I32 <"v_cmpx_ge_i32">;
defm V_CMPX_T_I32 : VOPCX_I32 <"v_cmpx_t_i32">;
-defm V_CMP_F_I64 : VOPC_I64 <"v_cmp_f_i64">;
-defm V_CMP_LT_I64 : VOPC_I64 <"v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
-defm V_CMP_EQ_I64 : VOPC_I64 <"v_cmp_eq_i64">;
-defm V_CMP_LE_I64 : VOPC_I64 <"v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
-defm V_CMP_GT_I64 : VOPC_I64 <"v_cmp_gt_i64", COND_SGT>;
-defm V_CMP_NE_I64 : VOPC_I64 <"v_cmp_ne_i64">;
-defm V_CMP_GE_I64 : VOPC_I64 <"v_cmp_ge_i64", COND_SGE>;
-defm V_CMP_T_I64 : VOPC_I64 <"v_cmp_t_i64">;
-
-defm V_CMPX_F_I64 : VOPCX_I64 <"v_cmpx_f_i64">;
-defm V_CMPX_LT_I64 : VOPCX_I64 <"v_cmpx_lt_i64", "v_cmpx_gt_i64">;
-defm V_CMPX_EQ_I64 : VOPCX_I64 <"v_cmpx_eq_i64">;
-defm V_CMPX_LE_I64 : VOPCX_I64 <"v_cmpx_le_i64", "v_cmpx_ge_i64">;
-defm V_CMPX_GT_I64 : VOPCX_I64 <"v_cmpx_gt_i64">;
-defm V_CMPX_NE_I64 : VOPCX_I64 <"v_cmpx_ne_i64">;
-defm V_CMPX_GE_I64 : VOPCX_I64 <"v_cmpx_ge_i64">;
-defm V_CMPX_T_I64 : VOPCX_I64 <"v_cmpx_t_i64">;
+defm V_CMP_F_I64 : VOPC_I64_Signed <"v_cmp_f_i64">;
+defm V_CMP_LT_I64 : VOPC_I64_Signed <"v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
+defm V_CMP_EQ_I64 : VOPC_I64_Signed <"v_cmp_eq_i64">;
+defm V_CMP_LE_I64 : VOPC_I64_Signed <"v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
+defm V_CMP_GT_I64 : VOPC_I64_Signed <"v_cmp_gt_i64", COND_SGT>;
+defm V_CMP_NE_I64 : VOPC_I64_Signed <"v_cmp_ne_i64">;
+defm V_CMP_GE_I64 : VOPC_I64_Signed <"v_cmp_ge_i64", COND_SGE>;
+defm V_CMP_T_I64 : VOPC_I64_Signed <"v_cmp_t_i64">;
+
+defm V_CMPX_F_I64 : VOPCX_I64_Signed <"v_cmpx_f_i64">;
+defm V_CMPX_LT_I64 : VOPCX_I64_Signed <"v_cmpx_lt_i64", "v_cmpx_gt_i64">;
+defm V_CMPX_EQ_I64 : VOPCX_I64_Signed <"v_cmpx_eq_i64">;
+defm V_CMPX_LE_I64 : VOPCX_I64_Signed <"v_cmpx_le_i64", "v_cmpx_ge_i64">;
+defm V_CMPX_GT_I64 : VOPCX_I64_Signed <"v_cmpx_gt_i64">;
+defm V_CMPX_NE_I64 : VOPCX_I64_Signed <"v_cmpx_ne_i64">;
+defm V_CMPX_GE_I64 : VOPCX_I64_Signed <"v_cmpx_ge_i64">;
+defm V_CMPX_T_I64 : VOPCX_I64_Signed <"v_cmpx_t_i64">;
defm V_CMP_F_U32 : VOPC_I32 <"v_cmp_f_u32">;
defm V_CMP_LT_U32 : VOPC_I32 <"v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
index cd4eefa846e57..6bfc604e03e7c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
@@ -128,11 +128,9 @@ define i16 @v_clamp_i64_i16_invalid_lower(i64 %in) #0 {
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0x8001, v[0:1]
-; GFX10-NEXT: v_mov_b32_e32 v2, 0xffff8000
-; GFX10-NEXT: v_mov_b32_e32 v3, -1
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x8001, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0xffffffffffff8000, v[0:1]
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0xffff8000, v0, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -140,10 +138,9 @@ define i16 @v_clamp_i64_i16_invalid_lower(i64 %in) #0 {
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0x8001, v[0:1]
-; GFX11-NEXT: v_dual_mov_b32 v2, 0xffff8000 :: v_dual_mov_b32 v3, -1
; GFX11-NEXT: v_dual_cndmask_b32 v0, 0x8001, v0 :: v_dual_cndmask_b32 v1, 0, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0xffffffffffff8000, v[0:1]
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0xffff8000, v0, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -189,9 +186,7 @@ define i16 @v_clamp_i64_i16_invalid_lower_and_higher(i64 %in) #0 {
; GFX10-LABEL: v_clamp_i64_i16_invalid_lower_and_higher:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v2, 0xffff7fff
-; GFX10-NEXT: v_mov_b32_e32 v3, -1
-; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0xffffffffffff7fff, v[0:1]
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0xffff7fff, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, -1, v1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0x8000, v[0:1]
@@ -201,10 +196,9 @@ define i16 @v_clamp_i64_i16_invalid_lower_and_higher(i64 %in) #0 {
; GFX11-LABEL: v_clamp_i64_i16_invalid_lower_and_higher:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v2, 0xffff7fff :: v_dual_mov_b32 v3, -1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0xffffffffffff7fff, v[0:1]
; GFX11-NEXT: v_dual_cndmask_b32 v0, 0xffff7fff, v0 :: v_dual_cndmask_b32 v1, -1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0x8000, v[0:1]
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x8000, v0, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
>From e0b45b9c3993e5adf6700a418ab04657b11793e1 Mon Sep 17 00:00:00 2001
From: addmisol <addmisol9 at gmail.com>
Date: Sat, 29 Aug 2026 22:21:37 +0530
Subject: [PATCH 3/5] Fix issues
Signed-off-by: addmisol <addmisol9 at gmail.com>
---
.../AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 16 +++++++++-------
llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s | 1 -
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index dff92b2a57360..6d3ef835da523 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -262,14 +262,16 @@ static uint32_t getLit64Encoding(const MCInstrDesc &Desc, uint64_t Val,
// The rest part needs to align with AMDGPUInstPrinter::printLiteral64.
- bool CanUse64BitLiterals = STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
- !SIInstrFlags::isVOP3Like(Desc);
- if (IsFP) {
- return CanUse64BitLiterals && Lo_32(Val) ? 254 : 255;
- }
+ auto Needs64BitLiteral = [&]() {
+ if (!STI.hasFeature(AMDGPU::Feature64BitLiterals) ||
+ SIInstrFlags::isVOP3Like(Desc))
+ return false;
+ if (IsFP)
+ return Lo_32(Val) != 0;
+ return !isInt<32>(Val) || !isUInt<32>(Val);
+ };
- return CanUse64BitLiterals && (!isInt<32>(Val) || !isUInt<32>(Val)) ? 254
- : 255;
+ return Needs64BitLiteral() ? 254 : 255;
}
std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
index 09e4719c0c8cd..17b904af62078 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
@@ -26,7 +26,6 @@ v_mov_b64 v[4:5], -1
v_mov_b64 v[4:5], 0.5
// GFX1250: v_mov_b64_e32 v[4:5], 0.5 ; encoding: [0xf0,0x3a,0x08,0x7e]
-// TODO: Encode as a 32-bit literal unless lit64() is specified.
v_mov_b64 v[254:255], 0xaf123456
// GFX1250-ASM: v_mov_b64_e32 v[254:255], 0xaf123456 ; encoding: [0xfe,0x3a,0xfc,0x7f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00]
// GFX1250-DIS: v_mov_b64_e32 v[254:255], lit64(0xaf123456) ; encoding: [0xfe,0x3a,0xfc,0x7f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00]
>From a45851c83548f24deafe4a295d26ccc5d289f41e Mon Sep 17 00:00:00 2001
From: addmisol <addmisol9 at gmail.com>
Date: Sun, 30 Aug 2026 07:47:47 +0530
Subject: [PATCH 4/5] fix : folding-of-i32-as-i64.mir tests check
Signed-off-by: addmisol <addmisol9 at gmail.com>
---
llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir b/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
index 781678e9e94ae..ea12f0db9e36d 100644
--- a/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
+++ b/llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
@@ -90,7 +90,8 @@ name: imm64_ashr_int32_const_0xffffffff
body: |
bb.0:
; GCN-LABEL: name: imm64_ashr_int32_const_0xffffffff
- ; GCN: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 4294967295, 1, implicit-def $scc
+ ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
+ ; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[S_MOV_B]], 1, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
%1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
>From bb8f1ccdcf783b36d86e957e93495b7cf43bbbc8 Mon Sep 17 00:00:00 2001
From: Addmisol <addmisol9 at gmail.com>
Date: Sun, 30 Aug 2026 08:33:23 +0530
Subject: [PATCH 5/5] fix : code formatter issues
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index eb1b264b4191c..d4ba0240de7a7 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6777,7 +6777,8 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
// correctly sign extended or incorrectly zero extended by HW.
// If 64-bit literals are supported and the literal will be encoded
// as full 64 bit we still can use it.
- if (!Is64BitFPOp && !Is64BitSignedOp && !Is64BitUnsignedOp && (int32_t)Imm < 0 &&
+ if (!Is64BitFPOp && !Is64BitSignedOp && !Is64BitUnsignedOp &&
+ (int32_t)Imm < 0 &&
(!ST.has64BitLiterals() || AMDGPU::isValid32BitLiteral(Imm, false)))
return false;
}
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