[llvm] [AMDGPU] Carry the log expansion flags through its f32 round trip (PR #219724)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-globalisel

Author: Dmitry Sidorov (MrSidims)

<details>
<summary>Changes</summary>

The f16 log and log10 expansion promotes to f32 and rounds back. GlobalISel built that G_FPEXT and G_FPTRUNC pair with no flags at all, where the SelectionDAG FP_EXTEND and FP_ROUND have always carried them, so hand them the expansion's flags too.

---
Full diff: https://github.com/llvm/llvm-project/pull/219724.diff


3 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir (+28) 
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir (+28) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 7c1a26f761c96..5e3e7ca8e4e0d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -3748,9 +3748,9 @@ bool AMDGPULegalizerInfo::legalizeFlogCommon(MachineInstr &MI,
         Ty == F16 && (!MI.getFlag(MachineInstr::FmAfn) || !ST.has16BitInsts());
     if (PromoteToF32) {
       Register LogVal = MRI.createGenericVirtualRegister(F32);
-      auto PromoteSrc = B.buildFPExt(F32, X);
+      auto PromoteSrc = B.buildFPExt(F32, X, Flags);
       legalizeFlogUnsafe(B, LogVal, PromoteSrc.getReg(0), IsLog10, Flags);
-      B.buildFPTrunc(Dst, LogVal);
+      B.buildFPTrunc(Dst, LogVal, Flags);
     } else {
       legalizeFlogUnsafe(B, Dst, X, IsLog10, Flags);
     }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
index 9c5c243a76138..668892f26e64d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
@@ -227,6 +227,34 @@ body: |
 
 ...
 
+---
+name: test_flog_f16_contract
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_flog_f16_contract
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+    ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = contract G_FPEXT [[TRUNC]](f16)
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = contract G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](f32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3F317218
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = contract G_FMUL [[INT]], [[C]]
+    ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = contract G_FPTRUNC [[FMUL]](f32)
+    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+    %0:_(i32) = COPY $vgpr0
+    %1:_(i16) = G_TRUNC %0
+    %2:_(f16) = G_BITCAST %1
+    %3:_(f16) = contract G_FLOG %2
+    %4:_(i16) = G_BITCAST %3
+    %5:_(i32) = G_ANYEXT %4
+    $vgpr0 = COPY %5
+
+...
+
 ---
 name: test_flog_v2f16
 body: |
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
index bd5a8fea2b6c2..f2951ef0e35fe 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
@@ -227,6 +227,34 @@ body: |
 
 ...
 
+---
+name: test_flog10_f16_contract
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_flog10_f16_contract
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+    ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = contract G_FPEXT [[TRUNC]](f16)
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = contract G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](f32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.010300e-01
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = contract G_FMUL [[INT]], [[C]]
+    ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = contract G_FPTRUNC [[FMUL]](f32)
+    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+    %0:_(i32) = COPY $vgpr0
+    %1:_(i16) = G_TRUNC %0
+    %2:_(f16) = G_BITCAST %1
+    %3:_(f16) = contract G_FLOG10 %2
+    %4:_(i16) = G_BITCAST %3
+    %5:_(i32) = G_ANYEXT %4
+    $vgpr0 = COPY %5
+
+...
+
 ---
 name: test_flog10_v2f16
 body: |

``````````

</details>


https://github.com/llvm/llvm-project/pull/219724