[llvm] [X86] Prefer sub-of-not for vector inc-of-add (PR #207695)

[Rohan Shenoy via llvm-commits]

================
@@ -101,9 +101,10 @@ define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
 define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
 ; ALL-LABEL: vector_i128_i8:
 ; ALL:       # %bb.0:
-; ALL-NEXT:    paddb %xmm1, %xmm0
-; ALL-NEXT:    pcmpeqd %xmm1, %xmm1
-; ALL-NEXT:    psubb %xmm1, %xmm0
+; ALL-NEXT:    pcmpeqd %xmm2, %xmm2
+; ALL-NEXT:    pxor %xmm0, %xmm2
+; ALL-NEXT:    psubb %xmm2, %xmm1
+; ALL-NEXT:    movdqa %xmm1, %xmm0
----------------
222rohan wrote:

To add to this, that extra mov can be removed if x and y were swapped here in DAGCombiner.cpp:3157 , but this would affect other targets. Do you think this is a change worth doing? @RKSimon @Andarwinux 

```cpp
    // Look for:
    //   add (add x, y), 1
    // And if the target does not like this form then turn into:
    //   sub y, (xor x, -1)
    if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD &&
        N0.hasOneUse() &&
        // Limit this to after legalization if the add has wrap flags
        (Level >= AfterLegalizeDAG || (!N->getFlags().hasNoUnsignedWrap() &&
                                       !N->getFlags().hasNoSignedWrap()))) {
      SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT);
      return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(1), Not);
    }
  }
```

https://github.com/llvm/llvm-project/pull/207695