[llvm] 2cba3ad - GlobalISel: Replace MachineOperand based register constraint API (#219283)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 29 00:44:20 PDT 2026
Author: Matt Arsenault
Date: 2026-08-29T09:44:15+02:00
New Revision: 2cba3ad3296c32ab512b282db5893c68b6f91d24
URL: https://github.com/llvm/llvm-project/commit/2cba3ad3296c32ab512b282db5893c68b6f91d24
DIFF: https://github.com/llvm/llvm-project/commit/2cba3ad3296c32ab512b282db5893c68b6f91d24.diff
LOG: GlobalISel: Replace MachineOperand based register constraint API (#219283)
Added:
Modified:
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/lib/CodeGen/GlobalISel/Utils.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.h
llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index dc677d47d30bf..dacd5fb575a4d 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1090,8 +1090,8 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
virtual const TargetRegisterClass *
- getConstrainedRegClassForOperand(const MachineOperand &MO,
- const MachineRegisterInfo &MRI) const {
+ getConstrainedRegClassForReg(Register Reg,
+ const MachineRegisterInfo &MRI) const {
return nullptr;
}
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 36e427188c0b5..c9f5c6248d1f1 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -130,7 +130,7 @@ Register llvm::constrainOperandRegClass(
// register types (E.g., AMDGPU's VGPR and AGPR). The regbank ambiguity
// resolved by targets during regbankselect should not be overridden.
if (const auto *SubRC = TRI.getCommonSubClass(
- OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI)))
+ OpRC, TRI.getConstrainedRegClassForReg(Reg, MRI)))
OpRC = SubRC;
OpRC = TRI.getAllocatableClass(OpRC);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index f37e08ca19fb5..353506378b229 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -100,22 +100,22 @@ bool AMDGPUInstructionSelector::constrainCopyLikeIntrin(MachineInstr &MI,
MI.removeOperand(1); // Remove intrinsic ID.
MI.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
- MachineOperand &Dst = MI.getOperand(0);
- MachineOperand &Src = MI.getOperand(1);
+ Register DstReg = MI.getOperand(0).getReg();
+ Register SrcReg = MI.getOperand(1).getReg();
// TODO: This should be legalized to s32 if needed
- if (MRI->getType(Dst.getReg()) == LLT::scalar(1))
+ if (MRI->getType(DstReg) == LLT::scalar(1))
return false;
- const TargetRegisterClass *DstRC
- = TRI.getConstrainedRegClassForOperand(Dst, *MRI);
- const TargetRegisterClass *SrcRC
- = TRI.getConstrainedRegClassForOperand(Src, *MRI);
+ const TargetRegisterClass *DstRC =
+ TRI.getConstrainedRegClassForReg(DstReg, *MRI);
+ const TargetRegisterClass *SrcRC =
+ TRI.getConstrainedRegClassForReg(SrcReg, *MRI);
if (!DstRC || DstRC != SrcRC)
return false;
- if (!RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) ||
- !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI))
+ if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||
+ !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
return false;
const MCInstrDesc &MCID = MI.getDesc();
if (MCID.getOperandConstraint(0, MCOI::EARLY_CLOBBER) != -1) {
@@ -129,15 +129,13 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
MachineBasicBlock *BB = I.getParent();
I.setDesc(TII.get(TargetOpcode::COPY));
- const MachineOperand &Src = I.getOperand(1);
- MachineOperand &Dst = I.getOperand(0);
- Register DstReg = Dst.getReg();
- Register SrcReg = Src.getReg();
+ Register DstReg = I.getOperand(0).getReg();
+ Register SrcReg = I.getOperand(1).getReg();
if (isVCC(DstReg, *MRI)) {
if (SrcReg == AMDGPU::SCC) {
- const TargetRegisterClass *RC
- = TRI.getConstrainedRegClassForOperand(Dst, *MRI);
+ const TargetRegisterClass *RC =
+ TRI.getConstrainedRegClassForReg(DstReg, *MRI);
if (!RC)
return true;
return RBI.constrainGenericRegister(DstReg, *RC, *MRI);
@@ -148,8 +146,8 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI))
return false;
- const TargetRegisterClass *SrcRC
- = TRI.getConstrainedRegClassForOperand(Src, *MRI);
+ const TargetRegisterClass *SrcRC =
+ TRI.getConstrainedRegClassForReg(SrcReg, *MRI);
std::optional<ValueAndVReg> ConstVal =
getIConstantVRegValWithLookThrough(SrcReg, *MRI, true);
@@ -202,7 +200,7 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
}
const TargetRegisterClass *RC =
- TRI.getConstrainedRegClassForOperand(Dst, *MRI);
+ TRI.getConstrainedRegClassForReg(DstReg, *MRI);
if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI))
return false;
@@ -214,7 +212,7 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
continue;
const TargetRegisterClass *RC =
- TRI.getConstrainedRegClassForOperand(MO, *MRI);
+ TRI.getConstrainedRegClassForReg(MO.getReg(), *MRI);
if (!RC)
continue;
RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI);
@@ -637,7 +635,7 @@ bool AMDGPUInstructionSelector::selectG_EXTRACT(MachineInstr &I) const {
DstSize = 32;
const TargetRegisterClass *DstRC =
- TRI.getConstrainedRegClassForOperand(I.getOperand(0), *MRI);
+ TRI.getConstrainedRegClassForReg(DstReg, *MRI);
if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
return false;
@@ -845,12 +843,13 @@ bool AMDGPUInstructionSelector::selectG_MERGE_VALUES(MachineInstr &MI) const {
BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::REG_SEQUENCE), DstReg);
for (int I = 0, E = MI.getNumOperands() - 1; I != E; ++I) {
MachineOperand &Src = MI.getOperand(I + 1);
- MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()));
+ Register SrcReg = Src.getReg();
+ MIB.addReg(SrcReg, getUndefRegState(Src.isUndef()));
MIB.addImm(SubRegs[I]);
- const TargetRegisterClass *SrcRC
- = TRI.getConstrainedRegClassForOperand(Src, *MRI);
- if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI))
+ const TargetRegisterClass *SrcRC =
+ TRI.getConstrainedRegClassForReg(SrcReg, *MRI);
+ if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
return false;
}
@@ -887,15 +886,15 @@ bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
// used for both.
ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8);
for (int I = 0, E = NumDst; I != E; ++I) {
- MachineOperand &Dst = MI.getOperand(I);
+ Register DstReg = MI.getOperand(I).getReg();
// hi16:sreg_32 is not allowed so explicitly shift upper 16-bits.
if (SrcBank->getID() == AMDGPU::SGPRRegBankID &&
SubRegs[I] == AMDGPU::hi16) {
- BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst.getReg())
+ BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), DstReg)
.addReg(SrcReg)
.addImm(16);
} else {
- BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
+ BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), DstReg)
.addReg(SrcReg, {}, SubRegs[I]);
}
@@ -905,8 +904,8 @@ bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
return false;
const TargetRegisterClass *DstRC =
- TRI.getConstrainedRegClassForOperand(Dst, *MRI);
- if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI))
+ TRI.getConstrainedRegClassForReg(DstReg, *MRI);
+ if (DstRC && !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
return false;
}
@@ -997,9 +996,10 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const {
bool AMDGPUInstructionSelector::selectG_IMPLICIT_DEF(MachineInstr &I) const {
const MachineOperand &MO = I.getOperand(0);
- // FIXME: Interface for getConstrainedRegClassForOperand needs work. The
- // regbank check here is to know why getConstrainedRegClassForOperand failed.
- const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, *MRI);
+ // FIXME: Interface for getConstrainedRegClassForReg needs work. The
+ // regbank check here is to know why getConstrainedRegClassForReg failed.
+ const TargetRegisterClass *RC =
+ TRI.getConstrainedRegClassForReg(MO.getReg(), *MRI);
if ((!RC && !MRI->getRegBankOrNull(MO.getReg())) ||
(RC && RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI))) {
I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
@@ -1783,12 +1783,11 @@ bool AMDGPUInstructionSelector::selectReturnAddress(MachineInstr &I) const {
MachineFunction &MF = *MBB->getParent();
const DebugLoc &DL = I.getDebugLoc();
- MachineOperand &Dst = I.getOperand(0);
- Register DstReg = Dst.getReg();
+ Register DstReg = I.getOperand(0).getReg();
unsigned Depth = I.getOperand(2).getImm();
- const TargetRegisterClass *RC
- = TRI.getConstrainedRegClassForOperand(Dst, *MRI);
+ const TargetRegisterClass *RC =
+ TRI.getConstrainedRegClassForReg(DstReg, *MRI);
if (!RC->hasSubClassEq(&AMDGPU::SGPR_64RegClass) ||
!RBI.constrainGenericRegister(DstReg, *RC, *MRI))
return false;
@@ -2502,7 +2501,7 @@ bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
// bank, because it does not cover the register class that we used to represent
// for it. So we need to manually set the register class here.
if (!MRI->getRegClassOrNull(CCReg))
- MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI));
+ MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForReg(CCReg, *MRI));
MachineInstr *Select = BuildMI(*BB, &I, DL, TII.get(SelectOpcode), DstReg)
.add(I.getOperand(2))
.add(I.getOperand(3));
@@ -7275,7 +7274,7 @@ bool AMDGPUInstructionSelector::selectSGetBarrierState(
auto DstReg = I.getOperand(0).getReg();
const TargetRegisterClass *DstRC =
- TRI.getConstrainedRegClassForOperand(I.getOperand(0), *MRI);
+ TRI.getConstrainedRegClassForReg(DstReg, *MRI);
if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
return false;
MIB.addDef(DstReg);
@@ -7420,7 +7419,7 @@ bool AMDGPUInstructionSelector::selectNamedBarrierInst(
if (IntrID == Intrinsic::amdgcn_s_get_named_barrier_state) {
auto DstReg = I.getOperand(0).getReg();
const TargetRegisterClass *DstRC =
- TRI.getConstrainedRegClassForOperand(I.getOperand(0), *MRI);
+ TRI.getConstrainedRegClassForReg(DstReg, *MRI);
if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
return false;
MIB.addDef(DstReg);
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 2b0d9fd380793..efbd366ea8a85 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -4197,12 +4197,11 @@ SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
}
}
-const TargetRegisterClass *
-SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
- const MachineRegisterInfo &MRI) const {
- const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
+const TargetRegisterClass *SIRegisterInfo::getConstrainedRegClassForReg(
+ Register Reg, const MachineRegisterInfo &MRI) const {
+ const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg);
if (const RegisterBank *RB = dyn_cast<const RegisterBank *>(RCOrRB))
- return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB);
+ return getRegClassForTypeOnBank(MRI.getType(Reg), *RB);
if (const auto *RC = dyn_cast<const TargetRegisterClass *>(RCOrRB))
return getAllocatableClass(RC);
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index e464c9334ffea..296389ed88915 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -377,8 +377,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
}
const TargetRegisterClass *
- getConstrainedRegClassForOperand(const MachineOperand &MO,
- const MachineRegisterInfo &MRI) const override;
+ getConstrainedRegClassForReg(Register Reg,
+ const MachineRegisterInfo &MRI) const override;
const TargetRegisterClass *getBoolRC() const {
return isWave32 ? &AMDGPU::SReg_32RegClass
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index bf31c9a9d1e9e..fcbdaabee1e1e 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1688,14 +1688,13 @@ bool RISCVInstructionSelector::isRegInFprb(Register Reg) const {
}
bool RISCVInstructionSelector::selectCopy(MachineInstr &MI) const {
- MachineOperand Dst = MI.getOperand(0);
Register DstReg = MI.getOperand(0).getReg();
if (DstReg.isPhysical())
return true;
const TargetRegisterClass *DstRC =
- TRI.getConstrainedRegClassForOperand(Dst, *MRI);
+ TRI.getConstrainedRegClassForReg(DstReg, *MRI);
assert(DstRC &&
"Register class not available for LLT, register bank combination");
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index f51f56cb10a46..adc6eadee2e35 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -120,14 +120,13 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
}
}
-const TargetRegisterClass *RISCVRegisterInfo::getConstrainedRegClassForOperand(
- const MachineOperand &MO, const MachineRegisterInfo &MRI) const {
+const TargetRegisterClass *RISCVRegisterInfo::getConstrainedRegClassForReg(
+ Register Reg, const MachineRegisterInfo &MRI) const {
const RISCVSubtarget &STI = MRI.getMF().getSubtarget<RISCVSubtarget>();
- const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
+ const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg);
if (const RegisterBank *RB = dyn_cast<const RegisterBank *>(RCOrRB))
- return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB,
- STI.is64Bit());
+ return getRegClassForTypeOnBank(MRI.getType(Reg), *RB, STI.is64Bit());
if (const auto *RC = dyn_cast<const TargetRegisterClass *>(RCOrRB)) {
return getAllocatableClass(RC);
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index 625c19b3a02fd..de24178acca45 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -77,8 +77,9 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
- const TargetRegisterClass *getConstrainedRegClassForOperand(
- const MachineOperand &MO, const MachineRegisterInfo &MRI) const override;
+ const TargetRegisterClass *
+ getConstrainedRegClassForReg(Register Reg,
+ const MachineRegisterInfo &MRI) const override;
const TargetRegisterClass *
getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, bool Is64Bit) const;
diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
index b5d0d68514e8e..1883d8ae33f33 100644
--- a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
+++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
@@ -119,19 +119,19 @@ WebAssemblyInstructionSelector::selectAddrOperands64(
bool WebAssemblyInstructionSelector::selectCopy(
MachineInstr &I, MachineRegisterInfo &MRI) const {
+ Register DstReg = I.getOperand(0).getReg();
+ Register SrcReg = I.getOperand(1).getReg();
+
const TargetRegisterClass *DstRC =
- TRI.getConstrainedRegClassForOperand(I.getOperand(0), MRI);
+ TRI.getConstrainedRegClassForReg(DstReg, MRI);
if (!DstRC)
return false;
const TargetRegisterClass *SrcRC =
- TRI.getConstrainedRegClassForOperand(I.getOperand(1), MRI);
+ TRI.getConstrainedRegClassForReg(SrcReg, MRI);
if (!SrcRC)
return false;
- Register DstReg = I.getOperand(0).getReg();
- Register SrcReg = I.getOperand(1).getReg();
-
if (DstReg.isVirtual())
RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
if (SrcReg.isVirtual())
@@ -191,7 +191,7 @@ bool WebAssemblyInstructionSelector::select(MachineInstr &I) {
const Register DefReg = I.getOperand(0).getReg();
const TargetRegisterClass *DefRC =
- TRI.getConstrainedRegClassForOperand(I.getOperand(0), MRI);
+ TRI.getConstrainedRegClassForReg(DefReg, MRI);
if (!DefRC)
return false;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
index 0c8241461f805..0472851543168 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
@@ -180,12 +180,8 @@ static const TargetRegisterClass &getRegClassForBank(const RegisterBank &RB) {
}
const TargetRegisterClass *
-WebAssemblyRegisterInfo::getConstrainedRegClassForOperand(
- const MachineOperand &MO, const MachineRegisterInfo &MRI) const {
- assert(MO.isReg());
-
- Register Reg = MO.getReg();
-
+WebAssemblyRegisterInfo::getConstrainedRegClassForReg(
+ Register Reg, const MachineRegisterInfo &MRI) const {
if (Reg.isPhysical()) {
switch (Reg.id()) {
case WebAssembly::SP32:
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
index ffff5d1d96397..325f412bfc78a 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
@@ -47,8 +47,9 @@ class WebAssemblyRegisterInfo final : public WebAssemblyGenRegisterInfo {
// This does not apply to wasm.
const uint32_t *getNoPreservedMask() const override { return nullptr; }
- const TargetRegisterClass *getConstrainedRegClassForOperand(
- const MachineOperand &MO, const MachineRegisterInfo &MRI) const override;
+ const TargetRegisterClass *
+ getConstrainedRegClassForReg(Register Reg,
+ const MachineRegisterInfo &MRI) const override;
};
} // end namespace llvm
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