[llvm] [RISCV] Lower vector UINT_TO_FP i1 to VSELECT 1.0/0.0 (PR #219426)
Liao Chunyu via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 28 18:48:51 PDT 2026
https://github.com/ChunyuLiao updated https://github.com/llvm/llvm-project/pull/219426
>From 9dc505673d379a492293373e58a6381ed8822b69 Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Thu, 27 Aug 2026 09:50:56 +0000
Subject: [PATCH 1/2] [RISCV] Lower vector UINT_TO_FP i1 to VSELECT 1.0/0.0
Previously, the i1 source was first zero-extended to an
integer type whose width is half the destination floating-point width.
The mask extension was lowered by lowerVectorMaskExt to a VSELECT, or
directly to VMERGE_VL for fixed-length vectors, materializing an integer
vector containing 0 or 1.
Since an unsigned i1-to-floating-point conversion can only produce 0.0
or 1.0, recognize this operation earlier and lower it directly to a
VSELECT between the floating-point constants 1.0 and 0.0. This removes
the intermediate integer mask extension and the following widening
integer-to-floating-point conversion.
half: https://alive2.llvm.org/ce/z/kxRon2
float: https://alive2.llvm.org/ce/z/U6py8U
double: https://alive2.llvm.org/ce/z/pe5B5N
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 +
.../CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll | 124 +++---
.../RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll | 78 ++--
llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll | 370 ++++++++++--------
.../test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll | 100 +++--
5 files changed, 411 insertions(+), 271 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9b80e1f304b3e..0035cdd08bfb8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8521,6 +8521,16 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return lowerStrictFPExtendOrRoundLike(Op, DAG);
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
+ // An unsigned i1-to-fp conversion is equivalent to selecting between
+ // 1.0 and 0.0. This avoids extending the mask before converting it.
+ if (Op.getOpcode() == ISD::UINT_TO_FP && Op.getValueType().isVector() &&
+ Op.getOperand(0).getValueType().getVectorElementType() == MVT::i1) {
+ SDLoc DL(Op);
+ EVT VT = Op.getValueType();
+ SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
+ SDValue One = DAG.getConstantFP(1.0, DL, VT);
+ return DAG.getNode(ISD::VSELECT, DL, VT, Op.getOperand(0), One, Zero);
+ }
// Fall back to zvfbfmin for bf16 case if source type is wider than 8 bits.
if (SDValue Op1 = Op.getOperand(0);
Op.getValueType().isVector() &&
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
index 842e967b468ea..f4a63709d3e65 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
@@ -77,10 +77,10 @@ define <2 x float> @ui2fp_v2i7_v2f32(<2 x i7> %x) {
define <2 x float> @ui2fp_v2i1_v2f32(<2 x i1> %x) {
; CHECK-LABEL: ui2fp_v2i1_v2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%z = uitofp <2 x i1> %x to <2 x float>
ret <2 x float> %z
@@ -275,10 +275,10 @@ define <3 x float> @ui2fp_v3i7_v3f32(<3 x i7> %x) {
define <3 x float> @ui2fp_v3i1_v3f32(<3 x i1> %x) {
; CHECK-LABEL: ui2fp_v3i1_v3f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%z = uitofp <3 x i1> %x to <3 x float>
ret <3 x float> %z
@@ -327,10 +327,10 @@ define <8 x float> @si2fp_v8i1_v8f32(<8 x i1> %x) {
define <8 x float> @ui2fp_v8i1_v8f32(<8 x i1> %x) {
; CHECK-LABEL: ui2fp_v8i1_v8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%z = uitofp <8 x i1> %x to <8 x float>
ret <8 x float> %z
@@ -409,13 +409,41 @@ define <8 x double> @si2fp_v8i1_v8f64(<8 x i1> %x) {
}
define <8 x double> @ui2fp_v8i1_v8f64(<8 x i1> %x) {
-; CHECK-LABEL: ui2fp_v8i1_v8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v12, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v12
-; CHECK-NEXT: ret
+; ZVFH32-LABEL: ui2fp_v8i1_v8f64:
+; ZVFH32: # %bb.0:
+; ZVFH32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; ZVFH32-NEXT: vmv.v.i v8, 0
+; ZVFH32-NEXT: lui a0, %hi(.LCPI21_0)
+; ZVFH32-NEXT: fld fa5, %lo(.LCPI21_0)(a0)
+; ZVFH32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; ZVFH32-NEXT: ret
+;
+; ZVFH64-LABEL: ui2fp_v8i1_v8f64:
+; ZVFH64: # %bb.0:
+; ZVFH64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; ZVFH64-NEXT: vmv.v.i v8, 0
+; ZVFH64-NEXT: li a0, 1023
+; ZVFH64-NEXT: slli a0, a0, 52
+; ZVFH64-NEXT: vmerge.vxm v8, v8, a0, v0
+; ZVFH64-NEXT: ret
+;
+; ZVFHMIN32-LABEL: ui2fp_v8i1_v8f64:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; ZVFHMIN32-NEXT: vmv.v.i v8, 0
+; ZVFHMIN32-NEXT: lui a0, %hi(.LCPI21_0)
+; ZVFHMIN32-NEXT: fld fa5, %lo(.LCPI21_0)(a0)
+; ZVFHMIN32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: ui2fp_v8i1_v8f64:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; ZVFHMIN64-NEXT: vmv.v.i v8, 0
+; ZVFHMIN64-NEXT: li a0, 1023
+; ZVFHMIN64-NEXT: slli a0, a0, 52
+; ZVFHMIN64-NEXT: vmerge.vxm v8, v8, a0, v0
+; ZVFHMIN64-NEXT: ret
%z = uitofp <8 x i1> %x to <8 x double>
ret <8 x double> %z
}
@@ -496,19 +524,21 @@ define <2 x bfloat> @si2fp_v2i1_v2bf16(<2 x i1> %x) {
define <2 x bfloat> @ui2fp_v2i1_v2bf16(<2 x i1> %x) {
; ZVFBFMIN-LABEL: ui2fp_v2i1_v2bf16:
; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 4
+; ZVFBFMIN-NEXT: addi a0, a0, -128
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v9, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v9, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: ui2fp_v2i1_v2bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v9, v8, 1, v0
-; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA-NEXT: lui a0, 4
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%z = uitofp <2 x i1> %x to <2 x bfloat>
ret <2 x bfloat> %z
@@ -590,19 +620,21 @@ define <8 x bfloat> @si2fp_v8i1_v8bf16(<8 x i1> %x) {
define <8 x bfloat> @ui2fp_v8i1_v8bf16(<8 x i1> %x) {
; ZVFBFMIN-LABEL: ui2fp_v8i1_v8bf16:
; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 4
+; ZVFBFMIN-NEXT: addi a0, a0, -128
; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v10, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v9, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: ui2fp_v8i1_v8bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 8, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v9, v8, 1, v0
-; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA-NEXT: lui a0, 4
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%z = uitofp <8 x i1> %x to <8 x bfloat>
ret <8 x bfloat> %z
@@ -900,19 +932,21 @@ define <2 x half> @si2fp_v2i1_v2f16(<2 x i1> %x) {
define <2 x half> @ui2fp_v2i1_v2f16(<2 x i1> %x) {
; ZVFH-LABEL: ui2fp_v2i1_v2f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v9, v8, 1, v0
-; ZVFH-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFH-NEXT: li a0, 15
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: ui2fp_v2i1_v2f16:
; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a0, 15
+; ZVFHMIN-NEXT: slli a0, a0, 10
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.xu.v v9, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: ret
%z = uitofp <2 x i1> %x to <2 x half>
ret <2 x half> %z
@@ -974,19 +1008,21 @@ define <8 x half> @si2fp_v8i1_v8f16(<8 x i1> %x) {
define <8 x half> @ui2fp_v8i1_v8f16(<8 x i1> %x) {
; ZVFH-LABEL: ui2fp_v8i1_v8f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v9, v8, 1, v0
-; ZVFH-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFH-NEXT: li a0, 15
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: ui2fp_v8i1_v8f16:
; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a0, 15
+; ZVFHMIN-NEXT: slli a0, a0, 10
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.xu.v v10, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: ret
%z = uitofp <8 x i1> %x to <8 x half>
ret <8 x half> %z
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
index e24e871a450b9..c6f7c19253734 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
@@ -1,14 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <4 x half> @vuitofp_v4f16_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_v4f16_v4i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
ret <4 x half> %v
@@ -17,10 +18,11 @@ define <4 x half> @vuitofp_v4f16_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %ev
define <4 x half> @vuitofp_v4f16_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_v4f16_v4i1_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
ret <4 x half> %v
@@ -29,10 +31,10 @@ define <4 x half> @vuitofp_v4f16_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
define <4 x float> @vuitofp_v4f32_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_v4f32_v4i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
ret <4 x float> %v
@@ -41,35 +43,55 @@ define <4 x float> @vuitofp_v4f32_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %e
define <4 x float> @vuitofp_v4f32_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_v4f32_v4i1_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
ret <4 x float> %v
}
define <4 x double> @vuitofp_v4f64_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vuitofp_v4f64_v4i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vuitofp_v4f64_v4i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI4_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI4_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vuitofp_v4f64_v4i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, 1023
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
ret <4 x double> %v
}
define <4 x double> @vuitofp_v4f64_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vuitofp_v4f64_v4i1_unmasked:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vuitofp_v4f64_v4i1_unmasked:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI5_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI5_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vuitofp_v4f64_v4i1_unmasked:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, 1023
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
ret <4 x double> %v
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
index 7616fad33126a..f3dfeeb9abeeb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
@@ -1,22 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFBFMIN,ZVFH
+; RUN: --check-prefixes=CHECK,RV32,ZVFBFMIN,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFBFMIN,ZVFH
+; RUN: --check-prefixes=CHECK,RV64,ZVFBFMIN,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN
+; RUN: --check-prefixes=CHECK,RV32,ZVFBFMIN,ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN
+; RUN: --check-prefixes=CHECK,RV64,ZVFBFMIN,ZVFHMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+experimental-zvfbfa \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
+; RUN: --check-prefixes=CHECK,RV32,ZVFHMIN,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+experimental-zvfbfa \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
+; RUN: --check-prefixes=CHECK,RV64,ZVFHMIN,ZVFBFA
define <vscale x 1 x bfloat> @vsitofp_nxv1i1_nxv1bf16(<vscale x 1 x i1> %va) {
; ZVFBFMIN-LABEL: vsitofp_nxv1i1_nxv1bf16:
@@ -42,19 +42,21 @@ define <vscale x 1 x bfloat> @vsitofp_nxv1i1_nxv1bf16(<vscale x 1 x i1> %va) {
define <vscale x 1 x bfloat> @vuitofp_nxv1i1_nxv1bf16(<vscale x 1 x i1> %va) {
; ZVFBFMIN-LABEL: vuitofp_nxv1i1_nxv1bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v9, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: lui a0, 4
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v9, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vuitofp_nxv1i1_nxv1bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v9, v8, 1, v0
-; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA-NEXT: lui a0, 4
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
@@ -84,19 +86,21 @@ define <vscale x 2 x bfloat> @vsitofp_nxv2i1_nxv2bf16(<vscale x 2 x i1> %va) {
define <vscale x 2 x bfloat> @vuitofp_nxv2i1_nxv2bf16(<vscale x 2 x i1> %va) {
; ZVFBFMIN-LABEL: vuitofp_nxv2i1_nxv2bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v9, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: lui a0, 4
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v9, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vuitofp_nxv2i1_nxv2bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v9, v8, 1, v0
-; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA-NEXT: lui a0, 4
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
@@ -126,19 +130,21 @@ define <vscale x 4 x bfloat> @vsitofp_nxv4i1_nxv4bf16(<vscale x 4 x i1> %va) {
define <vscale x 4 x bfloat> @vuitofp_nxv4i1_nxv4bf16(<vscale x 4 x i1> %va) {
; ZVFBFMIN-LABEL: vuitofp_nxv4i1_nxv4bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v10, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: lui a0, 4
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v9, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vuitofp_nxv4i1_nxv4bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v9, v8, 1, v0
-; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA-NEXT: lui a0, 4
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
@@ -168,19 +174,21 @@ define <vscale x 8 x bfloat> @vsitofp_nxv8i1_nxv8bf16(<vscale x 8 x i1> %va) {
define <vscale x 8 x bfloat> @vuitofp_nxv8i1_nxv8bf16(<vscale x 8 x i1> %va) {
; ZVFBFMIN-LABEL: vuitofp_nxv8i1_nxv8bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v12, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: lui a0, 4
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v10, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v10, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vuitofp_nxv8i1_nxv8bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v10, v8, 1, v0
-; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v10
+; ZVFBFA-NEXT: lui a0, 4
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
@@ -210,19 +218,21 @@ define <vscale x 16 x bfloat> @vsitofp_nxv16i1_nxv16bf16(<vscale x 16 x i1> %va)
define <vscale x 16 x bfloat> @vuitofp_nxv16i1_nxv16bf16(<vscale x 16 x i1> %va) {
; ZVFBFMIN-LABEL: vuitofp_nxv16i1_nxv16bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: lui a0, 4
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v12, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vuitofp_nxv16i1_nxv16bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m2, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v12, v8, 1, v0
-; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v12
+; ZVFBFA-NEXT: lui a0, 4
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 16 x i1> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
@@ -260,27 +270,21 @@ define <vscale x 32 x bfloat> @vsitofp_nxv32i1_nxv32bf16(<vscale x 32 x i1> %va)
define <vscale x 32 x bfloat> @vuitofp_nxv32i1_nxv32bf16(<vscale x 32 x i1> %va) {
; ZVFBFMIN-LABEL: vuitofp_nxv32i1_nxv32bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v12, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v12, 1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v8
-; ZVFBFMIN-NEXT: csrr a0, vlenb
-; ZVFBFMIN-NEXT: srli a0, a0, 2
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFBFMIN-NEXT: vslidedown.vx v0, v0, a0
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
-; ZVFBFMIN-NEXT: vmerge.vim v12, v12, 1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v12
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v12, v16
+; ZVFBFMIN-NEXT: lui a0, 4
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v16, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vuitofp_nxv32i1_nxv32bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m4, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v16, v8, 1, v0
-; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v16
+; ZVFBFA-NEXT: lui a0, 4
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 32 x i1> %va to <vscale x 32 x bfloat>
ret <vscale x 32 x bfloat> %evec
@@ -1192,19 +1196,21 @@ define <vscale x 1 x half> @vsitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
define <vscale x 1 x half> @vuitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
; ZVFH-LABEL: vuitofp_nxv1i1_nxv1f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v9, v8, 1, v0
-; ZVFH-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFH-NEXT: li a0, 15
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vuitofp_nxv1i1_nxv1f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.xu.v v9, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
+; ZVFHMIN-NEXT: li a0, 15
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: ret
%evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -1225,10 +1231,10 @@ define <vscale x 1 x float> @vsitofp_nxv1i1_nxv1f32(<vscale x 1 x i1> %va) {
define <vscale x 1 x float> @vuitofp_nxv1i1_nxv1f32(<vscale x 1 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv1i1_nxv1f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -1247,13 +1253,23 @@ define <vscale x 1 x double> @vsitofp_nxv1i1_nxv1f64(<vscale x 1 x i1> %va) {
}
define <vscale x 1 x double> @vuitofp_nxv1i1_nxv1f64(<vscale x 1 x i1> %va) {
-; CHECK-LABEL: vuitofp_nxv1i1_nxv1f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
-; CHECK-NEXT: ret
+; RV32-LABEL: vuitofp_nxv1i1_nxv1f64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI61_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI61_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vuitofp_nxv1i1_nxv1f64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, 1023
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
}
@@ -1282,19 +1298,21 @@ define <vscale x 2 x half> @vsitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
define <vscale x 2 x half> @vuitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
; ZVFH-LABEL: vuitofp_nxv2i1_nxv2f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v9, v8, 1, v0
-; ZVFH-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFH-NEXT: li a0, 15
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vuitofp_nxv2i1_nxv2f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.xu.v v9, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
+; ZVFHMIN-NEXT: li a0, 15
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: ret
%evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -1315,10 +1333,10 @@ define <vscale x 2 x float> @vsitofp_nxv2i1_nxv2f32(<vscale x 2 x i1> %va) {
define <vscale x 2 x float> @vuitofp_nxv2i1_nxv2f32(<vscale x 2 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv2i1_nxv2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -1337,13 +1355,23 @@ define <vscale x 2 x double> @vsitofp_nxv2i1_nxv2f64(<vscale x 2 x i1> %va) {
}
define <vscale x 2 x double> @vuitofp_nxv2i1_nxv2f64(<vscale x 2 x i1> %va) {
-; CHECK-LABEL: vuitofp_nxv2i1_nxv2f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vuitofp_nxv2i1_nxv2f64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI67_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI67_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vuitofp_nxv2i1_nxv2f64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, 1023
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
}
@@ -1372,19 +1400,21 @@ define <vscale x 4 x half> @vsitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
define <vscale x 4 x half> @vuitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
; ZVFH-LABEL: vuitofp_nxv4i1_nxv4f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v9, v8, 1, v0
-; ZVFH-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFH-NEXT: li a0, 15
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vuitofp_nxv4i1_nxv4f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.xu.v v10, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
+; ZVFHMIN-NEXT: li a0, 15
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: ret
%evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -1405,10 +1435,10 @@ define <vscale x 4 x float> @vsitofp_nxv4i1_nxv4f32(<vscale x 4 x i1> %va) {
define <vscale x 4 x float> @vuitofp_nxv4i1_nxv4f32(<vscale x 4 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv4i1_nxv4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -1427,13 +1457,23 @@ define <vscale x 4 x double> @vsitofp_nxv4i1_nxv4f64(<vscale x 4 x i1> %va) {
}
define <vscale x 4 x double> @vuitofp_nxv4i1_nxv4f64(<vscale x 4 x i1> %va) {
-; CHECK-LABEL: vuitofp_nxv4i1_nxv4f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v12, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vuitofp_nxv4i1_nxv4f64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI73_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI73_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vuitofp_nxv4i1_nxv4f64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, 1023
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
}
@@ -1462,19 +1502,21 @@ define <vscale x 8 x half> @vsitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
define <vscale x 8 x half> @vuitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
; ZVFH-LABEL: vuitofp_nxv8i1_nxv8f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v10, v8, 1, v0
-; ZVFH-NEXT: vfwcvt.f.xu.v v8, v10
+; ZVFH-NEXT: li a0, 15
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vuitofp_nxv8i1_nxv8f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.xu.v v12, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
+; ZVFHMIN-NEXT: li a0, 15
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v10, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v8, v0
; ZVFHMIN-NEXT: ret
%evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -1495,10 +1537,10 @@ define <vscale x 8 x float> @vsitofp_nxv8i1_nxv8f32(<vscale x 8 x i1> %va) {
define <vscale x 8 x float> @vuitofp_nxv8i1_nxv8f32(<vscale x 8 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv8i1_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v12, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v12
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
@@ -1517,13 +1559,23 @@ define <vscale x 8 x double> @vsitofp_nxv8i1_nxv8f64(<vscale x 8 x i1> %va) {
}
define <vscale x 8 x double> @vuitofp_nxv8i1_nxv8f64(<vscale x 8 x i1> %va) {
-; CHECK-LABEL: vuitofp_nxv8i1_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vuitofp_nxv8i1_nxv8f64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI79_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI79_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vuitofp_nxv8i1_nxv8f64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, 1023
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x double>
ret <vscale x 8 x double> %evec
}
@@ -1552,19 +1604,21 @@ define <vscale x 16 x half> @vsitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
define <vscale x 16 x half> @vuitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
; ZVFH-LABEL: vuitofp_nxv16i1_nxv16f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v12, v8, 1, v0
-; ZVFH-NEXT: vfwcvt.f.xu.v v8, v12
+; ZVFH-NEXT: li a0, 15
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vuitofp_nxv16i1_nxv16f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.xu.v v16, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
+; ZVFHMIN-NEXT: li a0, 15
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v12, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v8, v0
; ZVFHMIN-NEXT: ret
%evec = uitofp <vscale x 16 x i1> %va to <vscale x 16 x half>
ret <vscale x 16 x half> %evec
@@ -1585,10 +1639,10 @@ define <vscale x 16 x float> @vsitofp_nxv16i1_nxv16f32(<vscale x 16 x i1> %va) {
define <vscale x 16 x float> @vuitofp_nxv16i1_nxv16f32(<vscale x 16 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv16i1_nxv16f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v16
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%evec = uitofp <vscale x 16 x i1> %va to <vscale x 16 x float>
ret <vscale x 16 x float> %evec
@@ -1626,27 +1680,21 @@ define <vscale x 32 x half> @vsitofp_nxv32i1_nxv32f16(<vscale x 32 x i1> %va) {
define <vscale x 32 x half> @vuitofp_nxv32i1_nxv32f16(<vscale x 32 x i1> %va) {
; ZVFH-LABEL: vuitofp_nxv32i1_nxv32f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v16, v8, 1, v0
-; ZVFH-NEXT: vfwcvt.f.xu.v v8, v16
+; ZVFH-NEXT: li a0, 15
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vuitofp_nxv32i1_nxv32f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v12, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v12, 1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.xu.v v16, v8
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: srli a0, a0, 2
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a0
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
-; ZVFHMIN-NEXT: vmerge.vim v12, v12, 1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.xu.v v16, v12
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
+; ZVFHMIN-NEXT: li a0, 15
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v16, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
; ZVFHMIN-NEXT: ret
%evec = uitofp <vscale x 32 x i1> %va to <vscale x 32 x half>
ret <vscale x 32 x half> %evec
diff --git a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
index 82f5a873982a9..272b32c3d769f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
@@ -1,15 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <vscale x 2 x bfloat> @vuitofp_nxv2bf16_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv2bf16_nxv2i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.uitofp.nxv2bf16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -18,11 +19,12 @@ define <vscale x 2 x bfloat> @vuitofp_nxv2bf16_nxv2i1(<vscale x 2 x i1> %va, <vs
define <vscale x 2 x bfloat> @vuitofp_nxv2bf16_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv2bf16_nxv2i1_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.uitofp.nxv2bf16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -31,10 +33,11 @@ define <vscale x 2 x bfloat> @vuitofp_nxv2bf16_nxv2i1_unmasked(<vscale x 2 x i1>
define <vscale x 2 x half> @vuitofp_nxv2f16_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv2f16_nxv2i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.uitofp.nxv2f16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x half> %v
@@ -43,10 +46,11 @@ define <vscale x 2 x half> @vuitofp_nxv2f16_nxv2i1(<vscale x 2 x i1> %va, <vscal
define <vscale x 2 x half> @vuitofp_nxv2f16_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv2f16_nxv2i1_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.uitofp.nxv2f16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x half> %v
@@ -55,10 +59,10 @@ define <vscale x 2 x half> @vuitofp_nxv2f16_nxv2i1_unmasked(<vscale x 2 x i1> %v
define <vscale x 2 x float> @vuitofp_nxv2f32_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv2f32_nxv2i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x float> @llvm.vp.uitofp.nxv2f32.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x float> %v
@@ -67,35 +71,55 @@ define <vscale x 2 x float> @vuitofp_nxv2f32_nxv2i1(<vscale x 2 x i1> %va, <vsca
define <vscale x 2 x float> @vuitofp_nxv2f32_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv2f32_nxv2i1_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x float> @llvm.vp.uitofp.nxv2f32.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x float> %v
}
define <vscale x 2 x double> @vuitofp_nxv2f64_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vuitofp_nxv2f64_nxv2i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vuitofp_nxv2f64_nxv2i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI6_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI6_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vuitofp_nxv2f64_nxv2i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, 1023
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%v = call <vscale x 2 x double> @llvm.vp.uitofp.nxv2f64.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x double> %v
}
define <vscale x 2 x double> @vuitofp_nxv2f64_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vuitofp_nxv2f64_nxv2i1_unmasked:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vuitofp_nxv2f64_nxv2i1_unmasked:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI7_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI7_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vuitofp_nxv2f64_nxv2i1_unmasked:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, 1023
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%v = call <vscale x 2 x double> @llvm.vp.uitofp.nxv2f64.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x double> %v
}
>From 97eb0b6dca6316dd4523e4c2d7a0f0429157227b Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Sat, 29 Aug 2026 00:33:50 +0000
Subject: [PATCH 2/2] add SINT_TO_FP
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 12 +-
.../CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll | 124 +++---
.../RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll | 78 ++--
llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll | 358 ++++++++++--------
.../test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll | 100 +++--
5 files changed, 402 insertions(+), 270 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0035cdd08bfb8..e94ae1a7d6823 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8521,15 +8521,17 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return lowerStrictFPExtendOrRoundLike(Op, DAG);
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
- // An unsigned i1-to-fp conversion is equivalent to selecting between
- // 1.0 and 0.0. This avoids extending the mask before converting it.
- if (Op.getOpcode() == ISD::UINT_TO_FP && Op.getValueType().isVector() &&
+ // An i1-to-fp conversion is equivalent to selecting between 1.0/-1.0 and
+ // 0.0 for unsigned/signed conversion, respectively. This avoids extending
+ // the mask before converting it.
+ if (Op.getValueType().isVector() &&
Op.getOperand(0).getValueType().getVectorElementType() == MVT::i1) {
SDLoc DL(Op);
EVT VT = Op.getValueType();
SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
- SDValue One = DAG.getConstantFP(1.0, DL, VT);
- return DAG.getNode(ISD::VSELECT, DL, VT, Op.getOperand(0), One, Zero);
+ double TrueVal = Op.getOpcode() == ISD::UINT_TO_FP ? 1.0 : -1.0;
+ SDValue True = DAG.getConstantFP(TrueVal, DL, VT);
+ return DAG.getNode(ISD::VSELECT, DL, VT, Op.getOperand(0), True, Zero);
}
// Fall back to zvfbfmin for bf16 case if source type is wider than 8 bits.
if (SDValue Op1 = Op.getOperand(0);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
index f4a63709d3e65..5d021d2e0e031 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
@@ -37,10 +37,10 @@ define void @ui2fp_v2i32_v2f32(ptr %x, ptr %y) {
define <2 x float> @si2fp_v2i1_v2f32(<2 x i1> %x) {
; CHECK-LABEL: si2fp_v2i1_v2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%z = sitofp <2 x i1> %x to <2 x float>
ret <2 x float> %z
@@ -117,10 +117,10 @@ define void @ui2fp_v3i32_v3f32(ptr %x, ptr %y) {
define <3 x float> @si2fp_v3i1_v3f32(<3 x i1> %x) {
; CHECK-LABEL: si2fp_v3i1_v3f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%z = sitofp <3 x i1> %x to <3 x float>
ret <3 x float> %z
@@ -315,10 +315,10 @@ define void @ui2fp_v8i32_v8f32(ptr %x, ptr %y) {
define <8 x float> @si2fp_v8i1_v8f32(<8 x i1> %x) {
; CHECK-LABEL: si2fp_v8i1_v8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v10
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%z = sitofp <8 x i1> %x to <8 x float>
ret <8 x float> %z
@@ -397,13 +397,41 @@ define void @ui2fp_v8i16_v8f64(ptr %x, ptr %y) {
}
define <8 x double> @si2fp_v8i1_v8f64(<8 x i1> %x) {
-; CHECK-LABEL: si2fp_v8i1_v8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v12, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v12
-; CHECK-NEXT: ret
+; ZVFH32-LABEL: si2fp_v8i1_v8f64:
+; ZVFH32: # %bb.0:
+; ZVFH32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; ZVFH32-NEXT: vmv.v.i v8, 0
+; ZVFH32-NEXT: lui a0, %hi(.LCPI20_0)
+; ZVFH32-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
+; ZVFH32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; ZVFH32-NEXT: ret
+;
+; ZVFH64-LABEL: si2fp_v8i1_v8f64:
+; ZVFH64: # %bb.0:
+; ZVFH64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; ZVFH64-NEXT: vmv.v.i v8, 0
+; ZVFH64-NEXT: li a0, -1025
+; ZVFH64-NEXT: slli a0, a0, 52
+; ZVFH64-NEXT: vmerge.vxm v8, v8, a0, v0
+; ZVFH64-NEXT: ret
+;
+; ZVFHMIN32-LABEL: si2fp_v8i1_v8f64:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; ZVFHMIN32-NEXT: vmv.v.i v8, 0
+; ZVFHMIN32-NEXT: lui a0, %hi(.LCPI20_0)
+; ZVFHMIN32-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
+; ZVFHMIN32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: si2fp_v8i1_v8f64:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; ZVFHMIN64-NEXT: vmv.v.i v8, 0
+; ZVFHMIN64-NEXT: li a0, -1025
+; ZVFHMIN64-NEXT: slli a0, a0, 52
+; ZVFHMIN64-NEXT: vmerge.vxm v8, v8, a0, v0
+; ZVFHMIN64-NEXT: ret
%z = sitofp <8 x i1> %x to <8 x double>
ret <8 x double> %z
}
@@ -503,19 +531,21 @@ define void @ui2fp_v2i64_v2bf16(ptr %x, ptr %y) {
define <2 x bfloat> @si2fp_v2i1_v2bf16(<2 x i1> %x) {
; ZVFBFMIN-LABEL: si2fp_v2i1_v2bf16:
; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 1048572
+; ZVFBFMIN-NEXT: addi a0, a0, -128
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.x.v v9, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v9, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: si2fp_v2i1_v2bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v9, v8, -1, v0
-; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA-NEXT: lui a0, 1048572
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%z = sitofp <2 x i1> %x to <2 x bfloat>
ret <2 x bfloat> %z
@@ -599,19 +629,21 @@ define void @ui2fp_v8i64_v8bf16(ptr %x, ptr %y) {
define <8 x bfloat> @si2fp_v8i1_v8bf16(<8 x i1> %x) {
; ZVFBFMIN-LABEL: si2fp_v8i1_v8bf16:
; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 1048572
+; ZVFBFMIN-NEXT: addi a0, a0, -128
; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.x.v v10, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v9, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: si2fp_v8i1_v8bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 8, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v9, v8, -1, v0
-; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA-NEXT: lui a0, 1048572
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%z = sitofp <8 x i1> %x to <8 x bfloat>
ret <8 x bfloat> %z
@@ -911,19 +943,21 @@ define void @ui2fp_v2i64_v2f16(ptr %x, ptr %y) {
define <2 x half> @si2fp_v2i1_v2f16(<2 x i1> %x) {
; ZVFH-LABEL: si2fp_v2i1_v2f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v9, v8, -1, v0
-; ZVFH-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFH-NEXT: li a0, -17
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: si2fp_v2i1_v2f16:
; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a0, -17
+; ZVFHMIN-NEXT: slli a0, a0, 10
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.x.v v9, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: ret
%z = sitofp <2 x i1> %x to <2 x half>
ret <2 x half> %z
@@ -987,19 +1021,21 @@ define void @ui2fp_v8i64_v8f16(ptr %x, ptr %y) {
define <8 x half> @si2fp_v8i1_v8f16(<8 x i1> %x) {
; ZVFH-LABEL: si2fp_v8i1_v8f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v9, v8, -1, v0
-; ZVFH-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFH-NEXT: li a0, -17
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: si2fp_v8i1_v8f16:
; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a0, -17
+; ZVFHMIN-NEXT: slli a0, a0, 10
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.x.v v10, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: ret
%z = sitofp <8 x i1> %x to <8 x half>
ret <8 x half> %z
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
index ea86ba1cef8a3..6efbd27ddf2a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
@@ -1,14 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <4 x half> @vsitofp_v4f16_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_v4f16_v4i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
ret <4 x half> %v
@@ -17,10 +18,11 @@ define <4 x half> @vsitofp_v4f16_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %ev
define <4 x half> @vsitofp_v4f16_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_v4f16_v4i1_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
ret <4 x half> %v
@@ -29,10 +31,10 @@ define <4 x half> @vsitofp_v4f16_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
define <4 x float> @vsitofp_v4f32_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_v4f32_v4i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
ret <4 x float> %v
@@ -41,35 +43,55 @@ define <4 x float> @vsitofp_v4f32_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %e
define <4 x float> @vsitofp_v4f32_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_v4f32_v4i1_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
ret <4 x float> %v
}
define <4 x double> @vsitofp_v4f64_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vsitofp_v4f64_v4i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vsitofp_v4f64_v4i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI4_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI4_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vsitofp_v4f64_v4i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, -1025
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
ret <4 x double> %v
}
define <4 x double> @vsitofp_v4f64_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vsitofp_v4f64_v4i1_unmasked:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vsitofp_v4f64_v4i1_unmasked:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI5_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI5_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vsitofp_v4f64_v4i1_unmasked:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, -1025
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
ret <4 x double> %v
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
index f3dfeeb9abeeb..75cd70e1729e1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
@@ -21,19 +21,21 @@
define <vscale x 1 x bfloat> @vsitofp_nxv1i1_nxv1bf16(<vscale x 1 x i1> %va) {
; ZVFBFMIN-LABEL: vsitofp_nxv1i1_nxv1bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.x.v v9, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: lui a0, 1048572
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v9, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vsitofp_nxv1i1_nxv1bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v9, v8, -1, v0
-; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA-NEXT: lui a0, 1048572
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
@@ -65,19 +67,21 @@ define <vscale x 1 x bfloat> @vuitofp_nxv1i1_nxv1bf16(<vscale x 1 x i1> %va) {
define <vscale x 2 x bfloat> @vsitofp_nxv2i1_nxv2bf16(<vscale x 2 x i1> %va) {
; ZVFBFMIN-LABEL: vsitofp_nxv2i1_nxv2bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.x.v v9, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: lui a0, 1048572
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v9, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vsitofp_nxv2i1_nxv2bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v9, v8, -1, v0
-; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA-NEXT: lui a0, 1048572
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
@@ -109,19 +113,21 @@ define <vscale x 2 x bfloat> @vuitofp_nxv2i1_nxv2bf16(<vscale x 2 x i1> %va) {
define <vscale x 4 x bfloat> @vsitofp_nxv4i1_nxv4bf16(<vscale x 4 x i1> %va) {
; ZVFBFMIN-LABEL: vsitofp_nxv4i1_nxv4bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.x.v v10, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: lui a0, 1048572
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v9, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vsitofp_nxv4i1_nxv4bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v9, v8, -1, v0
-; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA-NEXT: lui a0, 1048572
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
@@ -153,19 +159,21 @@ define <vscale x 4 x bfloat> @vuitofp_nxv4i1_nxv4bf16(<vscale x 4 x i1> %va) {
define <vscale x 8 x bfloat> @vsitofp_nxv8i1_nxv8bf16(<vscale x 8 x i1> %va) {
; ZVFBFMIN-LABEL: vsitofp_nxv8i1_nxv8bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.x.v v12, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: lui a0, 1048572
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v10, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v10, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vsitofp_nxv8i1_nxv8bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v10, v8, -1, v0
-; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v10
+; ZVFBFA-NEXT: lui a0, 1048572
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
@@ -197,19 +205,21 @@ define <vscale x 8 x bfloat> @vuitofp_nxv8i1_nxv8bf16(<vscale x 8 x i1> %va) {
define <vscale x 16 x bfloat> @vsitofp_nxv16i1_nxv16bf16(<vscale x 16 x i1> %va) {
; ZVFBFMIN-LABEL: vsitofp_nxv16i1_nxv16bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v8, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v8
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: lui a0, 1048572
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v12, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vsitofp_nxv16i1_nxv16bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m2, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v12, v8, -1, v0
-; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v12
+; ZVFBFA-NEXT: lui a0, 1048572
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 16 x i1> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
@@ -241,27 +251,21 @@ define <vscale x 16 x bfloat> @vuitofp_nxv16i1_nxv16bf16(<vscale x 16 x i1> %va)
define <vscale x 32 x bfloat> @vsitofp_nxv32i1_nxv32bf16(<vscale x 32 x i1> %va) {
; ZVFBFMIN-LABEL: vsitofp_nxv32i1_nxv32bf16:
; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v12, 0
-; ZVFBFMIN-NEXT: vmerge.vim v8, v12, -1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v8
-; ZVFBFMIN-NEXT: csrr a0, vlenb
-; ZVFBFMIN-NEXT: srli a0, a0, 2
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFBFMIN-NEXT: vslidedown.vx v0, v0, a0
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
-; ZVFBFMIN-NEXT: vmerge.vim v12, v12, -1, v0
-; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v12
-; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v12, v16
+; ZVFBFMIN-NEXT: lui a0, 1048572
+; ZVFBFMIN-NEXT: addi a0, a0, -128
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.x v8, a0
+; ZVFBFMIN-NEXT: vmv.v.i v16, 0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vsitofp_nxv32i1_nxv32bf16:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m4, ta, ma
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: vmerge.vim v16, v8, -1, v0
-; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v16
+; ZVFBFA-NEXT: lui a0, 1048572
+; ZVFBFA-NEXT: addi a0, a0, -128
+; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 32 x i1> %va to <vscale x 32 x bfloat>
ret <vscale x 32 x bfloat> %evec
@@ -1175,19 +1179,21 @@ define <vscale x 8 x bfloat> @vuitofp_nxv8i64_nxv8bf16(<vscale x 8 x i64> %va) {
define <vscale x 1 x half> @vsitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
; ZVFH-LABEL: vsitofp_nxv1i1_nxv1f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v9, v8, -1, v0
-; ZVFH-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFH-NEXT: li a0, -17
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vsitofp_nxv1i1_nxv1f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.x.v v9, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
+; ZVFHMIN-NEXT: li a0, -17
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: ret
%evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -1219,10 +1225,10 @@ define <vscale x 1 x half> @vuitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
define <vscale x 1 x float> @vsitofp_nxv1i1_nxv1f32(<vscale x 1 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv1i1_nxv1f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -1241,13 +1247,23 @@ define <vscale x 1 x float> @vuitofp_nxv1i1_nxv1f32(<vscale x 1 x i1> %va) {
}
define <vscale x 1 x double> @vsitofp_nxv1i1_nxv1f64(<vscale x 1 x i1> %va) {
-; CHECK-LABEL: vsitofp_nxv1i1_nxv1f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
-; CHECK-NEXT: ret
+; RV32-LABEL: vsitofp_nxv1i1_nxv1f64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI60_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI60_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vsitofp_nxv1i1_nxv1f64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, -1025
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
}
@@ -1277,19 +1293,21 @@ define <vscale x 1 x double> @vuitofp_nxv1i1_nxv1f64(<vscale x 1 x i1> %va) {
define <vscale x 2 x half> @vsitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
; ZVFH-LABEL: vsitofp_nxv2i1_nxv2f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v9, v8, -1, v0
-; ZVFH-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFH-NEXT: li a0, -17
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vsitofp_nxv2i1_nxv2f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.x.v v9, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
+; ZVFHMIN-NEXT: li a0, -17
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: ret
%evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -1321,10 +1339,10 @@ define <vscale x 2 x half> @vuitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
define <vscale x 2 x float> @vsitofp_nxv2i1_nxv2f32(<vscale x 2 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv2i1_nxv2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -1343,13 +1361,23 @@ define <vscale x 2 x float> @vuitofp_nxv2i1_nxv2f32(<vscale x 2 x i1> %va) {
}
define <vscale x 2 x double> @vsitofp_nxv2i1_nxv2f64(<vscale x 2 x i1> %va) {
-; CHECK-LABEL: vsitofp_nxv2i1_nxv2f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vsitofp_nxv2i1_nxv2f64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI66_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI66_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vsitofp_nxv2i1_nxv2f64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, -1025
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
}
@@ -1379,19 +1407,21 @@ define <vscale x 2 x double> @vuitofp_nxv2i1_nxv2f64(<vscale x 2 x i1> %va) {
define <vscale x 4 x half> @vsitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
; ZVFH-LABEL: vsitofp_nxv4i1_nxv4f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v9, v8, -1, v0
-; ZVFH-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFH-NEXT: li a0, -17
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vsitofp_nxv4i1_nxv4f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.x.v v10, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
+; ZVFHMIN-NEXT: li a0, -17
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: ret
%evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -1423,10 +1453,10 @@ define <vscale x 4 x half> @vuitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
define <vscale x 4 x float> @vsitofp_nxv4i1_nxv4f32(<vscale x 4 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv4i1_nxv4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v10
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -1445,13 +1475,23 @@ define <vscale x 4 x float> @vuitofp_nxv4i1_nxv4f32(<vscale x 4 x i1> %va) {
}
define <vscale x 4 x double> @vsitofp_nxv4i1_nxv4f64(<vscale x 4 x i1> %va) {
-; CHECK-LABEL: vsitofp_nxv4i1_nxv4f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v12, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v12
-; CHECK-NEXT: ret
+; RV32-LABEL: vsitofp_nxv4i1_nxv4f64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI72_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI72_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vsitofp_nxv4i1_nxv4f64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, -1025
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
}
@@ -1481,19 +1521,21 @@ define <vscale x 4 x double> @vuitofp_nxv4i1_nxv4f64(<vscale x 4 x i1> %va) {
define <vscale x 8 x half> @vsitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
; ZVFH-LABEL: vsitofp_nxv8i1_nxv8f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v10, v8, -1, v0
-; ZVFH-NEXT: vfwcvt.f.x.v v8, v10
+; ZVFH-NEXT: li a0, -17
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vsitofp_nxv8i1_nxv8f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.x.v v12, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
+; ZVFHMIN-NEXT: li a0, -17
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v10, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v8, v0
; ZVFHMIN-NEXT: ret
%evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -1525,10 +1567,10 @@ define <vscale x 8 x half> @vuitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
define <vscale x 8 x float> @vsitofp_nxv8i1_nxv8f32(<vscale x 8 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv8i1_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v12, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v12
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
@@ -1547,13 +1589,23 @@ define <vscale x 8 x float> @vuitofp_nxv8i1_nxv8f32(<vscale x 8 x i1> %va) {
}
define <vscale x 8 x double> @vsitofp_nxv8i1_nxv8f64(<vscale x 8 x i1> %va) {
-; CHECK-LABEL: vsitofp_nxv8i1_nxv8f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v16, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v16
-; CHECK-NEXT: ret
+; RV32-LABEL: vsitofp_nxv8i1_nxv8f64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI78_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI78_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vsitofp_nxv8i1_nxv8f64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, -1025
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x double>
ret <vscale x 8 x double> %evec
}
@@ -1583,19 +1635,21 @@ define <vscale x 8 x double> @vuitofp_nxv8i1_nxv8f64(<vscale x 8 x i1> %va) {
define <vscale x 16 x half> @vsitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
; ZVFH-LABEL: vsitofp_nxv16i1_nxv16f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v12, v8, -1, v0
-; ZVFH-NEXT: vfwcvt.f.x.v v8, v12
+; ZVFH-NEXT: li a0, -17
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vsitofp_nxv16i1_nxv16f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v8, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v8, -1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.x.v v16, v8
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
+; ZVFHMIN-NEXT: li a0, -17
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v12, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v8, v0
; ZVFHMIN-NEXT: ret
%evec = sitofp <vscale x 16 x i1> %va to <vscale x 16 x half>
ret <vscale x 16 x half> %evec
@@ -1627,10 +1681,10 @@ define <vscale x 16 x half> @vuitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
define <vscale x 16 x float> @vsitofp_nxv16i1_nxv16f32(<vscale x 16 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv16i1_nxv16f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v16, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v16
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%evec = sitofp <vscale x 16 x i1> %va to <vscale x 16 x float>
ret <vscale x 16 x float> %evec
@@ -1651,27 +1705,21 @@ define <vscale x 16 x float> @vuitofp_nxv16i1_nxv16f32(<vscale x 16 x i1> %va) {
define <vscale x 32 x half> @vsitofp_nxv32i1_nxv32f16(<vscale x 32 x i1> %va) {
; ZVFH-LABEL: vsitofp_nxv32i1_nxv32f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: vmerge.vim v16, v8, -1, v0
-; ZVFH-NEXT: vfwcvt.f.x.v v8, v16
+; ZVFH-NEXT: li a0, -17
+; ZVFH-NEXT: slli a0, a0, 10
+; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vsitofp_nxv32i1_nxv32f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.i v12, 0
-; ZVFHMIN-NEXT: vmerge.vim v8, v12, -1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.x.v v16, v8
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: srli a0, a0, 2
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a0
-; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
-; ZVFHMIN-NEXT: vmerge.vim v12, v12, -1, v0
-; ZVFHMIN-NEXT: vfwcvt.f.x.v v16, v12
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
+; ZVFHMIN-NEXT: li a0, -17
+; ZVFHMIN-NEXT: slli a0, a0, 10
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.i v16, 0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
; ZVFHMIN-NEXT: ret
%evec = sitofp <vscale x 32 x i1> %va to <vscale x 32 x half>
ret <vscale x 32 x half> %evec
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
index a56a833e07d5b..b4961d2b06c82 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
@@ -1,15 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
+; CHECK-NEXT: lui a0, 1048572
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -18,11 +19,12 @@ define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i1(<vscale x 2 x i1> %va, <vs
define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i1_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
+; CHECK-NEXT: lui a0, 1048572
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -31,10 +33,11 @@ define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i1_unmasked(<vscale x 2 x i1>
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x half> %v
@@ -43,10 +46,11 @@ define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i1(<vscale x 2 x i1> %va, <vscal
define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv2f16_nxv2i1_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x half> %v
@@ -55,10 +59,10 @@ define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i1_unmasked(<vscale x 2 x i1> %v
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x float> %v
@@ -67,35 +71,55 @@ define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i1(<vscale x 2 x i1> %va, <vsca
define <vscale x 2 x float> @vsitofp_nxv2f32_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv2f32_nxv2i1_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: lui a0, 784384
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x float> @llvm.vp.sitofp.nxv2f32.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x float> %v
}
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vsitofp_nxv2f64_nxv2i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vsitofp_nxv2f64_nxv2i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI6_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI6_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vsitofp_nxv2f64_nxv2i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, -1025
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x double> %v
}
define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vsitofp_nxv2f64_nxv2i1_unmasked:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v10, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v8, v10
-; CHECK-NEXT: ret
+; RV32-LABEL: vsitofp_nxv2f64_nxv2i1_unmasked:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: lui a0, %hi(.LCPI7_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI7_0)(a0)
+; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vsitofp_nxv2f64_nxv2i1_unmasked:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: li a0, -1025
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
+; RV64-NEXT: ret
%v = call <vscale x 2 x double> @llvm.vp.sitofp.nxv2f64.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x double> %v
}
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