[llvm] [X86] Prefer sub-of-not for vector inc-of-add (PR #207695)

[Rohan Shenoy via llvm-commits]

================
@@ -3819,6 +3819,13 @@ unsigned X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(
   return ISD::SRL;
 }
 
+bool X86TargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
+  // Prefer inc-of-add for scalars and single-element vectors, and sub-of-not
+  // for multi-element vectors.
+  return VT.isScalarInteger() ||
+         (VT.isVector() && VT.getVectorElementCount().isScalar());
----------------
222rohan wrote:

> would a `!isTypeLegal(VT.getScalarType())` work better?

Yes it would! But using this would continue to use the add-of-inc form for `-mtriple=i686-unknown-unknown -mattr=+sse2` when we have a vector with 2 64bit (illegal) lanes. Do you think we should go ahead with it still?

(this case)
```ll
define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
  %t0 = xor <2 x i64> %x, <i64 -1, i64 -1>
  %t1 = sub <2 x i64> %y, %t0
  ret <2 x i64> %t1
}
```
```diff
-; ALL-LABEL: vector_i128_i64:
-; ALL:       # %bb.0:
-; ALL-NEXT:    pcmpeqd %xmm2, %xmm2
-; ALL-NEXT:    pxor %xmm0, %xmm2
-; ALL-NEXT:    psubq %xmm2, %xmm1
-; ALL-NEXT:    movdqa %xmm1, %xmm0
-; ALL-NEXT:    ret{{[l|q]}}
+; X86-LABEL: vector_i128_i64:
+; X86:       # %bb.0:
+; X86-NEXT:    paddq %xmm1, %xmm0
+; X86-NEXT:    pcmpeqd %xmm1, %xmm1
+; X86-NEXT:    psubq %xmm1, %xmm0
+; X86-NEXT:    retl
+;
+; X64-LABEL: vector_i128_i64:
+; X64:       # %bb.0:
+; X64-NEXT:    pcmpeqd %xmm2, %xmm2
+; X64-NEXT:    pxor %xmm0, %xmm2
+; X64-NEXT:    psubq %xmm2, %xmm1
+; X64-NEXT:    movdqa %xmm1, %xmm0
+; X64-NEXT:    retq
```

https://github.com/llvm/llvm-project/pull/207695