[llvm] [SLP][NFC]Add an extra test for gathered splats, NFC (PR #219574)
Alexey Bataev via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 28 14:00:38 PDT 2026
https://github.com/alexey-bataev created https://github.com/llvm/llvm-project/pull/219574
None
>From f79ea2b6d502ea7b76822a2ce6fed913b0c7a97d Mon Sep 17 00:00:00 2001
From: Alexey Bataev <a.bataev at outlook.com>
Date: Fri, 28 Aug 2026 14:00:25 -0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
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Created using spr 1.3.7
---
.../SLPVectorizer/RISCV/splat-gather-trim.ll | 152 ++++++++++++++++++
1 file changed, 152 insertions(+)
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim.ll
index a4fc6d48f80cc..8263b9d8e51a8 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes=slp-vectorizer -S -mtriple=riscv64 --mattr=+v,+zvl256b < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=riscv64 --mattr=+v,+zvl256b -slp-threshold=-2 < %s | FileCheck %s --check-prefix=THRESH
define void @splat_trim(ptr %A, ptr %B, ptr %C, ptr %D, ptr %E, ptr %F, ptr %S) {
; CHECK-LABEL: define void @splat_trim(
@@ -34,6 +35,38 @@ define void @splat_trim(ptr %A, ptr %B, ptr %C, ptr %D, ptr %E, ptr %F, ptr %S)
; CHECK-NEXT: store <4 x i64> [[TMP5]], ptr [[S]], align 8
; CHECK-NEXT: ret void
;
+; THRESH-LABEL: define void @splat_trim(
+; THRESH-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], ptr [[E:%.*]], ptr [[F:%.*]], ptr [[S:%.*]]) #[[ATTR0:[0-9]+]] {
+; THRESH-NEXT: [[ENTRY:.*:]]
+; THRESH-NEXT: [[A0:%.*]] = load i64, ptr [[A]], align 8
+; THRESH-NEXT: [[B0:%.*]] = load i64, ptr [[B]], align 8
+; THRESH-NEXT: [[C0:%.*]] = load i64, ptr [[C]], align 8
+; THRESH-NEXT: [[D0:%.*]] = load i64, ptr [[D]], align 8
+; THRESH-NEXT: [[E0:%.*]] = load i64, ptr [[E]], align 8
+; THRESH-NEXT: [[F0:%.*]] = load i64, ptr [[F]], align 8
+; THRESH-NEXT: [[V1:%.*]] = add i64 1, [[A0]]
+; THRESH-NEXT: [[V2:%.*]] = add i64 1, [[B0]]
+; THRESH-NEXT: [[AS2:%.*]] = add i64 [[V1]], [[V2]]
+; THRESH-NEXT: [[AS3:%.*]] = sub i64 [[V1]], [[V2]]
+; THRESH-NEXT: [[AS1:%.*]] = add i64 [[V1]], [[V2]]
+; THRESH-NEXT: [[AS0:%.*]] = add i64 [[V1]], [[V2]]
+; THRESH-NEXT: [[SH2:%.*]] = lshr i64 [[AS2]], [[E0]]
+; THRESH-NEXT: [[SH3:%.*]] = shl i64 [[AS3]], [[F0]]
+; THRESH-NEXT: [[SH1:%.*]] = lshr i64 [[AS1]], [[D0]]
+; THRESH-NEXT: [[SH0:%.*]] = shl i64 [[AS0]], [[C0]]
+; THRESH-NEXT: [[AS13:%.*]] = sub i64 [[SH2]], [[E0]]
+; THRESH-NEXT: [[AS12:%.*]] = add i64 [[SH3]], [[F0]]
+; THRESH-NEXT: [[AS11:%.*]] = add i64 [[SH1]], [[D0]]
+; THRESH-NEXT: [[AS10:%.*]] = add i64 [[SH0]], [[C0]]
+; THRESH-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[AS10]], i64 0
+; THRESH-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[AS11]], i64 1
+; THRESH-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[AS12]], i64 2
+; THRESH-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[AS13]], i64 3
+; THRESH-NEXT: [[TMP4:%.*]] = add <4 x i64> [[TMP3]], splat (i64 1)
+; THRESH-NEXT: [[TMP5:%.*]] = add <4 x i64> [[TMP4]], splat (i64 1)
+; THRESH-NEXT: store <4 x i64> [[TMP5]], ptr [[S]], align 8
+; THRESH-NEXT: ret void
+;
entry:
%A0 = load i64, ptr %A, align 8
%B0 = load i64, ptr %B, align 8
@@ -80,3 +113,122 @@ entry:
store i64 %Add3, ptr %idxS3, align 8
ret void
}
+
+define void @splat_trim_partial(ptr %A, ptr %B, ptr %C, ptr %D, ptr %E, ptr %F, ptr %S) {
+; CHECK-LABEL: define void @splat_trim_partial(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], ptr [[E:%.*]], ptr [[F:%.*]], ptr [[S:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[A0:%.*]] = load i64, ptr [[A]], align 8
+; CHECK-NEXT: [[B0:%.*]] = load i64, ptr [[B]], align 8
+; CHECK-NEXT: [[C0:%.*]] = load i64, ptr [[C]], align 8
+; CHECK-NEXT: [[D0:%.*]] = load i64, ptr [[D]], align 8
+; CHECK-NEXT: [[E0:%.*]] = load i64, ptr [[E]], align 8
+; CHECK-NEXT: [[F0:%.*]] = load i64, ptr [[F]], align 8
+; CHECK-NEXT: [[V1:%.*]] = add i64 1, [[A0]]
+; CHECK-NEXT: [[V2:%.*]] = add i64 1, [[B0]]
+; CHECK-NEXT: [[V3:%.*]] = add i64 1, [[E0]]
+; CHECK-NEXT: [[AS0:%.*]] = add i64 [[V1]], [[V2]]
+; CHECK-NEXT: [[AS3:%.*]] = sub i64 [[V1]], [[V2]]
+; CHECK-NEXT: [[AS1:%.*]] = add i64 [[V1]], [[V2]]
+; CHECK-NEXT: [[AS2:%.*]] = add i64 [[V1]], [[V2]]
+; CHECK-NEXT: [[SH2:%.*]] = lshr i64 [[AS0]], [[E0]]
+; CHECK-NEXT: [[SH3:%.*]] = shl i64 [[AS3]], [[F0]]
+; CHECK-NEXT: [[SH1:%.*]] = lshr i64 [[AS1]], [[D0]]
+; CHECK-NEXT: [[SH0:%.*]] = shl i64 [[AS2]], [[C0]]
+; CHECK-NEXT: [[AS13:%.*]] = sub i64 [[SH2]], [[E0]]
+; CHECK-NEXT: [[AS12:%.*]] = add i64 [[SH3]], [[F0]]
+; CHECK-NEXT: [[AS11:%.*]] = add i64 [[SH1]], [[D0]]
+; CHECK-NEXT: [[AS10:%.*]] = add i64 [[SH0]], [[C0]]
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[AS10]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[AS11]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[AS12]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[AS13]], i64 3
+; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i64> [[TMP3]], splat (i64 1)
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i64> poison, i64 [[V3]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP7:%.*]] = add <4 x i64> [[TMP4]], [[TMP6]]
+; CHECK-NEXT: store <4 x i64> [[TMP7]], ptr [[S]], align 8
+; CHECK-NEXT: ret void
+;
+; THRESH-LABEL: define void @splat_trim_partial(
+; THRESH-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], ptr [[E:%.*]], ptr [[F:%.*]], ptr [[S:%.*]]) #[[ATTR0]] {
+; THRESH-NEXT: [[ENTRY:.*:]]
+; THRESH-NEXT: [[A0:%.*]] = load i64, ptr [[A]], align 8
+; THRESH-NEXT: [[B0:%.*]] = load i64, ptr [[B]], align 8
+; THRESH-NEXT: [[C0:%.*]] = load i64, ptr [[C]], align 8
+; THRESH-NEXT: [[D0:%.*]] = load i64, ptr [[D]], align 8
+; THRESH-NEXT: [[E0:%.*]] = load i64, ptr [[E]], align 8
+; THRESH-NEXT: [[F0:%.*]] = load i64, ptr [[F]], align 8
+; THRESH-NEXT: [[TMP4:%.*]] = add i64 1, [[A0]]
+; THRESH-NEXT: [[V2:%.*]] = add i64 1, [[B0]]
+; THRESH-NEXT: [[V3:%.*]] = add i64 1, [[E0]]
+; THRESH-NEXT: [[AS2:%.*]] = add i64 [[TMP4]], [[V2]]
+; THRESH-NEXT: [[AS3:%.*]] = sub i64 [[TMP4]], [[V2]]
+; THRESH-NEXT: [[AS1:%.*]] = add i64 [[TMP4]], [[V2]]
+; THRESH-NEXT: [[AS0:%.*]] = add i64 [[TMP4]], [[V2]]
+; THRESH-NEXT: [[SH2:%.*]] = lshr i64 [[AS2]], [[E0]]
+; THRESH-NEXT: [[SH3:%.*]] = shl i64 [[AS3]], [[F0]]
+; THRESH-NEXT: [[SH1:%.*]] = lshr i64 [[AS1]], [[D0]]
+; THRESH-NEXT: [[SH0:%.*]] = shl i64 [[AS0]], [[C0]]
+; THRESH-NEXT: [[AS13:%.*]] = sub i64 [[SH2]], [[E0]]
+; THRESH-NEXT: [[AS12:%.*]] = add i64 [[SH3]], [[F0]]
+; THRESH-NEXT: [[AS11:%.*]] = add i64 [[SH1]], [[D0]]
+; THRESH-NEXT: [[AS10:%.*]] = add i64 [[SH0]], [[C0]]
+; THRESH-NEXT: [[TMP5:%.*]] = insertelement <4 x i64> poison, i64 [[AS10]], i64 0
+; THRESH-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> [[TMP5]], i64 [[AS11]], i64 1
+; THRESH-NEXT: [[TMP7:%.*]] = insertelement <4 x i64> [[TMP6]], i64 [[AS12]], i64 2
+; THRESH-NEXT: [[TMP8:%.*]] = insertelement <4 x i64> [[TMP7]], i64 [[AS13]], i64 3
+; THRESH-NEXT: [[TMP9:%.*]] = add <4 x i64> [[TMP8]], splat (i64 1)
+; THRESH-NEXT: [[TMP12:%.*]] = insertelement <4 x i64> poison, i64 [[V3]], i64 0
+; THRESH-NEXT: [[TMP10:%.*]] = shufflevector <4 x i64> [[TMP12]], <4 x i64> poison, <4 x i32> zeroinitializer
+; THRESH-NEXT: [[TMP11:%.*]] = add <4 x i64> [[TMP9]], [[TMP10]]
+; THRESH-NEXT: store <4 x i64> [[TMP11]], ptr [[S]], align 8
+; THRESH-NEXT: ret void
+;
+entry:
+ %A0 = load i64, ptr %A, align 8
+ %B0 = load i64, ptr %B, align 8
+ %C0 = load i64, ptr %C, align 8
+ %D0 = load i64, ptr %D, align 8
+ %E0 = load i64, ptr %E, align 8
+ %F0 = load i64, ptr %F, align 8
+
+ %v1 = add i64 1, %A0
+ %v2 = add i64 1, %B0
+ %v3 = add i64 1, %E0
+
+ %AS0 = add i64 %v1, %v2
+ %AS1 = add i64 %v1, %v2
+ %AS2 = add i64 %v1, %v2
+ %AS3 = sub i64 %v1, %v2
+
+ %Sh0 = shl i64 %AS0, %C0
+ %Sh1 = lshr i64 %AS1, %D0
+ %Sh2 = lshr i64 %AS2, %E0
+ %Sh3 = shl i64 %AS3, %F0
+
+ %AS10 = add i64 %Sh0, %C0
+ %AS11 = add i64 %Sh1, %D0
+ %AS12 = add i64 %Sh3, %F0
+ %AS13 = sub i64 %Sh2, %E0
+
+ %AS20 = add i64 %AS10, 1
+ %AS21 = add i64 %AS11, 1
+ %AS22 = add i64 %AS12, 1
+ %AS23 = add i64 %AS13, 1
+
+ %Add0 = add i64 %AS20, %v3
+ %Add1 = add i64 %AS21, %v3
+ %Add2 = add i64 %AS22, %v3
+ %Add3 = add i64 %AS23, %v3
+
+ %idxS1 = getelementptr inbounds i64, ptr %S, i64 1
+ %idxS2 = getelementptr inbounds i64, ptr %S, i64 2
+ %idxS3 = getelementptr inbounds i64, ptr %S, i64 3
+
+ store i64 %Add0, ptr %S, align 8
+ store i64 %Add1, ptr %idxS1, align 8
+ store i64 %Add2, ptr %idxS2, align 8
+ store i64 %Add3, ptr %idxS3, align 8
+ ret void
+}
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