[llvm] 847c164 - [AMDGPU] Reject i64 amdgcn.ubfe/sbfe with a diagnostic (#217461)

[via llvm-commits]

Author: Arseniy Obolenskiy
Date: 2026-08-28T21:20:16+02:00
New Revision: 847c164baf4220ce0d0dc634da767ae0b547f022

URL: https://github.com/llvm/llvm-project/commit/847c164baf4220ce0d0dc634da767ae0b547f022
DIFF: https://github.com/llvm/llvm-project/commit/847c164baf4220ce0d0dc634da767ae0b547f022.diff

LOG: [AMDGPU] Reject i64 amdgcn.ubfe/sbfe with a diagnostic (#217461)

- BFE_I32/BFE_U32 are 32-bit only
- wider widths now expand to shifts

Added: 
    llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.i64.err.ll
    llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.i64.err.ll

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 7acc9ca2bafbd..9040b506eb7c9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5668,8 +5668,8 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
     return performFAbsCombine(N, DCI);
   case AMDGPUISD::BFE_I32:
   case AMDGPUISD::BFE_U32: {
-    assert(!N->getValueType(0).isVector() &&
-           "Vector handling of BFE not implemented");
+    assert(N->getValueType(0) == MVT::i32 &&
+           "BFE_I32/BFE_U32 is a 32-bit operation");
     ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
     if (!Width)
       break;

diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 4bb61e43501d1..a8b4d1f9a568b 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -7998,6 +7998,27 @@ static SDValue lowerBALLOTIntrinsic(const SITargetLowering &TLI, SDNode *N,
       DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE));
 }
 
+static SDValue lowerBFEIntrinsic(SDValue Op, SelectionDAG &DAG,
+                                 Intrinsic::ID IntrinsicID) {
+  bool Signed = IntrinsicID == Intrinsic::amdgcn_sbfe;
+  SDLoc DL(Op);
+  EVT VT = Op.getValueType();
+  SDValue Src = Op.getOperand(1);
+  SDValue Offset = Op.getOperand(2);
+  SDValue Width = Op.getOperand(3);
+
+  if (VT != MVT::i32) {
+    DAG.getContext()->diagnose(DiagnosticInfoUnsupported(
+        DAG.getMachineFunction().getFunction(),
+        Twine(Intrinsic::getBaseName(IntrinsicID)) + " only supports i32",
+        DL.getDebugLoc()));
+    return DAG.getPOISON(VT);
+  }
+
+  return DAG.getNode(Signed ? AMDGPUISD::BFE_I32 : AMDGPUISD::BFE_U32, DL, VT,
+                     Src, Offset, Width);
+}
+
 static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
                                          EVT VT);
 
@@ -11424,11 +11445,8 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return DAG.getNode(AMDGPUISD::FMUL_LEGACY, DL, VT, Op.getOperand(1),
                        Op.getOperand(2));
   case Intrinsic::amdgcn_sbfe:
-    return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT, Op.getOperand(1),
-                       Op.getOperand(2), Op.getOperand(3));
   case Intrinsic::amdgcn_ubfe:
-    return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT, Op.getOperand(1),
-                       Op.getOperand(2), Op.getOperand(3));
+    return lowerBFEIntrinsic(Op, DAG, IntrinsicID);
   case Intrinsic::amdgcn_cvt_pkrtz:
   case Intrinsic::amdgcn_cvt_pknorm_i16:
   case Intrinsic::amdgcn_cvt_pknorm_u16:

diff  --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.i64.err.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.i64.err.ll
new file mode 100644
index 0000000000000..8e00d14c36f57
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.i64.err.ll
@@ -0,0 +1,11 @@
+; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s 2>&1 | FileCheck %s
+
+; CHECK: error: <unknown>:0:0: in function sbfe_i64 void (ptr addrspace(1), i64): llvm.amdgcn.sbfe only supports i32
+
+define amdgpu_kernel void @sbfe_i64(ptr addrspace(1) %out, i64 %src) {
+  %bfe = call i64 @llvm.amdgcn.sbfe.i64(i64 %src, i32 8, i32 16)
+  store i64 %bfe, ptr addrspace(1) %out
+  ret void
+}
+
+declare i64 @llvm.amdgcn.sbfe.i64(i64, i32, i32)

diff  --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.i64.err.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.i64.err.ll
new file mode 100644
index 0000000000000..2551dd61c591a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.i64.err.ll
@@ -0,0 +1,11 @@
+; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s 2>&1 | FileCheck %s
+
+; CHECK: error: <unknown>:0:0: in function ubfe_i64 void (ptr addrspace(1), i64): llvm.amdgcn.ubfe only supports i32
+
+define amdgpu_kernel void @ubfe_i64(ptr addrspace(1) %out, i64 %src) {
+  %bfe = call i64 @llvm.amdgcn.ubfe.i64(i64 %src, i32 8, i32 16)
+  store i64 %bfe, ptr addrspace(1) %out
+  ret void
+}
+
+declare i64 @llvm.amdgcn.ubfe.i64(i64, i32, i32)