[llvm] [AMDGPU] Model waterfall loop EXEC update as a terminator (PR #219519)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 28 10:02:36 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Arseniy Obolenskiy (aobolensk)
<details>
<summary>Changes</summary>
Defining a register normally disqualifies an instruction from being a terminator, so mark it unspillable instead
Skip this at -O0, since RegAllocFast ignores that and spills right after the def
---
Patch is 139.78 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/219519.diff
29 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h (+3)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+18-4)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+6)
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+2)
- (modified) llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp (+6)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll (+36-36)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll (+40-40)
- (modified) llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll (+40-40)
- (modified) llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll (+4-4)
- (added) llvm/test/CodeGen/AMDGPU/waterfall-loop-wrexec-terminator.mir (+150)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h b/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
index af14066c1bd46..fc1c005f25426 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
@@ -28,6 +28,7 @@ class LaneMaskConstants {
const unsigned AndN2SaveExecOpc;
const unsigned AndN2TermOpc;
const unsigned AndN2WrExecOpc; // GFX10+ (HasNoSdstCMPX) only
+ const unsigned AndN2WrExecTermOpc;
const unsigned AndSaveExecOpc;
const unsigned AndSaveExecTermOpc;
const unsigned BfmOpc;
@@ -55,6 +56,8 @@ class LaneMaskConstants {
: AMDGPU::S_ANDN2_B64_term),
AndN2WrExecOpc(IsWave32 ? AMDGPU::S_ANDN2_WREXEC_B32
: AMDGPU::S_ANDN2_WREXEC_B64),
+ AndN2WrExecTermOpc(IsWave32 ? AMDGPU::S_ANDN2_WREXEC_B32_term
+ : AMDGPU::S_ANDN2_WREXEC_B64_term),
AndSaveExecOpc(IsWave32 ? AMDGPU::S_AND_SAVEEXEC_B32
: AMDGPU::S_AND_SAVEEXEC_B64),
AndSaveExecTermOpc(IsWave32 ? AMDGPU::S_AND_SAVEEXEC_B32_term
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c70080cd1551f..ff5ce9314576d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2104,6 +2104,13 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
MI.setDesc(get(AMDGPU::V_CMPX_EQ_U64_nosdst_e32));
break;
+ case AMDGPU::S_ANDN2_WREXEC_B64_term:
+ MI.setDesc(get(AMDGPU::S_ANDN2_WREXEC_B64));
+ break;
+ case AMDGPU::S_ANDN2_WREXEC_B32_term:
+ MI.setDesc(get(AMDGPU::S_ANDN2_WREXEC_B32));
+ break;
+
case AMDGPU::SI_SPILL_S32_TO_VGPR:
MI.setDesc(get(AMDGPU::V_WRITELANE_B32));
break;
@@ -3255,6 +3262,8 @@ bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
case AMDGPU::S_AND_SAVEEXEC_B32_term:
case AMDGPU::V_CMPX_EQ_U32_nosdst_e32_term:
case AMDGPU::V_CMPX_EQ_U64_nosdst_e32_term:
+ case AMDGPU::S_ANDN2_WREXEC_B32_term:
+ case AMDGPU::S_ANDN2_WREXEC_B64_term:
break;
case AMDGPU::SI_IF:
case AMDGPU::SI_ELSE:
@@ -7475,9 +7484,8 @@ static void emitLoadScalarOpsFromVGPRLoop(
}
}
- // Instructions AndSaveExecOpc and AndN2WrExecOpc that modify EXEC mask
- // should have isTerminator=1 but terminators that define
- // virtual registers are not supported.
+ // AndSaveExecOpc modifies EXEC but can't be isTerminator=1: terminators
+ // that define virtual registers aren't supported.
Register SaveExec;
if (!UseNewExecInstructions) {
SaveExec = MRI.createVirtualRegister(BoolXExecRC);
@@ -7492,8 +7500,14 @@ static void emitLoadScalarOpsFromVGPRLoop(
I = BodyBB.end();
if (UseNewExecInstructions) {
+ // Terminator form lets PHI elimination fold this into the exec PHI's
+ // def. Skip it at -O0: RegAllocFast spills live-out defs right after
+ // them, not at the first terminator.
+ bool UseTermForm = MF.getTarget().getOptLevel() != CodeGenOptLevel::None;
MRI.setSimpleHint(NewExec, PhiExec);
- BuildMI(BodyBB, I, DL, TII.get(LMC.AndN2WrExecOpc), NewExec)
+ BuildMI(BodyBB, I, DL,
+ TII.get(UseTermForm ? LMC.AndN2WrExecTermOpc : LMC.AndN2WrExecOpc),
+ NewExec)
.addReg(PhiExec);
} else {
// Update EXEC, switch all done bits to 0 and all todo bits to 1.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 4bf0f557ae4e1..98381005b3c86 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -351,6 +351,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
bool expandPostRAPseudo(MachineInstr &MI) const override;
+ // See the comment in emitLoadScalarOpsFromVGPRLoop.
+ bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override {
+ return MI->getOpcode() == AMDGPU::S_ANDN2_WREXEC_B32_term ||
+ MI->getOpcode() == AMDGPU::S_ANDN2_WREXEC_B64_term;
+ }
+
void
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
Register DestReg, unsigned SubIdx, const MachineInstr &Orig,
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index eb23b6fea26b3..a45d424a6a882 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -497,6 +497,7 @@ def S_OR_B64_term : WrapTerminatorInst<S_OR_B64>;
def S_ANDN2_B64_term : WrapTerminatorInst<S_ANDN2_B64>;
def S_AND_B64_term : WrapTerminatorInst<S_AND_B64>;
def S_AND_SAVEEXEC_B64_term : WrapTerminatorInst<S_AND_SAVEEXEC_B64>;
+def S_ANDN2_WREXEC_B64_term : WrapTerminatorInst<S_ANDN2_WREXEC_B64>;
}
let WaveSizePredicate = isWave32 in {
@@ -506,6 +507,7 @@ def S_OR_B32_term : WrapTerminatorInst<S_OR_B32>;
def S_ANDN2_B32_term : WrapTerminatorInst<S_ANDN2_B32>;
def S_AND_B32_term : WrapTerminatorInst<S_AND_B32>;
def S_AND_SAVEEXEC_B32_term : WrapTerminatorInst<S_AND_SAVEEXEC_B32>;
+def S_ANDN2_WREXEC_B32_term : WrapTerminatorInst<S_ANDN2_WREXEC_B32>;
}
class WrapTerminatorVOPC<VOPC_Pseudo base_inst> : VPseudoInstSI<
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
index a9bd72e634414..fab31365eca17 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
@@ -299,6 +299,12 @@ bool SIOptimizeExecMasking::removeTerminatorBit(MachineInstr &MI) const {
case AMDGPU::V_CMPX_EQ_U64_nosdst_e32_term:
MI.setDesc(TII->get(AMDGPU::V_CMPX_EQ_U64_nosdst_e32));
return true;
+ case AMDGPU::S_ANDN2_WREXEC_B64_term:
+ MI.setDesc(TII->get(AMDGPU::S_ANDN2_WREXEC_B64));
+ return true;
+ case AMDGPU::S_ANDN2_WREXEC_B32_term:
+ MI.setDesc(TII->get(AMDGPU::S_ANDN2_WREXEC_B32));
+ return true;
default:
return false;
}
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
index 4719d6edbaaa5..b2cf394ccf193 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
@@ -387,9 +387,9 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__waterfall__amdgp
; GFX12-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_add_f32 v5, v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
-; GFX12-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX12-NEXT: ; implicit-def: $vgpr4
+; GFX12-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-NEXT: s_cbranch_execnz .LBB2_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 exec_lo, s4
@@ -444,9 +444,9 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__waterfall__amdgp
; GFX11-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_atomic_add_f32 v5, v4, s[0:3], 0 offen offset:1024 glc
-; GFX11-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX11-NEXT: ; implicit-def: $vgpr4
+; GFX11-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX11-NEXT: s_cbranch_execnz .LBB2_1
; GFX11-NEXT: ; %bb.2:
; GFX11-NEXT: s_mov_b32 exec_lo, s4
@@ -7036,9 +7036,9 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__waterfall
; GFX12-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_pk_add_f16 v5, v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
-; GFX12-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX12-NEXT: ; implicit-def: $vgpr4
+; GFX12-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-NEXT: s_cbranch_execnz .LBB21_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 exec_lo, s4
@@ -9857,9 +9857,9 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX12-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_pk_add_bf16 v5, v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
-; GFX12-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX12-NEXT: ; implicit-def: $vgpr4
+; GFX12-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 exec_lo, s4
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
index cecc14be3c521..3fdd9467a74f2 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
@@ -378,9 +378,9 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__waterfall__amdgp
; GFX12-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_max_num_f32 v5, v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
-; GFX12-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX12-NEXT: ; implicit-def: $vgpr4
+; GFX12-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-NEXT: s_cbranch_execnz .LBB2_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 exec_lo, s4
@@ -466,9 +466,9 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__waterfall__amdgp
; GFX11-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_atomic_max_f32 v5, v4, s[0:3], 0 offen offset:1024 glc
-; GFX11-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX11-NEXT: ; implicit-def: $vgpr4
+; GFX11-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX11-NEXT: s_cbranch_execnz .LBB2_1
; GFX11-NEXT: ; %bb.2:
; GFX11-NEXT: s_mov_b32 exec_lo, s4
@@ -494,9 +494,9 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__waterfall__amdgp
; GFX10-NEXT: v_cmpx_eq_u64_e32 s[6:7], v[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_fmax v5, v4, s[4:7], 0 offen offset:1024 glc
-; GFX10-NEXT: s_andn2_wrexec_b32 s9, s9
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4
+; GFX10-NEXT: s_andn2_wrexec_b32 s9, s9
; GFX10-NEXT: s_cbranch_execnz .LBB2_1
; GFX10-NEXT: ; %bb.2:
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
@@ -1710,9 +1710,9 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg
; GFX10-NEXT: v_cmpx_eq_u64_e32 s[6:7], v[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_fmax_x2 v[5:6], v4, s[4:7], 0 offen offset:2048 glc
-; GFX10-NEXT: s_andn2_wrexec_b32 s9, s9
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4
+; GFX10-NEXT: s_andn2_wrexec_b32 s9, s9
; GFX10-NEXT: s_cbranch_execnz .LBB7_1
; GFX10-NEXT: ; %bb.2:
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
index 7859ac4841a10..c6cd077701cdd 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
@@ -378,9 +378,9 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__waterfall__amdgp
; GFX12-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_min_num_f32 v5, v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
-; GFX12-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX12-NEXT: ; implicit-def: $vgpr4
+; GFX12-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX12-NEXT: s_cbranch_execnz .LBB2_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 exec_lo, s4
@@ -466,9 +466,9 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__waterfall__amdgp
; GFX11-NEXT: v_cmpx_eq_u64_e32 s[2:3], v[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_atomic_min_f32 v5, v4, s[0:3], 0 offen offset:1024 glc
-; GFX11-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX11-NEXT: ; implicit-def: $vgpr4
+; GFX11-NEXT: s_and_not1_wrexec_b32 s5, s5
; GFX11-NEXT: s_cbranch_execnz .LBB2_1
; GFX11-NEXT: ; %bb.2:
; GFX11-NEXT: s_mov_b32 exec_lo, s4
@@ -494,9 +494,9 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__waterfall__amdgp
; GFX10-NEXT: v_cmpx_eq_u64_e32 s[6:7], v[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_fmin v5, v4, s[4:7], 0 offen offset:1024 glc
-; GFX10-NEXT: s_andn2_wrexec_b32 s9, s9
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4
+; GFX10-NEXT: s_andn2_wrexec_b32 s9, s9
; GFX10-NEXT: s_cbranch_execnz .LBB2_1
; GFX10-NEXT: ; %bb.2:
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
@@ -1710,9 +1710,9 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg
; GFX10-NEXT: v_cmpx_eq_u64_e32 s[6:7], v[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_fmin_x2 v[5:6], v4, s[4:7], 0 offen offset:2048 glc
-; GFX10-NEXT: s_andn2_wrexec_b32 s9, s9
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4
+; GFX10-NEXT: s_andn2_wrexec_b32 s9, s9
; GFX10-NEXT: s_cbranch_execnz .LBB7_1
; GFX10-NEXT: ; %bb.2:
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
diff --git a/llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll b/llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
index 124ba142a56f6..e22aeee59af7a 100644
--- a/llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
+++ b/llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
@@ -37,8 +37,8 @@ define void @issue92561(ptr addrspace(1) %arg) {
; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
; SDAG-NEXT: v_cmpx_eq_u64_e32 s[6:7], v[6:7]
; SDAG-NEXT: image_sample_c_lz v9, [v8, v8, v8, v8], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
-; SDAG-NEXT: s_and_not1_wrexec_b32 s13, s13
; SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; SDAG-NEXT: s_and_not1_wrexec_b32 s13, s13
; SDAG-NEXT: s_cbranch_execnz .LBB0_1
; SDAG-NEXT: ; %bb.2:
; SDAG-NEXT: s_mov_b32 exec_lo, s12
diff --git a/llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
index 76d19d9c6a986..3c7394d9753ca 100644
--- a/llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
@@ -95,7 +95,7 @@ define float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(ptr
; GFX1250-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY1]], killed [[REG_SEQUENCE5]], killed [[V_READFIRSTLANE_B32_4]], 0, 0, 0, implicit $exec :: (dereferenceable load (s32) from %ir.rsrc, align 1, addrspace 8)
- ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32 [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32_term [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX1250-NEXT: SI_WATERFALL_LOOP %bb.1, implicit $exec
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: bb.3:
@@ -199,7 +199,7 @@ define float @raw_ptr_buffer_load_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset(ptr
; GFX1250-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY1]], killed [[REG_SEQUENCE5]], killed [[V_READFIRSTLANE_B32_4]], 0, 0, 0, implicit $exec :: (dereferenceable load (s32) from %ir.rsrc, align 1, addrspace 8)
- ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32 [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32_term [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX1250-NEXT: SI_WATERFALL_LOOP %bb.1, implicit $exec
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: bb.3:
@@ -303,7 +303,7 @@ define float @raw_ptr_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset(ptr
; GFX1250-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY1]], killed [[REG_SEQUENCE5]], killed [[V_READFIRSTLANE_B32_4]], 0, 0, 0, implicit $exec :: (dereferenceable load (s32) from %ir.rsrc, align 1, addrspace 8)
- ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32 [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32_term [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX1250-NEXT: SI_WATERFALL_LOOP %bb.1, implicit $exec
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: bb.3:
@@ -407,7 +407,7 @@ define float @raw_ptr_buffer_load_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffset(ptr
; GFX1250-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY1]], killed [[REG_SEQUENCE5]], killed [[V_READFIRSTLANE_B32_4]], 0, 0, 0, implicit $exec :: (dereferenceable load (s32) from %ir.rsrc, align 1, addrspace 8)
- ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32 [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32_term [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX1250-NEXT: SI_WATERFALL_LOOP %bb.1, implicit $exec
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: bb.3:
@@ -511,7 +511,7 @@ define float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
; GFX1250-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY1]], killed [[REG_SEQUENCE5]], killed [[V_READFIRSTLANE_B32_4]], 0, 1, 0, implicit $exec :: (dereferenceable load (s32) from %ir.rsrc, align 1, addrspace 8)
- ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32 [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32_term [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX1250-NEXT: SI_WATERFALL_LOOP %bb.1, implicit $exec
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: bb.3:
@@ -615,7 +615,7 @@ define float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
; GFX1250-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY1]], killed [[REG_SEQUENCE5]], killed [[V_READFIRSTLANE_B32_4]], 0, 2, 0, implicit $exec :: (dereferenceable load (s32) from %ir.rsrc, align 1, addrspace 8)
- ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32 [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX1250-NEXT: [[S_ANDN2_WREXEC_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_WREXEC_B32_term [[PHI]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX1250-NEX...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/219519
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