[llvm] ef80365 - [X86] Add missing X86ISD::VPERM2X128 v16bf16 pattern handling (#219513)

[via llvm-commits]

Author: Simon Pilgrim
Date: 2026-08-28T16:57:46Z
New Revision: ef8036591e699b5503a17e779e641bf606f5112a

URL: https://github.com/llvm/llvm-project/commit/ef8036591e699b5503a17e779e641bf606f5112a
DIFF: https://github.com/llvm/llvm-project/commit/ef8036591e699b5503a17e779e641bf606f5112a.diff

LOG: [X86] Add missing X86ISD::VPERM2X128 v16bf16 pattern handling (#219513)

Added: 
    llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bf16.ll

Modified: 
    llvm/lib/Target/X86/X86InstrSSE.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 17e7202527efe..2332cb81d54cc 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -7315,6 +7315,7 @@ let Predicates = [HasAVX1Only] in {
   defm : vperm2x128_lowering<"VPERM2F128", v8i32,  loadv8i32>;
   defm : vperm2x128_lowering<"VPERM2F128", v16i16, loadv16i16>;
   defm : vperm2x128_lowering<"VPERM2F128", v16f16, loadv16f16>;
+  defm : vperm2x128_lowering<"VPERM2F128", v16bf16, loadv16bf16>;
   defm : vperm2x128_lowering<"VPERM2F128", v32i8,  loadv32i8>;
 }
 
@@ -7994,6 +7995,7 @@ let Predicates = [HasAVX2] in {
   defm : vperm2x128_lowering<"VPERM2I128", v8i32,  loadv8i32>;
   defm : vperm2x128_lowering<"VPERM2I128", v16i16, loadv16i16>;
   defm : vperm2x128_lowering<"VPERM2I128", v16f16, loadv16f16>;
+  defm : vperm2x128_lowering<"VPERM2I128", v16bf16, loadv16bf16>;
   defm : vperm2x128_lowering<"VPERM2I128", v32i8,  loadv32i8>;
 }
 

diff  --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bf16.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bf16.ll
new file mode 100644
index 0000000000000..03e9afad78f82
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bf16.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512bf16,+avx512vl | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512bf16,+avx512vl | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512bf16 | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512bf16 | FileCheck %s --check-prefixes=X64
+
+define <16 x bfloat> @combine_perm2f128_v16bf16(ptr %p0) {
+; X86-LABEL: combine_perm2f128_v16bf16:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    vperm2f128 {{.*#+}} ymm0 = zero,zero,mem[0,1]
+; X86-NEXT:    retl
+;
+; X64-LABEL: combine_perm2f128_v16bf16:
+; X64:       # %bb.0:
+; X64-NEXT:    vperm2f128 {{.*#+}} ymm0 = zero,zero,mem[0,1]
+; X64-NEXT:    retq
+  %i0 = load <16 x bfloat>, ptr %p0
+  %i1 = extractelement <16 x bfloat> %i0, i64 0
+  %i2 = insertelement <16 x bfloat> <bfloat 0.000000e+00, bfloat 0.000000e+00, bfloat 0.000000e+00, bfloat 0.000000e+00, bfloat undef, bfloat undef, bfloat undef, bfloat undef, bfloat undef, bfloat undef, bfloat undef, bfloat undef, bfloat undef, bfloat undef, bfloat undef, bfloat undef>, bfloat %i1, i64 8
+  ret <16 x bfloat> %i2
+}