[llvm] [AMDGPU][NFC] Unify getImmOrMaterializedImm and getFoldableImm (PR #219522)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 28 09:43:12 PDT 2026
https://github.com/LU-JOHN created https://github.com/llvm/llvm-project/pull/219522
`getImmOrMaterializedImm` and `getFoldableImm` both determine if an operand has a constant value. Make a unified implementation that supports the interfaces of both using the `getImmOrMaterializedImm` name.
>From 164d4d84b1f9398456ee18ed721aa2e760fd789b Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Fri, 28 Aug 2026 11:40:04 -0500
Subject: [PATCH] Unify getImmOrMaterializedImm and getFoldableImm
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 6 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 92 +++++++++++------------
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 9 ++-
3 files changed, 54 insertions(+), 53 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 9a5046889a73b..6c9eb68d33d43 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -2459,8 +2459,7 @@ SIFoldOperandsImpl::isOMod(const MachineInstr &MI) const {
const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
// If there is an immediate operand, it must be Src1
- std::optional<int64_t> Src1Imm =
- TII->getImmOrMaterializedImm(*MRI, const_cast<MachineOperand &>(*Src1));
+ std::optional<int64_t> Src1Imm = TII->getImmOrMaterializedImm(*MRI, *Src1);
if (!Src1Imm)
return {nullptr, SIOutMods::NONE};
@@ -2513,8 +2512,7 @@ SIFoldOperandsImpl::isOMod(const MachineInstr &MI) const {
const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
// If there is an immediate operand, it must be Src1
- std::optional<int64_t> Src1Imm =
- TII->getImmOrMaterializedImm(*MRI, const_cast<MachineOperand &>(*Src1));
+ std::optional<int64_t> Src1Imm = TII->getImmOrMaterializedImm(*MRI, *Src1);
if (!Src1Imm)
return {nullptr, SIOutMods::NONE};
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c70080cd1551f..687ca49f514f9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1310,22 +1310,36 @@ bool SIInstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
std::optional<int64_t>
SIInstrInfo::getImmOrMaterializedImm(const MachineRegisterInfo &MRI,
- MachineOperand &Op) const {
+ const MachineOperand &Op,
+ MachineInstr **DefMI) const {
+ if (DefMI)
+ *DefMI = nullptr;
+
if (Op.isImm())
return Op.getImm();
if (!Op.isReg() || !Op.getReg().isVirtual())
return std::nullopt;
- const MachineInstr *Def = MRI.getVRegDef(Op.getReg());
+ MachineInstr *Def = MRI.getUniqueVRegDef(Op.getReg());
if (Def && Def->isMoveImmediate()) {
const MachineOperand &ImmSrc = Def->getOperand(1);
- if (ImmSrc.isImm())
+ if (ImmSrc.isImm()) {
+ if (DefMI)
+ *DefMI = Def;
return extractSubregFromImm(ImmSrc.getImm(), Op.getSubReg());
+ }
}
return std::nullopt;
}
+std::optional<int64_t>
+SIInstrInfo::getImmOrMaterializedImm(const MachineRegisterInfo &MRI,
+ Register Reg, MachineInstr **DefMI) const {
+ MachineOperand Op = MachineOperand::CreateReg(Reg, false);
+ return getImmOrMaterializedImm(MRI, Op, DefMI);
+}
+
unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
if (RI.isAGPRClass(DstRC))
@@ -4241,29 +4255,6 @@ bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
return false;
}
-static bool getFoldableImm(Register Reg, const MachineRegisterInfo &MRI,
- int64_t &Imm, MachineInstr **DefMI = nullptr) {
- if (Reg.isPhysical())
- return false;
- auto *Def = MRI.getUniqueVRegDef(Reg);
- if (Def && SIInstrInfo::isFoldableCopy(*Def) && Def->getOperand(1).isImm()) {
- Imm = Def->getOperand(1).getImm();
- if (DefMI)
- *DefMI = Def;
- return true;
- }
- return false;
-}
-
-static bool getFoldableImm(const MachineOperand *MO, int64_t &Imm,
- MachineInstr **DefMI = nullptr) {
- if (!MO->isReg())
- return false;
- const MachineFunction *MF = MO->getParent()->getMF();
- const MachineRegisterInfo &MRI = MF->getRegInfo();
- return getFoldableImm(MO->getReg(), MRI, Imm, DefMI);
-}
-
static void updateLiveVariables(LiveVariables *LV, MachineInstr &MI,
MachineInstr &NewMI) {
if (LV) {
@@ -4528,39 +4519,40 @@ SIInstrInfo::convertToThreeAddressImpl(MachineInstr &MI,
(ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
!RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) {
MachineInstr *DefMI = nullptr;
-
+ const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
+ std::optional<int64_t> ImmOpt;
int64_t Imm;
- if (!Src0Literal && getFoldableImm(Src2, Imm, &DefMI)) {
+
+ if (!Src0Literal &&
+ (ImmOpt = getImmOrMaterializedImm(MRI, *Src2, &DefMI))) {
unsigned NewOpc = getNewFMAAKInst(ST, Opc);
if (pseudoToMCOpcode(NewOpc) != -1) {
MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
.add(*Dst)
.add(*Src0)
.add(*Src1)
- .addImm(Imm)
+ .addImm(*ImmOpt)
.setMIFlags(MI.getFlags());
U.RemoveMIUse = DefMI;
return MIB;
}
}
unsigned NewOpc = getNewFMAMKInst(ST, Opc);
- if (!Src0Literal && getFoldableImm(Src1, Imm, &DefMI)) {
+ if (!Src0Literal &&
+ (ImmOpt = getImmOrMaterializedImm(MRI, *Src1, &DefMI))) {
if (pseudoToMCOpcode(NewOpc) != -1) {
MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
.add(*Dst)
.add(*Src0)
- .addImm(Imm)
+ .addImm(*ImmOpt)
.add(*Src2)
.setMIFlags(MI.getFlags());
U.RemoveMIUse = DefMI;
return MIB;
}
}
- if (Src0Literal || getFoldableImm(Src0, Imm, &DefMI)) {
- if (Src0Literal) {
- Imm = Src0->getImm();
- DefMI = nullptr;
- }
+ if ((ImmOpt = getImmOrMaterializedImm(MRI, *Src0, &DefMI))) {
+ Imm = *ImmOpt;
if (pseudoToMCOpcode(NewOpc) != -1 &&
isOperandLegal(
MI, AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::src0),
@@ -11513,12 +11505,13 @@ static bool setsSCCIfResultIsZero(const MachineInstr &Def, bool &NeedInversion,
return false;
const MachineOperand &AddSrc1 = Def.getOperand(1);
const MachineOperand &AddSrc2 = Def.getOperand(2);
- int64_t addend;
+ const MachineRegisterInfo &MRI = Def.getMF()->getRegInfo();
+ const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
+ Def.getMF()->getSubtarget().getInstrInfo());
- if ((!AddSrc1.isImm() || AddSrc1.getImm() != 1) &&
- (!AddSrc2.isImm() || AddSrc2.getImm() != 1) &&
- (!getFoldableImm(&AddSrc1, addend) || addend != 1) &&
- (!getFoldableImm(&AddSrc2, addend) || addend != 1))
+ auto Imm1 = TII->getImmOrMaterializedImm(MRI, AddSrc1);
+ auto Imm2 = TII->getImmOrMaterializedImm(MRI, AddSrc2);
+ if ((!Imm1 || *Imm1 != 1) && (!Imm2 || *Imm2 != 1))
return false;
if (Def.getOpcode() == AMDGPU::S_ADD_I32) {
@@ -11539,8 +11532,12 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
if (!SrcReg || SrcReg.isPhysical())
return false;
- if (SrcReg2 && !getFoldableImm(SrcReg2, *MRI, CmpValue))
- return false;
+ if (SrcReg2) {
+ auto ImmOpt = getImmOrMaterializedImm(*MRI, SrcReg2);
+ if (!ImmOpt)
+ return false;
+ CmpValue = *ImmOpt;
+ }
const auto optimizeCmpSelect = [&CmpInstr, SrcReg, CmpValue, MRI,
this](bool NeedInversion) -> bool {
@@ -11643,11 +11640,12 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
return false;
int64_t Mask;
- const auto isMask = [&Mask, SrcSize](const MachineOperand *MO) -> bool {
- if (MO->isImm())
- Mask = MO->getImm();
- else if (!getFoldableImm(MO, Mask))
+ const auto isMask = [&Mask, SrcSize, MRI,
+ this](const MachineOperand *MO) -> bool {
+ auto ImmOpt = this->getImmOrMaterializedImm(*MRI, *MO);
+ if (!ImmOpt)
return false;
+ Mask = *ImmOpt;
Mask &= maxUIntN(SrcSize);
return isPowerOf2_64(Mask);
};
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 4bf0f557ae4e1..2a608b6991b1c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -325,8 +325,13 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
int64_t &ImmVal) const override;
- std::optional<int64_t> getImmOrMaterializedImm(const MachineRegisterInfo &MRI,
- MachineOperand &Op) const;
+ std::optional<int64_t>
+ getImmOrMaterializedImm(const MachineRegisterInfo &MRI,
+ const MachineOperand &Op,
+ MachineInstr **DefMI = nullptr) const;
+ std::optional<int64_t>
+ getImmOrMaterializedImm(const MachineRegisterInfo &MRI, Register Reg,
+ MachineInstr **DefMI = nullptr) const;
unsigned getVectorRegSpillSaveOpcode(Register Reg,
const TargetRegisterClass *RC,
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