[llvm] 209c6d0 - VirtRegMap: Pass instruction and operand to readsUndefSubreg (#219485)

[via llvm-commits]

Author: Matt Arsenault
Date: 2026-08-28T16:04:54Z
New Revision: 209c6d006b589b3d5ebb17b2960777cc3eb9dec8

URL: https://github.com/llvm/llvm-project/commit/209c6d006b589b3d5ebb17b2960777cc3eb9dec8
DIFF: https://github.com/llvm/llvm-project/commit/209c6d006b589b3d5ebb17b2960777cc3eb9dec8.diff

LOG: VirtRegMap: Pass instruction and operand to readsUndefSubreg (#219485)

The helper recovered the instruction from the operand's parent to look
up its slot index. Pass the containing instruction and the operand directly so
it no longer depends on MachineOperand::getParent().

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Added: 
    

Modified: 
    llvm/lib/CodeGen/VirtRegMap.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 73e910027119e..92a5996c733e4 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -226,7 +226,7 @@ class VirtRegRewriter {
 
   void rewrite();
   void addMBBLiveIns();
-  bool readsUndefSubreg(const MachineOperand &MO) const;
+  bool readsUndefSubreg(const MachineInstr &MI, const MachineOperand &MO) const;
   void addLiveInsForSubRanges(const LiveInterval &LI, MCRegister PhysReg) const;
   void handleIdentityCopy(MachineInstr &MI);
   void expandCopyBundle(MachineInstr &MI) const;
@@ -462,16 +462,17 @@ void VirtRegRewriter::addMBBLiveIns() {
     MBB.sortUniqueLiveIns();
 }
 
-/// Returns true if the given machine operand \p MO only reads undefined lanes.
-/// The function only works for use operands with a subregister set.
-bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
+/// Returns true if the given machine operand \p MO of \p MI only reads
+/// undefined lanes.  The function only works for use operands with a
+/// subregister set.
+bool VirtRegRewriter::readsUndefSubreg(const MachineInstr &MI,
+                                       const MachineOperand &MO) const {
   // Shortcut if the operand is already marked undef.
   if (MO.isUndef())
     return true;
 
   Register Reg = MO.getReg();
   const LiveInterval &LI = LIS->getInterval(Reg);
-  const MachineInstr &MI = *MO.getParent();
   SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
   // This code is only meant to handle reading undefined subregisters which
   // we couldn't properly detect before.
@@ -697,7 +698,7 @@ void VirtRegRewriter::rewrite() {
             }
           } else {
             if (MO.isUse()) {
-              if (readsUndefSubreg(MO))
+              if (readsUndefSubreg(MI, MO))
                 // We need to add an <undef> flag if the subregister is
                 // completely undefined (and we are not adding super-register
                 // defs).