[llvm] [TableGen] Simplify some code in computeSubRegLaneMasks. NFC. (PR #219506)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-tablegen

Author: Jay Foad (jayfoad)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/219506.diff


1 Files Affected:

- (modified) llvm/utils/TableGen/Common/CodeGenRegisters.cpp (+2-7) 


``````````diff
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index b495bcb62969e..10a5a16feef78 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -1650,17 +1650,11 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
       // Idx. These make out all possible valid bits in the lane mask we want to
       // transform. Looking only at the leafs ensure that only a single bit in
       // the mask is set.
-      unsigned NextBit = 0;
       for (CodeGenSubRegIndex &Idx2 : SubRegIndices) {
         // Skip non-leaf subregisters.
         if (!Idx2.getComposites().empty())
           continue;
-        // Replicate the behaviour from the lane mask generation loop above.
-        unsigned SrcBit = NextBit;
-        LaneBitmask SrcMask = LaneBitmask::getLane(SrcBit);
-        if (NextBit < LaneBitmask::BitWidth - 1)
-          ++NextBit;
-        assert(Idx2.LaneMask == SrcMask);
+        LaneBitmask SrcMask = Idx2.LaneMask;
 
         // Get the composed subregister if there is any.
         auto C = Composites.find(&Idx2);
@@ -1671,6 +1665,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
         assert(Composite->getComposites().empty());
 
         // Create Mask+Rotate operation and merge with existing ops if possible.
+        unsigned SrcBit = SrcMask.getHighestLane();
         unsigned DstBit = Composite->LaneMask.getHighestLane();
         int Shift = DstBit - SrcBit;
         uint8_t RotateLeft =

``````````

</details>


https://github.com/llvm/llvm-project/pull/219506