[llvm] [InstCombine] Generalizing icmp ne X, 0 to trunc X to i1 IIF X in range (0,2] (PR #184182)
Andreas Jonson via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 28 06:11:13 PDT 2026
https://github.com/andjo403 updated https://github.com/llvm/llvm-project/pull/184182
>From bc48e3c2e5e564e60d79aca66c088bd148bda100 Mon Sep 17 00:00:00 2001
From: Andreas Jonson <andjo403 at hotmail.com>
Date: Mon, 2 Mar 2026 18:06:29 +0100
Subject: [PATCH] [InstCombine] Generalizing icmp eq/ne X, 1/0 to trunc X to i1
IIF X in range (0,2]
removes the icmp ne (and X, 1), 0 to trunc X to i1 fold that will no longer trigger
---
.../InstCombine/InstCombineCompares.cpp | 28 +++++-
.../AMDGPU/amdgpu-simplify-libcall-pown.ll | 87 ++++++++---------
.../AMDGPU/amdgpu-simplify-libcall-rootn.ll | 14 ++-
.../Transforms/InstCombine/X86/blend_x86.ll | 3 +-
.../Transforms/InstCombine/and-or-icmps.ll | 12 +--
llvm/test/Transforms/InstCombine/and.ll | 14 ++-
llvm/test/Transforms/InstCombine/assume.ll | 12 +--
.../test/Transforms/InstCombine/binop-cast.ll | 9 +-
.../test/Transforms/InstCombine/icmp-binop.ll | 3 +-
llvm/test/Transforms/InstCombine/icmp-dom.ll | 6 +-
.../Transforms/InstCombine/icmp-ne-pow2.ll | 3 +-
.../test/Transforms/InstCombine/icmp-range.ll | 4 +-
.../Transforms/InstCombine/icmp-usub-sat.ll | 2 +-
llvm/test/Transforms/InstCombine/icmp.ll | 2 +-
.../Transforms/InstCombine/known-non-zero.ll | 4 +-
.../InstCombine/known-phi-recurse.ll | 4 +-
llvm/test/Transforms/InstCombine/narrow.ll | 2 +-
.../test/Transforms/InstCombine/or-bitmask.ll | 45 ++++-----
llvm/test/Transforms/InstCombine/pr12251.ll | 15 ++-
llvm/test/Transforms/InstCombine/pr25342.ll | 3 +-
.../Transforms/InstCombine/select-icmp-and.ll | 15 ++-
.../InstCombine/select-of-bittest.ll | 68 ++++++-------
.../InstCombine/select-with-bitwise-ops.ll | 97 ++++++++-----------
llvm/test/Transforms/InstCombine/select.ll | 15 ++-
...ciation-in-bittest-with-truncation-lshr.ll | 22 +++--
...ociation-in-bittest-with-truncation-shl.ll | 8 +-
.../shift-amount-reassociation-in-bittest.ll | 4 +-
.../shift-direction-in-bit-test.ll | 8 +-
llvm/test/Transforms/InstCombine/shift.ll | 2 +-
.../InstCombine/vector-casts-inseltpoison.ll | 5 +-
.../Transforms/InstCombine/vector-casts.ll | 5 +-
.../Transforms/InstCombine/zext-or-icmp.ll | 16 +--
.../LoopUnroll/WebAssembly/basic-unrolling.ll | 5 +-
.../Transforms/LoopUnroll/unroll-cleanup.ll | 19 ++--
llvm/test/Transforms/PGOProfile/chr.ll | 46 ++++-----
.../PGOProfile/cspgo_profile_summary.ll | 8 +-
.../AArch64/extra-unroll-simplifications.ll | 18 ++--
llvm/test/Transforms/PhaseOrdering/pr40750.ll | 8 +-
38 files changed, 304 insertions(+), 337 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index dcae505450941..7cd1483fcd16d 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -1813,10 +1813,6 @@ Instruction *InstCombinerImpl::foldICmpAndConstConst(ICmpInst &Cmp,
const APInt &C1) {
bool isICMP_NE = Cmp.getPredicate() == ICmpInst::ICMP_NE;
- // icmp ne (and X, 1), 0 --> trunc X to i1
- if (isICMP_NE && C1.isZero() && match(And->getOperand(1), m_One()))
- return new TruncInst(And->getOperand(0), Cmp.getType());
-
const APInt *C2;
Value *X;
if (!match(And, m_And(m_Value(X), m_APInt(C2))))
@@ -7232,6 +7228,30 @@ Instruction *InstCombinerImpl::foldICmpUsingKnownBits(ICmpInst &I) {
break;
case ICmpInst::ICMP_EQ:
case ICmpInst::ICMP_NE: {
+ if (Ty->isIntOrIntVectorTy() && Op0Known.getMaxValue() == 1 &&
+ Op1Known.isConstant()) {
+ // If Op0 is 'and LHS, 1', look through it since the and is redundant.
+ Value *LHS;
+ bool IsNUW = false;
+ if (!match(Op0, m_And(m_Value(LHS), m_One()))) {
+ LHS = Op0;
+ IsNUW = true;
+ }
+ APInt Op1C = Op1Known.getConstant();
+ if ((Pred == CmpInst::ICMP_NE && Op1C.isZero()) ||
+ (Pred == CmpInst::ICMP_EQ && Op1C.isOne()))
+ return replaceInstUsesWith(
+ I, Builder.CreateTrunc(LHS, I.getType(), "", IsNUW));
+ if (((Pred == CmpInst::ICMP_NE && Op1C.isOne()) ||
+ (Pred == CmpInst::ICMP_EQ && Op1C.isZero())) &&
+ InstCombiner::canFreelyInvertAllUsersOf(&I,
+ /*IgnoredUser=*/nullptr)) {
+ freelyInvertAllUsersOf(&I);
+
+ return replaceInstUsesWith(
+ I, Builder.CreateTrunc(LHS, I.getType(), "", IsNUW));
+ }
+ }
// If all bits are known zero except for one, then we know at most one bit
// is set. If the comparison is against zero, then this is a check to see if
// *that* bit is set.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
index 52edb382e4f2a..2aea889c3c099 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
@@ -611,21 +611,20 @@ define float @test_pown_afn_f32(float %x, i32 %y) {
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; NOPRELINK-NEXT: [[TMP7:%.*]] = and i32 [[Y]], 1
-; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP7]], 0
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[TMP1]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP8]])
-; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
-; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP10]], +inf
-; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP1]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = icmp slt i32 [[Y]], 0
-; NOPRELINK-NEXT: [[TMP15:%.*]] = xor i1 [[TMP12]], [[TMP14]]
-; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[TMP1]]
-; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn float @llvm.copysign.f32(float [[TMP16]], float [[TMP17]])
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP13]], float [[TMP18]], float [[TMP9]]
-; NOPRELINK-NEXT: ret float [[TMP19]]
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = trunc i32 [[Y]] to i1
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[DOTNOT]], float [[TMP1]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], +inf
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP1]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float +inf
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[DOTNOT]], float [[TMP1]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = select afn i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
+; NOPRELINK-NEXT: ret float [[TMP18]]
;
entry:
%call = tail call afn float @_Z4pownfi(float %x, i32 %y)
@@ -649,21 +648,20 @@ define <2 x float> @test_pown_afn_v2f32(<2 x float> %x, <2 x i32> %y) {
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; NOPRELINK-NEXT: [[TMP7:%.*]] = and <2 x i32> [[Y]], splat (i32 1)
-; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq <2 x i32> [[TMP7]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP1]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP8]])
-; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP1]])
-; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[TMP10]], splat (float +inf)
-; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[TMP1]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP13:%.*]] = or <2 x i1> [[TMP11]], [[TMP12]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP15:%.*]] = xor <2 x i1> [[TMP12]], [[TMP14]]
-; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[TMP15]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
-; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[TMP1]]
-; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP16]], <2 x float> [[TMP17]])
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP13]], <2 x float> [[TMP18]], <2 x float> [[TMP9]]
-; NOPRELINK-NEXT: ret <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = trunc <2 x i32> [[Y]] to <2 x i1>
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> [[TMP1]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP1]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[TMP1]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = or <2 x i1> [[TMP10]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP14:%.*]] = xor <2 x i1> [[TMP11]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> [[TMP1]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP15]], <2 x float> [[TMP16]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[TMP17]], <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP18]]
;
entry:
%call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
@@ -1128,21 +1126,20 @@ define float @test_pown_afn_f32__x_known_positive(float nofpclass(ninf nsub nnor
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; NOPRELINK-NEXT: [[TMP7:%.*]] = and i32 [[Y]], 1
-; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP7]], 0
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[TMP1]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP8]])
-; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
-; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP10]], +inf
-; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP1]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = icmp slt i32 [[Y]], 0
-; NOPRELINK-NEXT: [[TMP15:%.*]] = xor i1 [[TMP12]], [[TMP14]]
-; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[TMP1]]
-; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn float @llvm.copysign.f32(float [[TMP16]], float [[TMP17]])
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP13]], float [[TMP18]], float [[TMP9]]
-; NOPRELINK-NEXT: ret float [[TMP19]]
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = trunc i32 [[Y]] to i1
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[DOTNOT]], float [[TMP1]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], +inf
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP1]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float +inf
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[DOTNOT]], float [[TMP1]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = select afn i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
+; NOPRELINK-NEXT: ret float [[TMP18]]
;
entry:
%call = tail call afn float @_Z4pownfi(float %x, i32 %y)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
index 805e510bde37b..6fc2bba16541d 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
@@ -1730,9 +1730,8 @@ define float @test_rootn_afn_f32__x_known_positive(float nofpclass(ninf nsub nno
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.log2.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul afn float [[TMP1]], [[TMP3]]
; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.exp2.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP6:%.*]] = and i32 [[Y]], 1
-; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = trunc i32 [[Y]] to i1
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[TMP6]], float [[X]], float 1.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], +inf
@@ -1741,7 +1740,7 @@ define float @test_rootn_afn_f32__x_known_positive(float nofpclass(ninf nsub nno
; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP6]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]])
; NOPRELINK-NEXT: [[TMP18:%.*]] = select afn i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[Y]], 0
@@ -1768,15 +1767,14 @@ define float @test_rootn_afn_ninf_nnan_f32__x_known_positive(float nofpclass(nin
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP1]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
-; NOPRELINK-NEXT: [[TMP5:%.*]] = and i32 [[Y]], 1
-; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0
-; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = trunc i32 [[Y]] to i1
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[X]], float 1.000000e+00
; NOPRELINK-NEXT: [[TMP7:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[TMP6]])
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP9:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP10:%.*]] = xor i1 [[TMP8]], [[TMP9]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan ninf afn i1 [[TMP10]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP13:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP11]], float [[TMP12]])
; NOPRELINK-NEXT: [[TMP14:%.*]] = select nnan ninf afn i1 [[TMP8]], float [[TMP13]], float [[TMP7]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[Y]], 0
diff --git a/llvm/test/Transforms/InstCombine/X86/blend_x86.ll b/llvm/test/Transforms/InstCombine/X86/blend_x86.ll
index 36479f7b4e709..d25ef658566e6 100644
--- a/llvm/test/Transforms/InstCombine/X86/blend_x86.ll
+++ b/llvm/test/Transforms/InstCombine/X86/blend_x86.ll
@@ -383,8 +383,7 @@ define <32 x i8> @shl_pblendvb_v32i8(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2
define <4 x float> @shl_blendvps_v4f32(<4 x float> %a0, <4 x float> %a1, <4 x i32> %a2) {
; CHECK-LABEL: @shl_blendvps_v4f32(
-; CHECK-NEXT: [[S_MASK:%.*]] = and <4 x i32> [[A2:%.*]], splat (i32 1)
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq <4 x i32> [[S_MASK]], zeroinitializer
+; CHECK-NEXT: [[DOTNOT:%.*]] = trunc <4 x i32> [[A2:%.*]] to <4 x i1>
; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[DOTNOT]], <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
diff --git a/llvm/test/Transforms/InstCombine/and-or-icmps.ll b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
index 420b963110364..0d1cfaa51e8e1 100644
--- a/llvm/test/Transforms/InstCombine/and-or-icmps.ll
+++ b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
@@ -3455,12 +3455,10 @@ define i1 @and_ugt_to_mask_off_by_one(i8 %x) {
ret i1 %and2
}
-; TODO: shall fold to trunc nuw i8 (and %x, %y) to i1.
define i1 @and_icmp_ne_with_binary_range_operands(i8 range(i8 0, 2) %x, i8 range(i8 0, 2) %y) {
; CHECK-LABEL: @and_icmp_ne_with_binary_range_operands(
-; CHECK-NEXT: [[ICMP1:%.*]] = icmp ne i8 [[X:%.*]], 0
-; CHECK-NEXT: [[ICMP2:%.*]] = icmp ne i8 [[Y:%.*]], 0
-; CHECK-NEXT: [[RET:%.*]] = and i1 [[ICMP1]], [[ICMP2]]
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = trunc nuw i8 [[TMP1]] to i1
; CHECK-NEXT: ret i1 [[RET]]
;
%icmp1 = icmp ne i8 %x, 0
@@ -3469,12 +3467,10 @@ define i1 @and_icmp_ne_with_binary_range_operands(i8 range(i8 0, 2) %x, i8 range
ret i1 %ret
}
-; TODO: shall fold to trunc nuw i8 (and %x, %y) to i1.
define i1 @and_icmp_eq_with_binary_range_operands(i8 range(i8 0, 2) %x, i8 range(i8 0, 2) %y) {
; CHECK-LABEL: @and_icmp_eq_with_binary_range_operands(
-; CHECK-NEXT: [[ICMP1:%.*]] = icmp ne i8 [[X:%.*]], 0
-; CHECK-NEXT: [[ICMP2:%.*]] = icmp ne i8 [[Y:%.*]], 0
-; CHECK-NEXT: [[RET:%.*]] = and i1 [[ICMP1]], [[ICMP2]]
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = trunc nuw i8 [[TMP1]] to i1
; CHECK-NEXT: ret i1 [[RET]]
;
%icmp1 = icmp eq i8 %x, 1
diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll
index 6a25e53ddaba4..a3acc94d90e3c 100644
--- a/llvm/test/Transforms/InstCombine/and.ll
+++ b/llvm/test/Transforms/InstCombine/and.ll
@@ -2459,9 +2459,8 @@ define <3 x i16> @lshr_shl_pow2_const_case1_poison3_vec(<3 x i16> %x) {
define i8 @negate_lowbitmask(i8 %x, i8 %y) !prof !0 {
; CHECK-LABEL: @negate_lowbitmask(
-; CHECK-NEXT: [[A:%.*]] = and i8 [[X:%.*]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[A]], 0
-; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP1]], i8 0, i8 [[Y:%.*]], !prof [[PROF1]]
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i8 [[X:%.*]] to i1
+; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP1]], i8 [[Y:%.*]], i8 0, !prof [[PROF1]]
; CHECK-NEXT: ret i8 [[R]]
;
%a = and i8 %x, 1
@@ -2473,9 +2472,8 @@ define i8 @negate_lowbitmask(i8 %x, i8 %y) !prof !0 {
define <2 x i5> @negate_lowbitmask_commute(<2 x i5> %x, <2 x i5> %p) {
; CHECK-LABEL: @negate_lowbitmask_commute(
; CHECK-NEXT: [[Y:%.*]] = mul <2 x i5> [[P:%.*]], [[P]]
-; CHECK-NEXT: [[A:%.*]] = and <2 x i5> [[X:%.*]], <i5 1, i5 poison>
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i5> [[A]], <i5 poison, i5 0>
-; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[TMP1]], <2 x i5> zeroinitializer, <2 x i5> [[Y]]
+; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i5> [[X:%.*]] to <2 x i1>
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[TMP1]], <2 x i5> [[Y]], <2 x i5> zeroinitializer
; CHECK-NEXT: ret <2 x i5> [[R]]
;
%y = mul <2 x i5> %p, %p ; thwart complexity-based canonicalization
@@ -2489,8 +2487,8 @@ define i8 @negate_lowbitmask_use1(i8 %x, i8 %y) {
; CHECK-LABEL: @negate_lowbitmask_use1(
; CHECK-NEXT: [[A:%.*]] = and i8 [[X:%.*]], 1
; CHECK-NEXT: call void @use8(i8 [[A]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[A]], 0
-; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP1]], i8 0, i8 [[Y:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i8 [[X]] to i1
+; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP1]], i8 [[Y:%.*]], i8 0
; CHECK-NEXT: ret i8 [[R]]
;
%a = and i8 %x, 1
diff --git a/llvm/test/Transforms/InstCombine/assume.ll b/llvm/test/Transforms/InstCombine/assume.ll
index 78c5c4fbff9d4..da08b962281c9 100644
--- a/llvm/test/Transforms/InstCombine/assume.ll
+++ b/llvm/test/Transforms/InstCombine/assume.ll
@@ -1104,8 +1104,8 @@ define void @canonicalize_assume(ptr %0) {
define void @assume_makes_and_known_assume_on_arg(ptr %p, i32 %x) {
; CHECK-LABEL: @assume_makes_and_known_assume_on_arg(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND2]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: store i32 0, ptr [[P:%.*]], align 4
; CHECK-NEXT: ret void
@@ -1121,8 +1121,8 @@ define void @assume_makes_and_known_assume_on_arg(ptr %p, i32 %x) {
define void @assume_makes_and_known_assume_on_mul(ptr %p, i32 %a, i32 %b) {
; CHECK-LABEL: @assume_makes_and_known_assume_on_mul(
; CHECK-NEXT: [[X:%.*]] = mul i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[X]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND2]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: store i32 0, ptr [[P:%.*]], align 4
; CHECK-NEXT: ret void
@@ -1139,8 +1139,8 @@ define void @assume_makes_and_known_assume_on_mul(ptr %p, i32 %a, i32 %b) {
define void @assume_makes_and_known_assume_on_bitwise(ptr %p, i32 %a, i32 %b) {
; CHECK-LABEL: @assume_makes_and_known_assume_on_bitwise(
; CHECK-NEXT: [[X:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[X]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND2]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: store i32 0, ptr [[P:%.*]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/InstCombine/binop-cast.ll b/llvm/test/Transforms/InstCombine/binop-cast.ll
index ae3036ffc88ae..7a6ace2a0ec6e 100644
--- a/llvm/test/Transforms/InstCombine/binop-cast.ll
+++ b/llvm/test/Transforms/InstCombine/binop-cast.ll
@@ -261,8 +261,8 @@ define i32 @xor_sext_to_sel_multi_use_constant_mask(i1 %y) {
define i64 @PR63321(ptr %ptr, i64 %c) !prof !0 {
; CHECK-LABEL: @PR63321(
; CHECK-NEXT: [[VAL:%.*]] = load i8, ptr [[PTR:%.*]], align 1, !range [[RNG2:![0-9]+]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[VAL]], 0
-; CHECK-NEXT: [[RES:%.*]] = select i1 [[TMP1]], i64 [[C:%.*]], i64 0, !prof [[PROF1]]
+; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw i8 [[VAL]] to i1
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[TMP1]], i64 0, i64 [[C:%.*]], !prof [[PROF1]]
; CHECK-NEXT: ret i64 [[RES]]
;
%val = load i8, ptr %ptr, align 1, !range !{i8 0, i8 2}
@@ -301,9 +301,8 @@ define i32 @and_add_bool_to_select(i1 %x, i32 %y) {
define i32 @and_add_bool_no_fold(i32 %y) !prof !0 {
; CHECK-LABEL: @and_add_bool_no_fold(
-; CHECK-NEXT: [[X:%.*]] = and i32 [[Y:%.*]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X]], 0
-; CHECK-NEXT: [[RES:%.*]] = select i1 [[TMP1]], i32 [[Y]], i32 0, !prof [[PROF1]]
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y:%.*]] to i1
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[TMP1]], i32 0, i32 [[Y]], !prof [[PROF1]]
; CHECK-NEXT: ret i32 [[RES]]
;
%x = and i32 %y, 1
diff --git a/llvm/test/Transforms/InstCombine/icmp-binop.ll b/llvm/test/Transforms/InstCombine/icmp-binop.ll
index 2cf70d30fab59..341aef323fdb3 100644
--- a/llvm/test/Transforms/InstCombine/icmp-binop.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-binop.ll
@@ -123,8 +123,7 @@ define <2 x i1> @mul_setoddV_unkV_ne(<2 x i32> %v1, <2 x i32> %v2) {
define i1 @mul_broddV_unkV_eq(i16 %v, i16 %v2) {
; CHECK-LABEL: @mul_broddV_unkV_eq(
-; CHECK-NEXT: [[LB:%.*]] = and i16 [[V2:%.*]], 1
-; CHECK-NEXT: [[ODD_NOT:%.*]] = icmp eq i16 [[LB]], 0
+; CHECK-NEXT: [[ODD_NOT:%.*]] = trunc i16 [[V2:%.*]] to i1
; CHECK-NEXT: br i1 [[ODD_NOT]], label [[FALSE:%.*]], label [[TRUE:%.*]]
; CHECK: true:
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[V:%.*]], 0
diff --git a/llvm/test/Transforms/InstCombine/icmp-dom.ll b/llvm/test/Transforms/InstCombine/icmp-dom.ll
index a72b5e0bbfa03..56b87cbb84292 100644
--- a/llvm/test/Transforms/InstCombine/icmp-dom.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-dom.ll
@@ -407,8 +407,7 @@ falselabel:
define i1 @and_mask1_eq(i32 %conv) {
; CHECK-LABEL: @and_mask1_eq(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[CONV:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[CONV:%.*]] to i1
; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
; CHECK: then:
; CHECK-NEXT: ret i1 false
@@ -432,8 +431,7 @@ else:
define i1 @and_mask1_ne(i32 %conv) {
; CHECK-LABEL: @and_mask1_ne(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[CONV:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[CONV:%.*]] to i1
; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
; CHECK: then:
; CHECK-NEXT: ret i1 false
diff --git a/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll b/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll
index 4be85be543760..d9f5083d01934 100644
--- a/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll
@@ -161,8 +161,7 @@ False:
define i64 @pow2_64_br(i64 %x) {
; CHECK-LABEL: @pow2_64_br(
-; CHECK-NEXT: [[AND:%.*]] = and i64 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[AND]], 0
+; CHECK-NEXT: [[CMP_NOT:%.*]] = trunc i64 [[X:%.*]] to i1
; CHECK-NEXT: br i1 [[CMP_NOT]], label [[FALSE:%.*]], label [[TRUE:%.*]]
; CHECK: True:
; CHECK-NEXT: ret i64 1
diff --git a/llvm/test/Transforms/InstCombine/icmp-range.ll b/llvm/test/Transforms/InstCombine/icmp-range.ll
index 1970694cf9c42..ea8fb1ff1b23e 100644
--- a/llvm/test/Transforms/InstCombine/icmp-range.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-range.ll
@@ -1174,7 +1174,7 @@ define i1 @icmp_eq_bool_0(ptr %ptr) {
define i1 @icmp_eq_bool_1(ptr %ptr) {
; CHECK-LABEL: @icmp_eq_bool_1(
; CHECK-NEXT: [[VAL:%.*]] = load i64, ptr [[PTR:%.*]], align 8, !range [[RNG6]]
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[VAL]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc nuw i64 [[VAL]] to i1
; CHECK-NEXT: ret i1 [[CMP]]
;
%val = load i64, ptr %ptr, align 8, !range !{i64 0, i64 2}
@@ -1185,7 +1185,7 @@ define i1 @icmp_eq_bool_1(ptr %ptr) {
define i1 @icmp_ne_bool_0(ptr %ptr) {
; CHECK-LABEL: @icmp_ne_bool_0(
; CHECK-NEXT: [[VAL:%.*]] = load i64, ptr [[PTR:%.*]], align 8, !range [[RNG6]]
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[VAL]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc nuw i64 [[VAL]] to i1
; CHECK-NEXT: ret i1 [[CMP]]
;
%val = load i64, ptr %ptr, align 8, !range !{i64 0, i64 2}
diff --git a/llvm/test/Transforms/InstCombine/icmp-usub-sat.ll b/llvm/test/Transforms/InstCombine/icmp-usub-sat.ll
index 2cd07b17af580..5662056dbee83 100644
--- a/llvm/test/Transforms/InstCombine/icmp-usub-sat.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-usub-sat.ll
@@ -259,7 +259,7 @@ define i1 @icmp_eq_multiuse_negative(i8 %arg) {
; CHECK-LABEL: define i1 @icmp_eq_multiuse_negative
; CHECK-SAME: (i8 [[ARG:%.*]]) {
; CHECK-NEXT: [[SUB:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[ARG]], i8 -2)
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[ARG]], -1
+; CHECK-NEXT: [[CMP:%.*]] = trunc nuw i8 [[SUB]] to i1
; CHECK-NEXT: call void @use.i8(i8 [[SUB]])
; CHECK-NEXT: ret i1 [[CMP]]
;
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll
index 61ae46ba08d2d..c6336817fd557 100644
--- a/llvm/test/Transforms/InstCombine/icmp.ll
+++ b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -5295,7 +5295,7 @@ define i1 @zext_bool_and_ne0_use(i1 %x, i64 %y) {
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y]], 1
; CHECK-NEXT: [[A:%.*]] = select i1 [[X]], i64 [[TMP1]], i64 0
; CHECK-NEXT: call void @use_i64(i64 [[A]])
-; CHECK-NEXT: [[R:%.*]] = icmp ne i64 [[A]], 0
+; CHECK-NEXT: [[R:%.*]] = trunc nuw i64 [[A]] to i1
; CHECK-NEXT: ret i1 [[R]]
;
%zx = zext i1 %x to i64
diff --git a/llvm/test/Transforms/InstCombine/known-non-zero.ll b/llvm/test/Transforms/InstCombine/known-non-zero.ll
index ead43b2ea29a8..5c96e0cda8a6b 100644
--- a/llvm/test/Transforms/InstCombine/known-non-zero.ll
+++ b/llvm/test/Transforms/InstCombine/known-non-zero.ll
@@ -100,8 +100,8 @@ define void @D60846_miscompile(ptr %p) {
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[I:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[COMMON:%.*]] ]
-; CHECK-NEXT: [[IS_ZERO:%.*]] = icmp eq i16 [[I]], 0
-; CHECK-NEXT: br i1 [[IS_ZERO]], label [[COMMON]], label [[NON_ZERO:%.*]]
+; CHECK-NEXT: [[IS_ZERO:%.*]] = trunc nuw i16 [[I]] to i1
+; CHECK-NEXT: br i1 [[IS_ZERO]], label [[NON_ZERO:%.*]], label [[COMMON]]
; CHECK: non_zero:
; CHECK-NEXT: store i1 true, ptr [[P:%.*]], align 1
; CHECK-NEXT: br label [[COMMON]]
diff --git a/llvm/test/Transforms/InstCombine/known-phi-recurse.ll b/llvm/test/Transforms/InstCombine/known-phi-recurse.ll
index 657ef26e6ffb9..9d61a229161ee 100644
--- a/llvm/test/Transforms/InstCombine/known-phi-recurse.ll
+++ b/llvm/test/Transforms/InstCombine/known-phi-recurse.ll
@@ -164,8 +164,8 @@ define i32 @knownbits_phi_select_test1(ptr %p1, ptr %p2, i8 %x) {
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i16 [[MASK]], 0
; CHECK-NEXT: br i1 [[CMP1]], label [[BB2]], label [[BB1]]
; CHECK: bb1:
-; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[INDVAR4]], 0
-; CHECK-NEXT: [[CMP3:%.*]] = icmp ne i32 [[INDVAR5]], 0
+; CHECK-NEXT: [[CMP2:%.*]] = trunc nuw i32 [[INDVAR4]] to i1
+; CHECK-NEXT: [[CMP3:%.*]] = trunc nuw i32 [[INDVAR5]] to i1
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP2]], i1 true, i1 [[CMP3]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[BB2]], label [[EXIT]]
; CHECK: bb2:
diff --git a/llvm/test/Transforms/InstCombine/narrow.ll b/llvm/test/Transforms/InstCombine/narrow.ll
index 3161d284b637f..c3055513505f7 100644
--- a/llvm/test/Transforms/InstCombine/narrow.ll
+++ b/llvm/test/Transforms/InstCombine/narrow.ll
@@ -160,7 +160,7 @@ define i1 @searchArray2(i32 %hay, ptr %haystack) {
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVAR_NEXT]], 1000
; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
-; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT: [[TOBOOL:%.*]] = trunc nuw i8 [[AND]] to i1
; CHECK-NEXT: ret i1 [[TOBOOL]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/or-bitmask.ll b/llvm/test/Transforms/InstCombine/or-bitmask.ll
index 5fd78827d5f30..717cf22c0b7ee 100644
--- a/llvm/test/Transforms/InstCombine/or-bitmask.ll
+++ b/llvm/test/Transforms/InstCombine/or-bitmask.ll
@@ -159,11 +159,10 @@ define i32 @add_select_cmp_trunc1(i32 %in) {
define i32 @add_select_cmp_and_const_mismatch(i32 %in) {
; CHECK-LABEL: @add_select_cmp_and_const_mismatch(
-; CHECK-NEXT: [[BITOP0:%.*]] = and i32 [[IN:%.*]], 1
-; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[BITOP0]], 0
+; CHECK-NEXT: [[CMP0:%.*]] = trunc i32 [[IN:%.*]] to i1
; CHECK-NEXT: [[BITOP1:%.*]] = and i32 [[IN]], 2
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[BITOP1]], 0
-; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 0, i32 72
+; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 72, i32 0
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i32 0, i32 288
; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[SEL0]], [[SEL1]]
; CHECK-NEXT: ret i32 [[OUT]]
@@ -180,11 +179,10 @@ define i32 @add_select_cmp_and_const_mismatch(i32 %in) {
define i32 @add_select_cmp_and_value_mismatch(i32 %in, i32 %in1) {
; CHECK-LABEL: @add_select_cmp_and_value_mismatch(
-; CHECK-NEXT: [[BITOP0:%.*]] = and i32 [[IN:%.*]], 1
-; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[BITOP0]], 0
+; CHECK-NEXT: [[CMP0:%.*]] = trunc i32 [[IN:%.*]] to i1
; CHECK-NEXT: [[BITOP1:%.*]] = and i32 [[IN1:%.*]], 2
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[BITOP1]], 0
-; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 0, i32 72
+; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 72, i32 0
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i32 0, i32 144
; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[SEL0]], [[SEL1]]
; CHECK-NEXT: ret i32 [[OUT]]
@@ -201,10 +199,9 @@ define i32 @add_select_cmp_and_value_mismatch(i32 %in, i32 %in1) {
define i32 @add_select_cmp_and_negative(i32 %in) {
; CHECK-LABEL: @add_select_cmp_and_negative(
-; CHECK-NEXT: [[BITOP0:%.*]] = and i32 [[IN:%.*]], 1
-; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[BITOP0]], 0
+; CHECK-NEXT: [[CMP0:%.*]] = trunc i32 [[IN:%.*]] to i1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[IN]], 2
-; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 0, i32 72
+; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 72, i32 0
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i32 0, i32 -144
; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[SEL0]], [[SEL1]]
; CHECK-NEXT: ret i32 [[OUT]]
@@ -240,11 +237,10 @@ define i32 @add_select_cmp_and_bitsel_overlap(i32 %in) {
define i32 @add_select_cmp_and_multbit_mask(i32 %in) {
; CHECK-LABEL: @add_select_cmp_and_multbit_mask(
-; CHECK-NEXT: [[BITOP0:%.*]] = and i32 [[IN:%.*]], 1
-; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[BITOP0]], 0
+; CHECK-NEXT: [[CMP0:%.*]] = trunc i32 [[IN:%.*]] to i1
; CHECK-NEXT: [[BITOP1:%.*]] = and i32 [[IN]], 6
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[BITOP1]], 0
-; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 0, i32 72
+; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 72, i32 0
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i32 0, i32 432
; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[SEL0]], [[SEL1]]
; CHECK-NEXT: ret i32 [[OUT]]
@@ -278,12 +274,11 @@ define <2 x i32> @add_select_cmp_vec(<2 x i32> %in) {
define <2 x i32> @add_select_cmp_vec_poison(<2 x i32> %in) {
; CHECK-LABEL: @add_select_cmp_vec_poison(
-; CHECK-NEXT: [[BITOP0:%.*]] = and <2 x i32> [[IN:%.*]], splat (i32 1)
-; CHECK-NEXT: [[CMP0:%.*]] = icmp eq <2 x i32> [[BITOP0]], zeroinitializer
+; CHECK-NEXT: [[CMP0:%.*]] = trunc <2 x i32> [[IN:%.*]] to <2 x i1>
; CHECK-NEXT: [[BITOP1:%.*]] = and <2 x i32> [[IN]], splat (i32 2)
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq <2 x i32> [[BITOP1]], zeroinitializer
; CHECK-NEXT: [[SEL1:%.*]] = select <2 x i1> [[CMP1]], <2 x i32> zeroinitializer, <2 x i32> <i32 poison, i32 144>
-; CHECK-NEXT: [[OUT:%.*]] = select <2 x i1> [[CMP0]], <2 x i32> [[SEL1]], <2 x i32> <i32 72, i32 poison>
+; CHECK-NEXT: [[OUT:%.*]] = select <2 x i1> [[CMP0]], <2 x i32> <i32 72, i32 poison>, <2 x i32> [[SEL1]]
; CHECK-NEXT: ret <2 x i32> [[OUT]]
;
%bitop0 = and <2 x i32> %in, <i32 1, i32 1>
@@ -319,11 +314,10 @@ define <2 x i32> @add_select_cmp_vec_nonunique(<2 x i32> %in) {
define i64 @mask_select_types(i32 %in) {
; CHECK-LABEL: @mask_select_types(
-; CHECK-NEXT: [[BITOP0:%.*]] = and i32 [[IN:%.*]], 1
-; CHECK-NEXT: [[CMP0_NOT:%.*]] = icmp eq i32 [[BITOP0]], 0
+; CHECK-NEXT: [[CMP0_NOT:%.*]] = trunc i32 [[IN:%.*]] to i1
; CHECK-NEXT: [[BITOP1:%.*]] = and i32 [[IN]], 2
; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq i32 [[BITOP1]], 0
-; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0_NOT]], i64 0, i64 72
+; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0_NOT]], i64 72, i64 0
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1_NOT]], i64 0, i64 144
; CHECK-NEXT: [[OUT:%.*]] = or disjoint i64 [[SEL0]], [[SEL1]]
; CHECK-NEXT: ret i64 [[OUT]]
@@ -400,10 +394,9 @@ define i32 @add_select_cmp_and_mul(i32 %in) {
define i32 @add_select_cmp_mixed2_mismatch(i32 %in) {
; CHECK-LABEL: @add_select_cmp_mixed2_mismatch(
-; CHECK-NEXT: [[BITOP0:%.*]] = and i32 [[IN:%.*]], 1
-; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[BITOP0]], 0
+; CHECK-NEXT: [[CMP0:%.*]] = trunc i32 [[IN:%.*]] to i1
; CHECK-NEXT: [[MASK:%.*]] = and i32 [[IN]], 2
-; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 0, i32 73
+; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 73, i32 0
; CHECK-NEXT: [[SEL1:%.*]] = mul nuw nsw i32 [[MASK]], 72
; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[SEL0]], [[SEL1]]
; CHECK-NEXT: ret i32 [[OUT]]
@@ -895,12 +888,11 @@ define i32 @no_chain(i32 %in, i32 %in2, i32 %in3) {
define <2 x i64> @issue199506_1(i64 %idx) {
; CHECK-LABEL: @issue199506_1(
-; CHECK-NEXT: [[B0:%.*]] = and i64 [[IDX:%.*]], 1
-; CHECK-NEXT: [[C0:%.*]] = icmp eq i64 [[B0]], 0
+; CHECK-NEXT: [[C0:%.*]] = trunc i64 [[IDX:%.*]] to i1
; CHECK-NEXT: [[B1:%.*]] = and i64 [[IDX]], 2
; CHECK-NEXT: [[C1:%.*]] = icmp eq i64 [[B1]], 0
; CHECK-NEXT: [[HI:%.*]] = select i1 [[C1]], <2 x i64> zeroinitializer, <2 x i64> splat (i64 -6148914691236517206)
-; CHECK-NEXT: [[LO:%.*]] = select i1 [[C0]], <2 x i64> zeroinitializer, <2 x i64> splat (i64 6148914691236517205)
+; CHECK-NEXT: [[LO:%.*]] = select i1 [[C0]], <2 x i64> splat (i64 6148914691236517205), <2 x i64> zeroinitializer
; CHECK-NEXT: [[OR:%.*]] = or disjoint <2 x i64> [[HI]], [[LO]]
; CHECK-NEXT: ret <2 x i64> [[OR]]
;
@@ -916,12 +908,11 @@ define <2 x i64> @issue199506_1(i64 %idx) {
define <2 x i64> @issue199506_2(i64 %idx) {
; CHECK-LABEL: @issue199506_2(
-; CHECK-NEXT: [[B0:%.*]] = and i64 [[IDX:%.*]], 1
-; CHECK-NEXT: [[C0_NOT:%.*]] = icmp eq i64 [[B0]], 0
+; CHECK-NEXT: [[C0_NOT:%.*]] = trunc i64 [[IDX:%.*]] to i1
; CHECK-NEXT: [[B1:%.*]] = and i64 [[IDX]], 2
; CHECK-NEXT: [[C1_NOT:%.*]] = icmp eq i64 [[B1]], 0
; CHECK-NEXT: [[HI:%.*]] = select i1 [[C1_NOT]], <2 x i64> zeroinitializer, <2 x i64> splat (i64 -6148914691236517206)
-; CHECK-NEXT: [[LO:%.*]] = select i1 [[C0_NOT]], <2 x i64> zeroinitializer, <2 x i64> splat (i64 6148914691236517205)
+; CHECK-NEXT: [[LO:%.*]] = select i1 [[C0_NOT]], <2 x i64> splat (i64 6148914691236517205), <2 x i64> zeroinitializer
; CHECK-NEXT: [[OR:%.*]] = or disjoint <2 x i64> [[HI]], [[LO]]
; CHECK-NEXT: ret <2 x i64> [[OR]]
;
diff --git a/llvm/test/Transforms/InstCombine/pr12251.ll b/llvm/test/Transforms/InstCombine/pr12251.ll
index 1041bdc67b63a..679ad864b45e3 100644
--- a/llvm/test/Transforms/InstCombine/pr12251.ll
+++ b/llvm/test/Transforms/InstCombine/pr12251.ll
@@ -1,6 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
define zeroext i1 @_Z3fooPb(ptr nocapture %x) {
+; CHECK-LABEL: define zeroext i1 @_Z3fooPb(
+; CHECK-SAME: ptr captures(none) [[X:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[A:%.*]] = load i8, ptr [[X]], align 1, !range [[RNG0:![0-9]+]]
+; CHECK-NEXT: [[TOBOOL:%.*]] = trunc nuw i8 [[A]] to i1
+; CHECK-NEXT: ret i1 [[TOBOOL]]
+;
entry:
%a = load i8, ptr %x, align 1, !range !0
%b = and i8 %a, 1
@@ -8,8 +16,7 @@ entry:
ret i1 %tobool
}
-; CHECK: %a = load i8, ptr %x, align 1, !range !0
-; CHECK-NEXT: %tobool = icmp ne i8 %a, 0
-; CHECK-NEXT: ret i1 %tobool
-
!0 = !{i8 0, i8 2}
+;.
+; CHECK: [[RNG0]] = !{i8 0, i8 2}
+;.
diff --git a/llvm/test/Transforms/InstCombine/pr25342.ll b/llvm/test/Transforms/InstCombine/pr25342.ll
index 826070bc4e76b..65debfaac09d9 100644
--- a/llvm/test/Transforms/InstCombine/pr25342.ll
+++ b/llvm/test/Transforms/InstCombine/pr25342.ll
@@ -92,8 +92,7 @@ define void @multi_phi(i32 signext %n) {
; CHECK-NEXT: [[SUB_I:%.*]] = fsub float [[MUL_I]], [[MUL4_I]]
; CHECK-NEXT: [[ADD_I:%.*]] = fadd float [[SUB_I]], [[TMP0]]
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1
-; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[I_0]], 1
-; CHECK-NEXT: [[EVEN_NOT_NOT_NOT:%.*]] = icmp eq i32 [[TMP5]], 0
+; CHECK-NEXT: [[EVEN_NOT_NOT_NOT:%.*]] = trunc i32 [[INC]] to i1
; CHECK-NEXT: br i1 [[EVEN_NOT_NOT_NOT]], label [[ODD_BB]], label [[EVEN_BB:%.*]]
; CHECK: even.bb:
; CHECK-NEXT: [[TMP6:%.*]] = fadd float [[SUB_I]], [[ADD_I]]
diff --git a/llvm/test/Transforms/InstCombine/select-icmp-and.ll b/llvm/test/Transforms/InstCombine/select-icmp-and.ll
index 4309c603bba81..78b78f4272cd3 100644
--- a/llvm/test/Transforms/InstCombine/select-icmp-and.ll
+++ b/llvm/test/Transforms/InstCombine/select-icmp-and.ll
@@ -734,9 +734,8 @@ entry:
define i32 @select_bittest_to_shl(i32 %x) {
; CHECK-LABEL: @select_bittest_to_shl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
-; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 2, i32 4
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 4, i32 2
; CHECK-NEXT: ret i32 [[RET]]
;
entry:
@@ -749,9 +748,8 @@ entry:
define i32 @select_bittest_to_lshr(i32 %x) {
; CHECK-LABEL: @select_bittest_to_lshr(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
-; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 4, i32 2
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 2, i32 4
; CHECK-NEXT: ret i32 [[RET]]
;
entry:
@@ -778,9 +776,8 @@ entry:
define i32 @select_bittest_to_shl_negative_test(i32 %x) {
; CHECK-LABEL: @select_bittest_to_shl_negative_test(
-; CHECK-NEXT: [[MASK:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[MASK]], 0
-; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND]], i32 4, i32 6
+; CHECK-NEXT: [[COND:%.*]] = trunc i32 [[X:%.*]] to i1
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND]], i32 6, i32 4
; CHECK-NEXT: ret i32 [[RES]]
;
%mask = and i32 %x, 1
diff --git a/llvm/test/Transforms/InstCombine/select-of-bittest.ll b/llvm/test/Transforms/InstCombine/select-of-bittest.ll
index 4495e7f6ed067..b4bf011fe690a 100644
--- a/llvm/test/Transforms/InstCombine/select-of-bittest.ll
+++ b/llvm/test/Transforms/InstCombine/select-of-bittest.ll
@@ -7,9 +7,10 @@
define i32 @and_lshr_and(i32 %arg) {
; CHECK-LABEL: @and_lshr_and(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 3
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
-; CHECK-NEXT: [[T4:%.*]] = zext i1 [[TMP2]] to i32
+; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i1
+; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[ARG]], 1
+; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], 1
+; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], i32 1, i32 [[T3]]
; CHECK-NEXT: ret i32 [[T4]]
;
%t = and i32 %arg, 1
@@ -22,9 +23,10 @@ define i32 @and_lshr_and(i32 %arg) {
define <2 x i32> @and_lshr_and_splatvec(<2 x i32> %arg) {
; CHECK-LABEL: @and_lshr_and_splatvec(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[ARG:%.*]], splat (i32 3)
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
-; CHECK-NEXT: [[T4:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
+; CHECK-NEXT: [[T1:%.*]] = trunc <2 x i32> [[ARG:%.*]] to <2 x i1>
+; CHECK-NEXT: [[T2:%.*]] = lshr <2 x i32> [[ARG]], splat (i32 1)
+; CHECK-NEXT: [[T3:%.*]] = and <2 x i32> [[T2]], splat (i32 1)
+; CHECK-NEXT: [[T4:%.*]] = select <2 x i1> [[T1]], <2 x i32> splat (i32 1), <2 x i32> [[T3]]
; CHECK-NEXT: ret <2 x i32> [[T4]]
;
%t = and <2 x i32> %arg, <i32 1, i32 1>
@@ -52,9 +54,10 @@ define <2 x i32> @and_lshr_and_vec_v0(<2 x i32> %arg) {
define <2 x i32> @and_lshr_and_vec_v1(<2 x i32> %arg) {
; CHECK-LABEL: @and_lshr_and_vec_v1(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[ARG:%.*]], <i32 3, i32 5>
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
-; CHECK-NEXT: [[T4:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
+; CHECK-NEXT: [[T1:%.*]] = trunc <2 x i32> [[ARG:%.*]] to <2 x i1>
+; CHECK-NEXT: [[T2:%.*]] = lshr <2 x i32> [[ARG]], <i32 1, i32 2>
+; CHECK-NEXT: [[T3:%.*]] = and <2 x i32> [[T2]], splat (i32 1)
+; CHECK-NEXT: [[T4:%.*]] = select <2 x i1> [[T1]], <2 x i32> splat (i32 1), <2 x i32> [[T3]]
; CHECK-NEXT: ret <2 x i32> [[T4]]
;
%t = and <2 x i32> %arg, <i32 1, i32 1>
@@ -82,9 +85,10 @@ define <2 x i32> @and_lshr_and_vec_v2(<2 x i32> %arg) {
define <3 x i32> @and_lshr_and_vec_poison(<3 x i32> %arg) {
; CHECK-LABEL: @and_lshr_and_vec_poison(
-; CHECK-NEXT: [[TMP1:%.*]] = and <3 x i32> [[ARG:%.*]], <i32 3, i32 poison, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <3 x i32> [[TMP1]], zeroinitializer
-; CHECK-NEXT: [[T4:%.*]] = zext <3 x i1> [[TMP2]] to <3 x i32>
+; CHECK-NEXT: [[T1:%.*]] = trunc <3 x i32> [[ARG:%.*]] to <3 x i1>
+; CHECK-NEXT: [[T2:%.*]] = lshr <3 x i32> [[ARG]], <i32 1, i32 poison, i32 1>
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], <i32 1, i32 poison, i32 1>
+; CHECK-NEXT: [[T4:%.*]] = select <3 x i1> [[T1]], <3 x i32> <i32 1, i32 poison, i32 1>, <3 x i32> [[T3]]
; CHECK-NEXT: ret <3 x i32> [[T4]]
;
%t = and <3 x i32> %arg, <i32 1, i32 poison, i32 1>
@@ -304,11 +308,10 @@ define <3 x i32> @f_var1_vec_poison(<3 x i32> %arg, <3 x i32> %arg1) {
define i32 @f_var2(i32 %arg, i32 %arg1) {
; CHECK-LABEL: @f_var2(
-; CHECK-NEXT: [[T:%.*]] = and i32 [[ARG:%.*]], 1
-; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T]], 0
+; CHECK-NEXT: [[T2:%.*]] = trunc i32 [[ARG:%.*]] to i1
; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[ARG]], [[ARG1:%.*]]
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], 1
-; CHECK-NEXT: [[T5:%.*]] = select i1 [[T2]], i32 [[T4]], i32 1
+; CHECK-NEXT: [[T5:%.*]] = select i1 [[T2]], i32 1, i32 [[T4]]
; CHECK-NEXT: ret i32 [[T5]]
;
%t = and i32 %arg, 1
@@ -321,11 +324,10 @@ define i32 @f_var2(i32 %arg, i32 %arg1) {
define <2 x i32> @f_var2_splatvec(<2 x i32> %arg, <2 x i32> %arg1) {
; CHECK-LABEL: @f_var2_splatvec(
-; CHECK-NEXT: [[T:%.*]] = and <2 x i32> [[ARG:%.*]], splat (i32 1)
-; CHECK-NEXT: [[T2:%.*]] = icmp eq <2 x i32> [[T]], zeroinitializer
+; CHECK-NEXT: [[T2:%.*]] = trunc <2 x i32> [[ARG:%.*]] to <2 x i1>
; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i32> [[ARG]], [[ARG1:%.*]]
; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T3]], splat (i32 1)
-; CHECK-NEXT: [[T5:%.*]] = select <2 x i1> [[T2]], <2 x i32> [[T4]], <2 x i32> splat (i32 1)
+; CHECK-NEXT: [[T5:%.*]] = select <2 x i1> [[T2]], <2 x i32> splat (i32 1), <2 x i32> [[T4]]
; CHECK-NEXT: ret <2 x i32> [[T5]]
;
%t = and <2 x i32> %arg, <i32 1, i32 1>
@@ -355,11 +357,10 @@ define <2 x i32> @f_var2_vec(<2 x i32> %arg, <2 x i32> %arg1) {
define <3 x i32> @f_var2_vec_poison(<3 x i32> %arg, <3 x i32> %arg1) {
; CHECK-LABEL: @f_var2_vec_poison(
-; CHECK-NEXT: [[T:%.*]] = and <3 x i32> [[ARG:%.*]], <i32 1, i32 poison, i32 1>
-; CHECK-NEXT: [[T2:%.*]] = icmp eq <3 x i32> [[T]], <i32 0, i32 poison, i32 0>
+; CHECK-NEXT: [[T2:%.*]] = trunc <3 x i32> [[ARG:%.*]] to <3 x i1>
; CHECK-NEXT: [[T3:%.*]] = lshr <3 x i32> [[ARG]], [[ARG1:%.*]]
; CHECK-NEXT: [[T4:%.*]] = and <3 x i32> [[T3]], <i32 1, i32 poison, i32 1>
-; CHECK-NEXT: [[T5:%.*]] = select <3 x i1> [[T2]], <3 x i32> [[T4]], <3 x i32> <i32 1, i32 poison, i32 1>
+; CHECK-NEXT: [[T5:%.*]] = select <3 x i1> [[T2]], <3 x i32> <i32 1, i32 poison, i32 1>, <3 x i32> [[T4]]
; CHECK-NEXT: ret <3 x i32> [[T5]]
;
%t = and <3 x i32> %arg, <i32 1, i32 poison, i32 1>
@@ -503,11 +504,10 @@ define i32 @n_var1_oneuse(i32 %arg, i32 %arg1) {
define i32 @n0(i32 %arg, i32 %arg1) {
; CHECK-LABEL: @n0(
-; CHECK-NEXT: [[T:%.*]] = and i32 [[ARG:%.*]], 1
-; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T]], 0
+; CHECK-NEXT: [[T2:%.*]] = trunc i32 [[ARG:%.*]] to i1
; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[ARG1:%.*]], 1
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], 1
-; CHECK-NEXT: [[T5:%.*]] = select i1 [[T2]], i32 [[T4]], i32 1
+; CHECK-NEXT: [[T5:%.*]] = select i1 [[T2]], i32 1, i32 [[T4]]
; CHECK-NEXT: ret i32 [[T5]]
;
%t = and i32 %arg, 1
@@ -537,11 +537,10 @@ define i32 @n1(i32 %arg, i32 %arg1) {
define i32 @n2(i32 %arg) {
; CHECK-LABEL: @n2(
-; CHECK-NEXT: [[T:%.*]] = and i32 [[ARG:%.*]], 1
-; CHECK-NEXT: [[T1:%.*]] = icmp eq i32 [[T]], 0
+; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i1
; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[ARG]], 2
; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], 1
-; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], i32 [[T3]], i32 0
+; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], i32 0, i32 [[T3]]
; CHECK-NEXT: ret i32 [[T4]]
;
%t = and i32 %arg, 1
@@ -571,11 +570,10 @@ define i32 @n3(i32 %arg) {
define i32 @n4(i32 %arg) {
; CHECK-LABEL: @n4(
-; CHECK-NEXT: [[T:%.*]] = and i32 [[ARG:%.*]], 1
-; CHECK-NEXT: [[T1:%.*]] = icmp eq i32 [[T]], 0
+; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i1
; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[ARG]], 2
; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], 2
-; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], i32 [[T3]], i32 1
+; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], i32 1, i32 [[T3]]
; CHECK-NEXT: ret i32 [[T4]]
;
%t = and i32 %arg, 1
@@ -603,11 +601,10 @@ define i32 @n5(i32 %arg) {
define i32 @n6(i32 %arg) {
; CHECK-LABEL: @n6(
-; CHECK-NEXT: [[T:%.*]] = and i32 [[ARG:%.*]], 1
-; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i32 [[T]], 0
+; CHECK-NEXT: [[T1_NOT:%.*]] = trunc i32 [[ARG:%.*]] to i1
; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[ARG]], 2
; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], 1
-; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1_NOT]], i32 1, i32 [[T3]]
+; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1_NOT]], i32 [[T3]], i32 1
; CHECK-NEXT: ret i32 [[T4]]
;
%t = and i32 %arg, 1
@@ -637,11 +634,10 @@ define i32 @n7(i32 %arg) {
define i32 @n8(i32 %arg) {
; CHECK-LABEL: @n8(
-; CHECK-NEXT: [[T:%.*]] = and i32 [[ARG:%.*]], 1
-; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i32 [[T]], 0
+; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i1
; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[ARG]], 2
; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], 1
-; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1_NOT]], i32 1, i32 [[T3]]
+; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], i32 [[T3]], i32 1
; CHECK-NEXT: ret i32 [[T4]]
;
%t = and i32 %arg, 1
diff --git a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
index 771fad66e961e..5fd15871318ed 100644
--- a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
+++ b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
@@ -64,8 +64,8 @@ define <2 x i32> @select_icmp_eq_and_1_0_or_2_vec(<2 x i32> %x, <2 x i32> %y) {
define <2 x i32> @select_icmp_eq_and_1_0_or_2_vec_poison1(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @select_icmp_eq_and_1_0_or_2_vec_poison1(
-; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 1, i32 poison>
-; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw <2 x i32> [[AND]], splat (i32 1)
+; CHECK-NEXT: [[TMP2:%.*]] = shl <2 x i32> [[X:%.*]], splat (i32 1)
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[TMP2]], splat (i32 2)
; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[Y:%.*]], [[TMP1]]
; CHECK-NEXT: ret <2 x i32> [[SELECT]]
;
@@ -120,10 +120,9 @@ define i32 @select_icmp_eq_and_1_0_xor_2(i32 %x, i32 %y) {
define i32 @select_icmp_eq_and_1_0_and_not_2(i32 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_eq_and_1_0_and_not_2(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -3
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]
; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i32 %x, 1
@@ -345,10 +344,9 @@ define i32 @select_icmp_eq_0_and_1_xor_1(i64 %x, i32 %y) {
define i32 @select_icmp_eq_0_and_1_and_not_1(i64 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_eq_0_and_1_and_not_1(
-; CHECK-NEXT: [[AND:%.*]] = and i64 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i64 [[X:%.*]] to i1
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -2
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]
; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i64 %x, 1
@@ -557,10 +555,9 @@ define i32 @select_icmp_ne_0_and_8_and_not_1073741824(i8 %x, i32 %y) {
; Just make sure we don't assert.
define <2 x i32> @select_icmp_eq_and_1_0_or_vector_of_2s(i32 %x, <2 x i32> %y) {
; CHECK-LABEL: @select_icmp_eq_and_1_0_or_vector_of_2s(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[Y:%.*]], splat (i32 2)
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x i32> [[Y]], <2 x i32> [[OR]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x i32> [[OR]], <2 x i32> [[Y]]
; CHECK-NEXT: ret <2 x i32> [[SELECT]]
;
%and = and i32 %x, 1
@@ -851,10 +848,9 @@ define i8 @test70_multiuse(i8 %x, i8 %y) {
define i32 @shift_no_xor_multiuse_or(i32 %x, i32 %y) {
; CHECK-LABEL: @shift_no_xor_multiuse_or(
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2
-; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2
-; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[Y]], [[TMP1]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[OR]], i32 [[Y]]
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[OR]]
; CHECK-NEXT: ret i32 [[RES]]
;
@@ -868,10 +864,9 @@ define i32 @shift_no_xor_multiuse_or(i32 %x, i32 %y) {
define i32 @shift_no_xor_multiuse_xor(i32 %x, i32 %y) {
; CHECK-LABEL: @shift_no_xor_multiuse_xor(
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2
-; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2
-; CHECK-NEXT: [[SELECT:%.*]] = xor i32 [[Y]], [[TMP1]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[XOR]]
; CHECK-NEXT: ret i32 [[RES]]
;
@@ -885,10 +880,9 @@ define i32 @shift_no_xor_multiuse_xor(i32 %x, i32 %y) {
define i32 @shift_no_xor_multiuse_and(i32 %x, i32 %y) {
; CHECK-LABEL: @shift_no_xor_multiuse_and(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -3
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[AND2]]
; CHECK-NEXT: ret i32 [[RES]]
;
@@ -1053,12 +1047,11 @@ define i32 @shift_xor_multiuse_and(i32 %x, i32 %y) {
define i32 @shift_no_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
; CHECK-LABEL: @shift_no_xor_multiuse_cmp(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i32 [[AND]], 1
-; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[Y:%.*]], [[TMP1]]
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
-; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
+; CHECK-NEXT: [[Z:%.*]] = or i32 [[W:%.*]], 2
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z]], i32 [[W]]
+; CHECK-NEXT: [[SELECT3:%.*]] = select i1 [[CMP]], i32 [[W1:%.*]], i32 [[Z1:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT2]], [[SELECT3]]
; CHECK-NEXT: ret i32 [[RES]]
;
%and = and i32 %x, 1
@@ -1072,12 +1065,11 @@ define i32 @shift_no_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
define i32 @shift_no_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
; CHECK-LABEL: @shift_no_xor_multiuse_cmp_with_xor(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i32 [[AND]], 1
-; CHECK-NEXT: [[SELECT:%.*]] = xor i32 [[Y:%.*]], [[TMP1]]
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
-; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
+; CHECK-NEXT: [[Z:%.*]] = xor i32 [[W:%.*]], 2
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z]], i32 [[W]]
+; CHECK-NEXT: [[SELECT3:%.*]] = select i1 [[CMP]], i32 [[W1:%.*]], i32 [[Z1:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT2]], [[SELECT3]]
; CHECK-NEXT: ret i32 [[RES]]
;
%and = and i32 %x, 1
@@ -1091,10 +1083,9 @@ define i32 @shift_no_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
define i32 @shift_no_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w) {
; CHECK-LABEL: @shift_no_xor_multiuse_cmp_with_and(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -3
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]
; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
; CHECK-NEXT: ret i32 [[RES]]
@@ -1279,10 +1270,9 @@ define i32 @shift_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w) {
define i32 @shift_no_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {
; CHECK-LABEL: @shift_no_xor_multiuse_cmp_or(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[OR]], i32 [[Y]]
; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
@@ -1300,10 +1290,9 @@ define i32 @shift_no_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {
define i32 @shift_no_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
; CHECK-LABEL: @shift_no_xor_multiuse_cmp_xor(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[XOR]]
@@ -1321,10 +1310,9 @@ define i32 @shift_no_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
define i32 @shift_no_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32 %w) {
; CHECK-LABEL: @shift_no_xor_multiuse_cmp_and(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -3
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]
; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[AND2]]
@@ -1652,10 +1640,9 @@ define i8 @clear_bits_extra_use2(i8 %x, i1 %b) {
; Tests factoring in cost of saving the `and`
define i64 @xor_i8_to_i64_shl_save_and_eq(i8 %x, i64 %y) {
; CHECK-LABEL: @xor_i8_to_i64_shl_save_and_eq(
-; CHECK-NEXT: [[XX:%.*]] = and i8 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[XX]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i8 [[X:%.*]] to i1
; CHECK-NEXT: [[Z:%.*]] = xor i64 [[Y:%.*]], -9223372036854775808
-; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP]], i64 [[Z]], i64 [[Y]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP]], i64 [[Y]], i64 [[Z]]
; CHECK-NEXT: ret i64 [[R]]
;
%xx = and i8 %x, 1
@@ -1667,9 +1654,9 @@ define i64 @xor_i8_to_i64_shl_save_and_eq(i8 %x, i64 %y) {
define i64 @xor_i8_to_i64_shl_save_and_ne(i8 %x, i64 %y) {
; CHECK-LABEL: @xor_i8_to_i64_shl_save_and_ne(
-; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[X:%.*]] to i64
-; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 63
-; CHECK-NEXT: [[R:%.*]] = xor i64 [[Y:%.*]], [[TMP2]]
+; CHECK-NEXT: [[CMP_NOT:%.*]] = trunc i8 [[X:%.*]] to i1
+; CHECK-NEXT: [[Z:%.*]] = xor i64 [[Y:%.*]], -9223372036854775808
+; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP_NOT]], i64 [[Z]], i64 [[Y]]
; CHECK-NEXT: ret i64 [[R]]
;
%xx = and i8 %x, 1
@@ -1681,10 +1668,9 @@ define i64 @xor_i8_to_i64_shl_save_and_ne(i8 %x, i64 %y) {
define i32 @select_icmp_eq_and_1_0_srem_2_fail_null_identity(i32 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_eq_and_1_0_srem_2_fail_null_identity(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
; CHECK-NEXT: [[XOR:%.*]] = srem i32 [[Y:%.*]], 2
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i32 %x, 1
@@ -1697,10 +1683,9 @@ define i32 @select_icmp_eq_and_1_0_srem_2_fail_null_identity(i32 %x, i32 %y) {
define i32 @select_icmp_eq_and_1_0_sdiv_2_fail_null_1_identity(i32 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_eq_and_1_0_sdiv_2_fail_null_1_identity(
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1
; CHECK-NEXT: [[XOR:%.*]] = sdiv i32 [[Y:%.*]], 2
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i32 %x, 1
diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll
index a1e84fad9a827..f788ff77bf2be 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -5009,10 +5009,9 @@ define i8 @test_replace_freeze_oneuse(i1 %x, i8 %y) {
define i8 @select_knownbits_simplify(i8 noundef %x) {
; CHECK-LABEL: define i8 @select_knownbits_simplify(
; CHECK-SAME: i8 noundef [[X:%.*]]) {
-; CHECK-NEXT: [[X_LO:%.*]] = and i8 [[X]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X_LO]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i8 [[X]] to i1
; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], -2
-; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i8 [[AND]], i8 0
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i8 0, i8 [[AND]]
; CHECK-NEXT: ret i8 [[RES]]
;
%x.lo = and i8 %x, 1
@@ -5025,11 +5024,10 @@ define i8 @select_knownbits_simplify(i8 noundef %x) {
define i8 @select_knownbits_simplify_nested(i8 noundef %x) {
; CHECK-LABEL: define i8 @select_knownbits_simplify_nested(
; CHECK-SAME: i8 noundef [[X:%.*]]) {
-; CHECK-NEXT: [[X_LO:%.*]] = and i8 [[X]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X_LO]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i8 [[X]] to i1
; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], -2
; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[AND]], [[AND]]
-; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i8 [[MUL]], i8 0
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i8 0, i8 [[MUL]]
; CHECK-NEXT: ret i8 [[RES]]
;
%x.lo = and i8 %x, 1
@@ -5043,10 +5041,9 @@ define i8 @select_knownbits_simplify_nested(i8 noundef %x) {
define i8 @select_knownbits_simplify_missing_noundef(i8 %x) {
; CHECK-LABEL: define i8 @select_knownbits_simplify_missing_noundef(
; CHECK-SAME: i8 [[X:%.*]]) {
-; CHECK-NEXT: [[X_LO:%.*]] = and i8 [[X]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X_LO]], 0
+; CHECK-NEXT: [[CMP:%.*]] = trunc i8 [[X]] to i1
; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], -2
-; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i8 [[AND]], i8 0
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i8 0, i8 [[AND]]
; CHECK-NEXT: ret i8 [[RES]]
;
%x.lo = and i8 %x, 1
diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll
index 006b06cfc7669..c9cabff237ad2 100644
--- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll
+++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll
@@ -205,8 +205,8 @@ define <2 x i1> @n6_vec(<2 x i64> %y, <2 x i32> %len) {
; New shift amount would be 16, minimal count of leading zeros in %x is 47. Ok.
define <2 x i1> @t7_vec(<2 x i32> %x, <2 x i32> %len) {
; CHECK-LABEL: @t7_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 1, i32 0>
-; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[X:%.*]] to <2 x i1>
+; CHECK-NEXT: [[T5:%.*]] = and <2 x i1> [[TMP1]], <i1 true, i1 false>
; CHECK-NEXT: ret <2 x i1> [[T5]]
;
%t0 = sub <2 x i32> <i32 32, i32 32>, %len
@@ -251,7 +251,7 @@ define i1 @t9_highest_bit(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[X:%.*]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[Y:%.*]], 63
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0
+; CHECK-NEXT: [[T5:%.*]] = trunc nuw i64 [[TMP3]] to i1
; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 64, %len
@@ -412,10 +412,10 @@ define i1 @t14_x_is_one(i32 %x, i32 %len) {
define <2 x i1> @t15_vec_x_is_one_or_zero(<2 x i64> %y, <2 x i32> %len) {
; CHECK-LABEL: @t15_vec_x_is_one_or_zero(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> [[Y:%.*]], splat (i64 48)
-; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> [[TMP1]], <i64 1, i64 0>
+; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> [[Y:%.*]], splat (i64 281474976710656)
; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[T5]]
+; CHECK-NEXT: [[T6:%.*]] = and <2 x i1> [[T5]], <i1 true, i1 false>
+; CHECK-NEXT: ret <2 x i1> [[T6]]
;
%t0 = sub <2 x i32> <i32 64, i32 64>, %len
%t1 = shl <2 x i32> <i32 1, i32 0>, %t0
@@ -429,7 +429,15 @@ define <2 x i1> @t15_vec_x_is_one_or_zero(<2 x i64> %y, <2 x i32> %len) {
}
define <2 x i1> @t16_vec_y_is_one_or_zero(<2 x i32> %x, <2 x i32> %len) {
; CHECK-LABEL: @t16_vec_y_is_one_or_zero(
-; CHECK-NEXT: ret <2 x i1> zeroinitializer
+; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> splat (i32 64), [[LEN:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], splat (i32 -16)
+; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>
+; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> <i64 1, i64 0>, [[T2_WIDE]]
+; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc nuw nsw <2 x i64> [[T3]] to <2 x i32>
+; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]
+; CHECK-NEXT: [[T5:%.*]] = trunc nuw <2 x i32> [[T4]] to <2 x i1>
+; CHECK-NEXT: ret <2 x i1> [[T5]]
;
%t0 = sub <2 x i32> <i32 64, i32 64>, %len
%t1 = shl <2 x i32> %x, %t0
diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll
index 2c508c0c47472..21ea443185dc3 100644
--- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll
+++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll
@@ -18,7 +18,7 @@ define i1 @t0_const_after_fold_lshr_shl_ne(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[Y:%.*]], [[TMP2]]
-; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0
+; CHECK-NEXT: [[T5:%.*]] = trunc nuw i64 [[TMP3]] to i1
; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
@@ -41,7 +41,7 @@ define <2 x i1> @t1_vec_splat(<2 x i32> %x, <2 x i64> %y, <2 x i32> %len) {
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], splat (i32 31)
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64>
; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i64> [[Y:%.*]], [[TMP2]]
-; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer
+; CHECK-NEXT: [[T5:%.*]] = trunc nuw <2 x i64> [[TMP3]] to <2 x i1>
; CHECK-NEXT: ret <2 x i1> [[T5]]
;
%t0 = sub <2 x i32> <i32 32, i32 32>, %len
@@ -213,7 +213,7 @@ define i1 @t6_oneuse3(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[Y]], [[TMP2]]
-; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0
+; CHECK-NEXT: [[T5:%.*]] = trunc nuw i64 [[TMP3]] to i1
; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
@@ -245,7 +245,7 @@ define i1 @t7_oneuse4(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[Y]], [[TMP2]]
-; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0
+; CHECK-NEXT: [[T5:%.*]] = trunc nuw i64 [[TMP3]] to i1
; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len ; no extra uses
diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
index 64ef1936fc2c1..4096d41d8d81f 100644
--- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
+++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
@@ -57,7 +57,7 @@ define i1 @t3_const_after_fold_lshr_shl_ne(i32 %x, i32 %y, i32 %len) {
; CHECK-LABEL: @t3_const_after_fold_lshr_shl_ne(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: [[T5:%.*]] = trunc nuw i32 [[TMP2]] to i1
; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
@@ -72,7 +72,7 @@ define i1 @t4_const_after_fold_lshr_shl_ne(i32 %x, i32 %y, i32 %len) {
; CHECK-LABEL: @t4_const_after_fold_lshr_shl_ne(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[Y:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
-; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: [[T5:%.*]] = trunc nuw i32 [[TMP2]] to i1
; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
diff --git a/llvm/test/Transforms/InstCombine/shift-direction-in-bit-test.ll b/llvm/test/Transforms/InstCombine/shift-direction-in-bit-test.ll
index 5d63545b08e9a..f2b32c5a47089 100644
--- a/llvm/test/Transforms/InstCombine/shift-direction-in-bit-test.ll
+++ b/llvm/test/Transforms/InstCombine/shift-direction-in-bit-test.ll
@@ -226,8 +226,8 @@ define i1 @t12_shift_of_const0(i32 %x, i32 %y, i32 %z) {
define i1 @t13_shift_of_const1(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @t13_shift_of_const1(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[Y:%.*]], 0
-; CHECK-NEXT: [[T1:%.*]] = and i32 [[Z:%.*]], 1
-; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[Z:%.*]], 1
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[TMP2]], 0
; CHECK-NEXT: [[T3:%.*]] = select i1 [[TMP1]], i1 true, i1 [[T2]]
; CHECK-NEXT: ret i1 [[T3]]
;
@@ -241,8 +241,8 @@ define i1 @t14_and_with_const0(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @t14_and_with_const0(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[Y:%.*]], 0
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[TMP2]], 0
-; CHECK-NEXT: [[T3:%.*]] = select i1 [[TMP1]], i1 true, i1 [[T2]]
+; CHECK-NEXT: [[T21:%.*]] = icmp eq i32 [[TMP2]], 0
+; CHECK-NEXT: [[T3:%.*]] = select i1 [[TMP1]], i1 true, i1 [[T21]]
; CHECK-NEXT: ret i1 [[T3]]
;
%t0 = shl i32 %x, %y
diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index 71914ec6393e6..3c77c27db39bd 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -398,7 +398,7 @@ define <2 x i1> @test28vec(<2 x i8> %x) {
define i8 @test28a(i8 %x, i8 %y) {
; CHECK-LABEL: @test28a(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[COND1_NOT:%.*]] = icmp sgt i8 [[X:%.*]], -1
+; CHECK-NEXT: [[COND1_NOT:%.*]] = icmp slt i8 [[X:%.*]], 0
; CHECK-NEXT: br i1 [[COND1_NOT]], label [[BB2:%.*]], label [[BB1:%.*]]
; CHECK: bb1:
; CHECK-NEXT: ret i8 1
diff --git a/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
index 3d47f99a9bc5e..3ec0e509476d4 100644
--- a/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
@@ -36,12 +36,9 @@ define <2 x i1> @and_cmp_is_trunc_even_with_poison_elt(<2 x i64> %a) {
ret <2 x i1> %r
}
-; TODO: This could be just 1 instruction (trunc), but our poison matching is incomplete.
-
define <2 x i1> @and_cmp_is_trunc_even_with_poison_elts(<2 x i64> %a) {
; CHECK-LABEL: @and_cmp_is_trunc_even_with_poison_elts(
-; CHECK-NEXT: [[T:%.*]] = and <2 x i64> [[A:%.*]], <i64 poison, i64 1>
-; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i64> [[T]], <i64 poison, i64 0>
+; CHECK-NEXT: [[R:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i1>
; CHECK-NEXT: ret <2 x i1> [[R]]
;
%t = and <2 x i64> %a, <i64 poison, i64 1>
diff --git a/llvm/test/Transforms/InstCombine/vector-casts.ll b/llvm/test/Transforms/InstCombine/vector-casts.ll
index 2a2448a9e6ad9..1227c8ea54f4c 100644
--- a/llvm/test/Transforms/InstCombine/vector-casts.ll
+++ b/llvm/test/Transforms/InstCombine/vector-casts.ll
@@ -36,12 +36,9 @@ define <2 x i1> @and_cmp_is_trunc_even_with_poison_elt(<2 x i64> %a) {
ret <2 x i1> %r
}
-; TODO: This could be just 1 instruction (trunc), but our poison matching is incomplete.
-
define <2 x i1> @and_cmp_is_trunc_even_with_poison_elts(<2 x i64> %a) {
; CHECK-LABEL: @and_cmp_is_trunc_even_with_poison_elts(
-; CHECK-NEXT: [[T:%.*]] = and <2 x i64> [[A:%.*]], <i64 poison, i64 1>
-; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i64> [[T]], <i64 poison, i64 0>
+; CHECK-NEXT: [[R:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i1>
; CHECK-NEXT: ret <2 x i1> [[R]]
;
%t = and <2 x i64> %a, <i64 poison, i64 1>
diff --git a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
index feb4be9e37050..94bf034daffee 100644
--- a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
+++ b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
@@ -3,10 +3,10 @@
define i8 @zext_or_icmp_icmp(i8 %a, i8 %b) {
; CHECK-LABEL: @zext_or_icmp_icmp(
-; CHECK-NEXT: [[MASK:%.*]] = and i8 [[A:%.*]], 1
-; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i8 [[MASK]], 0
-; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B:%.*]], 0
-; CHECK-NEXT: [[BOTHCOND:%.*]] = or i1 [[TOBOOL1]], [[TOBOOL2]]
+; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], 1
+; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B]], 0
+; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i8 [[B1:%.*]], 0
+; CHECK-NEXT: [[BOTHCOND:%.*]] = or i1 [[TOBOOL2]], [[TOBOOL1]]
; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[BOTHCOND]] to i8
; CHECK-NEXT: ret i8 [[ZEXT]]
;
@@ -20,10 +20,10 @@ define i8 @zext_or_icmp_icmp(i8 %a, i8 %b) {
define i8 @zext_or_icmp_icmp_logical(i8 %a, i8 %b) {
; CHECK-LABEL: @zext_or_icmp_icmp_logical(
-; CHECK-NEXT: [[MASK:%.*]] = and i8 [[A:%.*]], 1
-; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i8 [[MASK]], 0
-; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B:%.*]], 0
-; CHECK-NEXT: [[BOTHCOND:%.*]] = select i1 [[TOBOOL1]], i1 true, i1 [[TOBOOL2]]
+; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], 1
+; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B]], 0
+; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp eq i8 [[B1:%.*]], 0
+; CHECK-NEXT: [[BOTHCOND:%.*]] = select i1 [[TOBOOL2]], i1 true, i1 [[TOBOOL3]]
; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[BOTHCOND]] to i8
; CHECK-NEXT: ret i8 [[ZEXT]]
;
diff --git a/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll b/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll
index d842c4adcb74d..74caef5c6867e 100644
--- a/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll
+++ b/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll
@@ -122,15 +122,14 @@ define hidden void @runtime(ptr nocapture %a, ptr nocapture readonly %b, ptr noc
; CHECK-NEXT: [[CMP8_NOT:%.*]] = icmp eq i32 [[N:%.*]], 0
; CHECK-NEXT: br i1 [[CMP8_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]]
; CHECK: for.body.preheader:
-; CHECK-NEXT: [[XTRAITER:%.*]] = and i32 [[N]], 1
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[N]], 1
; CHECK-NEXT: br i1 [[TMP0]], label [[FOR_BODY_EPIL_PREHEADER:%.*]], label [[FOR_BODY_PREHEADER_NEW:%.*]]
; CHECK: for.body.preheader.new:
; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i32 [[N]], -2
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.cond.cleanup.loopexit.unr-lcssa:
-; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i32 [[XTRAITER]], 0
-; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_EPIL_PREHEADER]]
+; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = trunc i32 [[N]] to i1
+; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[FOR_BODY_EPIL_PREHEADER]], label [[FOR_COND_CLEANUP]]
; CHECK: for.body.epil.preheader:
; CHECK-NEXT: [[I_09_UNR:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INC_1:%.*]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA:%.*]] ]
; CHECK-NEXT: [[LCMP_MOD1:%.*]] = trunc i32 [[N]] to i1
diff --git a/llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll b/llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
index 91c74cbbbd290..756e2b9e29a45 100644
--- a/llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
+++ b/llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
@@ -27,7 +27,7 @@ define void @_Z3fn1v(ptr %r, ptr %a) #0 {
; CHECK-NEXT: [[TOBOOL20:%.*]] = icmp eq i32 [[T]], 0
; CHECK-NEXT: br i1 [[TOBOOL20]], label %[[FOR_END6:.*]], label %[[FOR_BODY:.*]]
; CHECK: [[FOR_COND_LOOPEXIT_LOOPEXIT:.*]]:
-; CHECK-NEXT: [[ADD_PTR_LCSSA:%.*]] = phi ptr [ [[ADD_PTR_LCSSA_UNR:%.*]], %[[FOR_BODY3_PROL_LOOPEXIT:.*]] ], [ [[ADD_PTR_1:%.*]], %[[FOR_INC_1:.*]] ]
+; CHECK-NEXT: [[ADD_PTR_LCSSA:%.*]] = phi ptr [ [[ADD_PTR_LCSSA_UNR:%.*]], %[[FOR_BODY3_PROL:.*]] ], [ [[ADD_PTR_1:%.*]], %[[FOR_INC_1:.*]] ]
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A_021:%.*]], i64 1
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[T2:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
@@ -48,10 +48,9 @@ define void @_Z3fn1v(ptr %r, ptr %a) #0 {
; CHECK-NEXT: [[TOBOOL215:%.*]] = icmp eq i32 [[T2]], 0
; CHECK-NEXT: br i1 [[TOBOOL215]], label %[[FOR_COND_LOOPEXIT]], label %[[FOR_BODY3_PREHEADER:.*]]
; CHECK: [[FOR_BODY3_PREHEADER]]:
-; CHECK-NEXT: [[XTRAITER:%.*]] = and i32 [[T2]], 1
-; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i32 [[XTRAITER]], 0
-; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label %[[FOR_BODY3_PROL_LOOPEXIT]], label %[[FOR_BODY3_PROL:.*]]
-; CHECK: [[FOR_BODY3_PROL]]:
+; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = trunc i32 [[T2]] to i1
+; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label %[[FOR_BODY3_PROL_LOOPEXIT:.*]], label %[[FOR_BODY3_PROL]]
+; CHECK: [[FOR_BODY3_PROL_LOOPEXIT]]:
; CHECK-NEXT: [[DEC18_PROL:%.*]] = add nsw i32 [[T2]], -1
; CHECK-NEXT: [[T3_PROL:%.*]] = load i8, ptr [[A_021]], align 1
; CHECK-NEXT: [[CMP_PROL:%.*]] = icmp eq i8 [[T3_PROL]], 0
@@ -66,8 +65,8 @@ define void @_Z3fn1v(ptr %r, ptr %a) #0 {
; CHECK: [[FOR_INC_PROL]]:
; CHECK-NEXT: [[INCDEC_PTR_PROL:%.*]] = getelementptr inbounds nuw i8, ptr [[A_021]], i64 1
; CHECK-NEXT: [[ADD_PTR_PROL:%.*]] = getelementptr inbounds nuw i8, ptr [[R_022]], i64 6
-; CHECK-NEXT: br label %[[FOR_BODY3_PROL_LOOPEXIT]]
-; CHECK: [[FOR_BODY3_PROL_LOOPEXIT]]:
+; CHECK-NEXT: br label %[[FOR_BODY3_PROL]]
+; CHECK: [[FOR_BODY3_PROL]]:
; CHECK-NEXT: [[ADD_PTR_LCSSA_UNR]] = phi ptr [ poison, %[[FOR_BODY3_PREHEADER]] ], [ [[ADD_PTR_PROL]], %[[FOR_INC_PROL]] ]
; CHECK-NEXT: [[DEC18_IN_UNR:%.*]] = phi i32 [ [[T2]], %[[FOR_BODY3_PREHEADER]] ], [ [[DEC18_PROL]], %[[FOR_INC_PROL]] ]
; CHECK-NEXT: [[R_117_UNR:%.*]] = phi ptr [ [[R_022]], %[[FOR_BODY3_PREHEADER]] ], [ [[ADD_PTR_PROL]], %[[FOR_INC_PROL]] ]
@@ -75,9 +74,9 @@ define void @_Z3fn1v(ptr %r, ptr %a) #0 {
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[T2]], 1
; CHECK-NEXT: br i1 [[TMP2]], label %[[FOR_COND_LOOPEXIT_LOOPEXIT]], label %[[FOR_BODY3:.*]]
; CHECK: [[FOR_BODY3]]:
-; CHECK-NEXT: [[DEC18_IN:%.*]] = phi i32 [ [[DEC18_1:%.*]], %[[FOR_INC_1]] ], [ [[DEC18_IN_UNR]], %[[FOR_BODY3_PROL_LOOPEXIT]] ]
-; CHECK-NEXT: [[R_117:%.*]] = phi ptr [ [[ADD_PTR_1]], %[[FOR_INC_1]] ], [ [[R_117_UNR]], %[[FOR_BODY3_PROL_LOOPEXIT]] ]
-; CHECK-NEXT: [[A_116:%.*]] = phi ptr [ [[INCDEC_PTR_1:%.*]], %[[FOR_INC_1]] ], [ [[A_116_UNR]], %[[FOR_BODY3_PROL_LOOPEXIT]] ]
+; CHECK-NEXT: [[DEC18_IN:%.*]] = phi i32 [ [[DEC18_1:%.*]], %[[FOR_INC_1]] ], [ [[DEC18_IN_UNR]], %[[FOR_BODY3_PROL]] ]
+; CHECK-NEXT: [[R_117:%.*]] = phi ptr [ [[ADD_PTR_1]], %[[FOR_INC_1]] ], [ [[R_117_UNR]], %[[FOR_BODY3_PROL]] ]
+; CHECK-NEXT: [[A_116:%.*]] = phi ptr [ [[INCDEC_PTR_1:%.*]], %[[FOR_INC_1]] ], [ [[A_116_UNR]], %[[FOR_BODY3_PROL]] ]
; CHECK-NEXT: [[T3:%.*]] = load i8, ptr [[A_116]], align 1
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[T3]], 0
; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[FOR_INC:.*]]
diff --git a/llvm/test/Transforms/PGOProfile/chr.ll b/llvm/test/Transforms/PGOProfile/chr.ll
index 12829512b3474..96ea9c071bfaf 100644
--- a/llvm/test/Transforms/PGOProfile/chr.ll
+++ b/llvm/test/Transforms/PGOProfile/chr.ll
@@ -198,9 +198,8 @@ define void @test_chr_2(ptr %i) !prof !14 {
; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB4]], label [[BB0_NONCHR:%.*]], !prof [[PROF17]]
; CHECK: bb0.nonchr:
-; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 1
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
-; CHECK-NEXT: br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF17]]
+; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[DOTFR1]] to i1
+; CHECK-NEXT: br i1 [[TMP4]], label [[BB1_NONCHR:%.*]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
; CHECK: bb2.nonchr:
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[DOTFR1]], 2
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
@@ -462,10 +461,9 @@ define i32 @test_chr_5(ptr %i, i32 %sum0) !prof !14 {
; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF17]]
; CHECK: bb0.nonchr:
-; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[DOTFR1]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
+; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[DOTFR1]] to i1
; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[SUM0]], 42
-; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM0]], i32 [[TMP7]], !prof [[PROF17]]
+; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP5]], i32 [[TMP7]], i32 [[SUM0]], !prof [[PROF16]]
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[DOTFR1]], 2
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 0
; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[SUM1_NONCHR]], 43
@@ -563,10 +561,9 @@ define i32 @test_chr_5_1(ptr %i, i32 %sum0) !prof !14 {
; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP7]], 0
; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF17]]
; CHECK: bb0.nonchr:
-; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[DOTFR1]], 1
-; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 0
+; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[DOTFR1]] to i1
; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[SUM0_FR]], 42
-; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP9]], i32 [[SUM0_FR]], i32 [[TMP10]], !prof [[PROF17]]
+; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP8]], i32 [[TMP10]], i32 [[SUM0_FR]], !prof [[PROF16]]
; CHECK-NEXT: [[TMP11:%.*]] = and i32 [[DOTFR1]], 2
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP11]], 0
; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[SUM1_NONCHR]], 43
@@ -875,9 +872,8 @@ define void @test_chr_8(ptr %i) !prof !14 {
; CHECK-LABEL: @test_chr_8(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF18:![0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i1
+; CHECK-NEXT: br i1 [[TMP1]], label [[BB0:%.*]], label [[BB1:%.*]], !prof [[PROF18:![0-9]+]]
; CHECK: bb0:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[BB1]]
@@ -1184,10 +1180,9 @@ define i32 @test_chr_12(ptr %i, i32 %sum0) !prof !14 {
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: br i1 [[TMP2]], label [[BB3:%.*]], label [[BB0:%.*]], !prof [[PROF17]]
; CHECK: bb0:
-; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[DOTFR2]], 1
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[DOTFR2]] to i1
; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[SUM0:%.*]], 42
-; CHECK-NEXT: [[SUM1:%.*]] = select i1 [[TMP4]], i32 [[SUM0]], i32 [[TMP5]], !prof [[PROF17]]
+; CHECK-NEXT: [[SUM1:%.*]] = select i1 [[TMP3]], i32 [[TMP5]], i32 [[SUM0]], !prof [[PROF16]]
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[DOTFR2]], 2
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[SUM1]], 43
@@ -1569,8 +1564,8 @@ define i32 @test_chr_17(i32 %i, i1 %j) !prof !14 {
; CHECK-NEXT: br i1 [[J:%.*]], label [[BB3:%.*]], label [[BB1:%.*]]
; CHECK: bbe:
; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[I]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TMP1]], label [[BB1]], label [[BB0:%.*]], !prof [[PROF17]]
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[I]] to i1
+; CHECK-NEXT: br i1 [[TMP1]], label [[BB0:%.*]], label [[BB1]], !prof [[PROF16]]
; CHECK: bb0:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: [[S:%.*]] = add nuw nsw i32 [[TMP0]], [[I]]
@@ -1762,15 +1757,14 @@ define i32 @test_chr_19(ptr %i, i32 %sum0) !prof !14 {
; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF17]]
; CHECK: bb0.nonchr:
-; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[DOTFR1]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
+; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[DOTFR1]] to i1
; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[SUM0]], 85
-; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM0]], i32 [[TMP7]], !prof [[PROF17]]
+; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP5]], i32 [[TMP7]], i32 [[SUM0]], !prof [[PROF16]]
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[DOTFR1]], 8
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 0
; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP9]], i32 44, i32 88, !prof [[PROF17]]
; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]
-; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF17]]
+; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP5]], i32 [[SUM4_NONCHR]], i32 [[SUM2_NONCHR]], !prof [[PROF16]]
; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3:
; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ], [ [[TMP3]], [[BB1]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ]
@@ -2516,9 +2510,8 @@ define void @test_chr_24(ptr %i) !prof !14 {
; CHECK-LABEL: @test_chr_24(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF21:![0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i1
+; CHECK-NEXT: br i1 [[TMP1]], label [[BB0:%.*]], label [[BB1:%.*]], !prof [[PROF21:![0-9]+]]
; CHECK: bb0:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[BB1]]
@@ -2561,9 +2554,8 @@ define void @test_chr_with_bbs_address_taken1(ptr %i) !prof !14 {
; CHECK-LABEL: @test_chr_with_bbs_address_taken1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF17]]
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i1
+; CHECK-NEXT: br i1 [[TMP1]], label [[BB0:%.*]], label [[BB1:%.*]], !prof [[PROF16]]
; CHECK: bb0:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[BB1]]
diff --git a/llvm/test/Transforms/PGOProfile/cspgo_profile_summary.ll b/llvm/test/Transforms/PGOProfile/cspgo_profile_summary.ll
index 7040bac6a4c43..3c9352a9a920f 100644
--- a/llvm/test/Transforms/PGOProfile/cspgo_profile_summary.ll
+++ b/llvm/test/Transforms/PGOProfile/cspgo_profile_summary.ll
@@ -66,10 +66,10 @@ for.end:
ret void
}
; PGOSUMMARY-LABEL: @bar
-; PGOSUMMARY: %even.odd = select i1 %tobool{{[0-9]*}}, ptr @even, ptr @odd
+; PGOSUMMARY: %odd.even = select i1 %tobool{{[0-9]*}}, ptr @odd, ptr @even
; PGOSUMMARY-SAME: !prof ![[BW_PGO_BAR:[0-9]+]]
; CSPGOSUMMARY-LABEL: @bar
-; CSPGOSUMMARY: %even.odd = select i1 %tobool{{[0-9]*}}, ptr @even, ptr @odd
+; CSPGOSUMMARY: %odd.even = select i1 %tobool{{[0-9]*}}, ptr @odd, ptr @even
; CSPGOSUMMARY-SAME: !prof ![[BW_CSPGO_BAR:[0-9]+]]
define internal fastcc i32 @cond(i32 %i) {
@@ -102,9 +102,9 @@ for.end:
ret void
}
; CSPGOSUMMARY-LABEL: @foo
-; CSPGOSUMMARY: %even.odd.i = select i1 %tobool.i{{[0-9]*}}, ptr @even, ptr @odd
+; CSPGOSUMMARY: %odd.even.i = select i1 %tobool.i{{[0-9]*}}, ptr @odd, ptr @even
; CSPGOSUMMARY-SAME: !prof ![[BW_CSPGO_BAR]]
-; CSPGOSUMMARY: %even.odd.i2 = select i1 %tobool.i{{[0-9]*}}, ptr @odd, ptr @even
+; CSPGOSUMMARY: %odd.even.i2 = select i1 %tobool.i{{[0-9]*}}, ptr @odd, ptr @even
; CSPGOSUMMARY-SAME: !prof ![[BW_CSPGO_BAR]]
declare dso_local i32 @bar_m(i32)
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
index bfed4b193562f..1159ebebf8538 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
@@ -11,12 +11,11 @@ define void @partial_unroll_forced(i32 %N, ptr %src, ptr noalias %dst) {
; CHECK-NEXT: [[CMP141:%.*]] = icmp sgt i32 [[N]], 0
; CHECK-NEXT: br i1 [[CMP141]], label [[LOOP_LATCH_PREHEADER:%.*]], label [[EXIT:%.*]]
; CHECK: loop.latch.preheader:
-; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64
-; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 1
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[N]], 1
; CHECK-NEXT: br i1 [[TMP0]], label [[LOOP_LATCH_EPIL_PREHEADER:%.*]], label [[LOOP_LATCH_PREHEADER_NEW:%.*]]
; CHECK: loop.latch.preheader.new:
-; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 2147483646
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[N]], 2147483646
+; CHECK-NEXT: [[UNROLL_ITER:%.*]] = zext nneg i32 [[TMP1]] to i64
; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]
; CHECK: loop.latch:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[LOOP_LATCH]] ]
@@ -37,8 +36,8 @@ define void @partial_unroll_forced(i32 %N, ptr %src, ptr noalias %dst) {
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[LOOP_LATCH]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: exit.loopexit.unr-lcssa:
-; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[XTRAITER]], 0
-; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[EXIT]], label [[LOOP_LATCH_EPIL_PREHEADER]]
+; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = trunc i32 [[N]] to i1
+; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[LOOP_LATCH_EPIL_PREHEADER]], label [[EXIT]]
; CHECK: loop.latch.epil.preheader:
; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER]] ], [ [[INDVARS_IV_NEXT_1]], [[EXIT_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[LCMP_MOD4:%.*]] = trunc i32 [[N]] to i1
@@ -83,12 +82,11 @@ define void @cse_matching_load_from_previous_unrolled_iteration(i32 %N, ptr %src
; CHECK-NEXT: [[CMP141:%.*]] = icmp sgt i32 [[N]], 0
; CHECK-NEXT: br i1 [[CMP141]], label [[LOOP_LATCH_PREHEADER:%.*]], label [[EXIT:%.*]]
; CHECK: loop.latch.preheader:
-; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64
-; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 1
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[N]], 1
; CHECK-NEXT: br i1 [[TMP0]], label [[LOOP_LATCH_EPIL_PREHEADER:%.*]], label [[LOOP_LATCH_PREHEADER_NEW:%.*]]
; CHECK: loop.latch.preheader.new:
-; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 2147483646
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[N]], 2147483646
+; CHECK-NEXT: [[UNROLL_ITER:%.*]] = zext nneg i32 [[TMP1]] to i64
; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]
; CHECK: loop.latch:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[LOOP_LATCH]] ]
@@ -111,8 +109,8 @@ define void @cse_matching_load_from_previous_unrolled_iteration(i32 %N, ptr %src
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[LOOP_LATCH]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: exit.loopexit.unr-lcssa:
-; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[XTRAITER]], 0
-; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[EXIT]], label [[LOOP_LATCH_EPIL_PREHEADER]]
+; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = trunc i32 [[N]] to i1
+; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[LOOP_LATCH_EPIL_PREHEADER]], label [[EXIT]]
; CHECK: loop.latch.epil.preheader:
; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER]] ], [ [[INDVARS_IV_NEXT_1]], [[EXIT_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[LCMP_MOD4:%.*]] = trunc i32 [[N]] to i1
diff --git a/llvm/test/Transforms/PhaseOrdering/pr40750.ll b/llvm/test/Transforms/PhaseOrdering/pr40750.ll
index 4a55d1cfab03d..0382528007b8c 100644
--- a/llvm/test/Transforms/PhaseOrdering/pr40750.ll
+++ b/llvm/test/Transforms/PhaseOrdering/pr40750.ll
@@ -7,9 +7,11 @@ define i32 @get(ptr nocapture readonly %arg) {
; CHECK-LABEL: @get(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[I1:%.*]] = load i8, ptr [[ARG:%.*]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[I1]], 3
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[TMP0]], 0
-; CHECK-NEXT: [[I9:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT: [[I3:%.*]] = trunc i8 [[I1]] to i1
+; CHECK-NEXT: [[I5:%.*]] = lshr i8 [[I1]], 1
+; CHECK-NEXT: [[I6:%.*]] = and i8 [[I5]], 1
+; CHECK-NEXT: [[I7:%.*]] = zext nneg i8 [[I6]] to i32
+; CHECK-NEXT: [[I9:%.*]] = select i1 [[I3]], i32 1, i32 [[I7]]
; CHECK-NEXT: ret i32 [[I9]]
;
bb:
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