[llvm] [VPlan] Fix miscompile when widening induction with loop-variant step (PR #206010)

[Florian Hahn via llvm-commits]

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@@ -0,0 +1,243 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S < %s | FileCheck %s
+
+
+; Loop with i8 induction using a variant step (zext of comparison).
+; InductionDescriptor classifies %iv as IK_IntInduction with step=1,
+; but the VPlan backedge step is loop-variant (zext i1 %cmp to i8).
+; Without the fix, ReplaceExtractsWithExitingIVValue replaces the iv
+; exit value with 'trunc i32 %n.vec to i8' (the vector iteration count)
+; instead of the actual last iv value, producing an off-by-one result.
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fhahn wrote:

Better to rewrite this w/o referencing 'the fix'. Perhaps just state that the live-out IV value needs to be extracted, not pre-computed.

It might also be clearer to clarify that the step is invariant except for the increment of the last iteration

https://github.com/llvm/llvm-project/pull/206010