[llvm] [RISCV] Move combineANDOfSETCCToCZERO to isel patterns. (PR #219318)

[Afonso Bordado via llvm-commits]

================
@@ -577,6 +976,107 @@ define i64 @select_w_minsize(i64 %true, i64 %false, i1 zeroext %c) minsize {
 ; RV64ZICOND-NEXT:    mv a0, a1
 ; RV64ZICOND-NEXT:  .LBB20_2:
 ; RV64ZICOND-NEXT:    ret
+;
+; RV32XVENTANACONDOPS-LABEL: select_w_minsize:
+; RV32XVENTANACONDOPS:       # %bb.0:
+; RV32XVENTANACONDOPS-NEXT:    bnez a4, .LBB20_2
+; RV32XVENTANACONDOPS-NEXT:  # %bb.1:
+; RV32XVENTANACONDOPS-NEXT:    mv a0, a2
+; RV32XVENTANACONDOPS-NEXT:    mv a1, a3
+; RV32XVENTANACONDOPS-NEXT:  .LBB20_2:
+; RV32XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: select_w_minsize:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    bnez a2, .LBB20_2
+; RV64XVENTANACONDOPS-NEXT:  # %bb.1:
+; RV64XVENTANACONDOPS-NEXT:    mv a0, a1
+; RV64XVENTANACONDOPS-NEXT:  .LBB20_2:
+; RV64XVENTANACONDOPS-NEXT:    ret
   %r = select i1 %c, i64 %true, i64 %false
   ret i64 %r
 }
+
+; (and (icmp x, C, eq), (icmp y, C, eq)) -> (czero.eqz (icmp x, 0, eq), (addi x, -C))
+define i32 @and_icmp_eq_non_zero(i64 %x, i64 %y) {
+; RV32ZICOND-LABEL: and_icmp_eq_non_zero:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    srli a3, a3, 31
+; RV32ZICOND-NEXT:    xori a0, a0, 1234
+; RV32ZICOND-NEXT:    or a0, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a3, a0
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: and_icmp_eq_non_zero:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    srli a1, a1, 63
+; RV64ZICOND-NEXT:    addi a0, a0, -1234
+; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
+; RV64ZICOND-NEXT:    ret
+;
+; RV32XVENTANACONDOPS-LABEL: and_icmp_eq_non_zero:
+; RV32XVENTANACONDOPS:       # %bb.0:
+; RV32XVENTANACONDOPS-NEXT:    srli a3, a3, 31
+; RV32XVENTANACONDOPS-NEXT:    xori a0, a0, 1234
+; RV32XVENTANACONDOPS-NEXT:    or a0, a0, a1
+; RV32XVENTANACONDOPS-NEXT:    vt.maskcn a0, a3, a0
+; RV32XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: and_icmp_eq_non_zero:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    srli a1, a1, 63
+; RV64XVENTANACONDOPS-NEXT:    addi a0, a0, -1234
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
+; RV64XVENTANACONDOPS-NEXT:    ret
+
+  %3 = icmp slt i64 %y, 0
+  %4 = icmp eq i64 %x, 1234
+  %5 = and i1 %4, %3
+  %6 = zext i1 %5 to i32
+  ret i32 %6
+}
+
+; (and (icmp x, C, ne), (icmp y, C, ne)) -> (czero.eqz (icmp x, 0, ne), (addi x, -C))
+define i32 @and_icmp_ne_non_zero(i64 %x, i64 %y) {
+; RV32ZICOND-LABEL: and_icmp_ne_non_zero:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xori a2, a2, 1234
+; RV32ZICOND-NEXT:    or a2, a2, a3
+; RV32ZICOND-NEXT:    xori a0, a0, 1234
+; RV32ZICOND-NEXT:    snez a2, a2
+; RV32ZICOND-NEXT:    or a0, a0, a1
+; RV32ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: and_icmp_ne_non_zero:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    addi a1, a1, -1234
+; RV64ZICOND-NEXT:    snez a1, a1
+; RV64ZICOND-NEXT:    addi a0, a0, -1234
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    ret
+;
+; RV32XVENTANACONDOPS-LABEL: and_icmp_ne_non_zero:
+; RV32XVENTANACONDOPS:       # %bb.0:
+; RV32XVENTANACONDOPS-NEXT:    xori a2, a2, 1234
+; RV32XVENTANACONDOPS-NEXT:    or a2, a2, a3
+; RV32XVENTANACONDOPS-NEXT:    xori a0, a0, 1234
+; RV32XVENTANACONDOPS-NEXT:    snez a2, a2
+; RV32XVENTANACONDOPS-NEXT:    or a0, a0, a1
+; RV32XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: and_icmp_ne_non_zero:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    addi a1, a1, -1234
+; RV64XVENTANACONDOPS-NEXT:    snez a1, a1
+; RV64XVENTANACONDOPS-NEXT:    addi a0, a0, -1234
+; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
+; RV64XVENTANACONDOPS-NEXT:    ret
+
+  %3 = icmp ne i64 %y, 1234
+  %4 = icmp ne i64 %x, 1234
+  %5 = and i1 %4, %3
+  %6 = zext i1 %5 to i32
+  ret i32 %6
+}
----------------
afonso360 wrote:

Sorry about this, I didn't notice this failure on the other PR. Just to double check this was caught when running the llvm-test-suite with RVV right? I can do that before submitting in future PR's

https://github.com/llvm/llvm-project/pull/219318